diff options
| author | Nanley Chery <nanley.g.chery@intel.com> | 2024-03-12 16:14:04 -0400 |
|---|---|---|
| committer | Marge Bot <emma+marge@anholt.net> | 2024-04-04 15:17:50 +0000 |
| commit | 8845f1e439bd0816216b39e75681692b8326ff11 (patch) | |
| tree | fbf584299e8584f1b749c814e560ab0c10513153 | |
| parent | 81d8c071aca4d953aa07f2e021e033aa2d501e6c (diff) | |
intel/isl: Remove inconsistency when encoding Tile64
We guard surface state encoding of tilings by macros when the encoded
value is not present on certain platforms. For gfx20 however, we added
these macros even when the existing ones for gfx125 were sufficient.
Remove the extra macros.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28284>
| -rw-r--r-- | src/intel/isl/isl_emit_cpb.c | 5 | ||||
| -rw-r--r-- | src/intel/isl/isl_emit_depth_stencil.c | 6 | ||||
| -rw-r--r-- | src/intel/isl/isl_surface_state.c | 6 |
3 files changed, 5 insertions, 12 deletions
diff --git a/src/intel/isl/isl_emit_cpb.c b/src/intel/isl/isl_emit_cpb.c index e57fa929167..bfc39282e61 100644 --- a/src/intel/isl/isl_emit_cpb.c +++ b/src/intel/isl/isl_emit_cpb.c @@ -42,11 +42,8 @@ __gen_combine_address(__attribute__((unused)) void *data, #if GFX_VERx10 >= 125 static const uint8_t isl_encode_tiling[] = { [ISL_TILING_4] = TILE4, -#if GFX_VER >= 20 - [ISL_TILING_64_XE2] = TILE64, -#else [ISL_TILING_64] = TILE64, -#endif + [ISL_TILING_64_XE2] = TILE64, }; #endif diff --git a/src/intel/isl/isl_emit_depth_stencil.c b/src/intel/isl/isl_emit_depth_stencil.c index dc23f5a6474..4d82f539824 100644 --- a/src/intel/isl/isl_emit_depth_stencil.c +++ b/src/intel/isl/isl_emit_depth_stencil.c @@ -60,12 +60,10 @@ static const uint32_t isl_encode_ds_surftype[] = { #if GFX_VER >= 9 static const uint8_t isl_encode_tiling[] = { -#if GFX_VER >= 20 - [ISL_TILING_4] = TILE4, - [ISL_TILING_64_XE2] = TILE64, -#elif GFX_VERx10 >= 125 +#if GFX_VERx10 >= 125 [ISL_TILING_4] = TILE4, [ISL_TILING_64] = TILE64, + [ISL_TILING_64_XE2] = TILE64, #else [ISL_TILING_Y0] = NONE, [ISL_TILING_SKL_Yf] = TILEYF, diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index 181a3dfd1b4..7cbf2774f02 100644 --- a/src/intel/isl/isl_surface_state.c +++ b/src/intel/isl/isl_surface_state.c @@ -44,12 +44,10 @@ __gen_combine_address(__attribute__((unused)) void *data, static const uint8_t isl_encode_tiling[] = { [ISL_TILING_LINEAR] = LINEAR, [ISL_TILING_X] = XMAJOR, -#if GFX_VER >= 20 - [ISL_TILING_4] = TILE4, - [ISL_TILING_64_XE2] = TILE64, -#elif GFX_VERx10 >= 125 +#if GFX_VERx10 >= 125 [ISL_TILING_4] = TILE4, [ISL_TILING_64] = TILE64, + [ISL_TILING_64_XE2] = TILE64, #else [ISL_TILING_Y0] = YMAJOR, [ISL_TILING_ICL_Yf] = YMAJOR, |