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-rw-r--r--src/mesa/drivers/dri/i965/brw_meta_fast_clear.c4
-rw-r--r--src/mesa/drivers/dri/i965/brw_state.h2
-rw-r--r--src/mesa/drivers/dri/i965/brw_state_cache.c2
-rw-r--r--src/mesa/drivers/dri/i965/brw_state_upload.c13
-rw-r--r--src/mesa/drivers/dri/i965/gen8_depth_state.c2
5 files changed, 11 insertions, 12 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
index d45f1e6d51..06916e28cb 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
@@ -400,7 +400,7 @@ use_rectlist(struct brw_context *brw, bool enable)
* _NEW_BUFFERS to make sure we emit new SURFACE_STATE with the new fast
* clear color value.
*/
- brw->state.dirty.mesa |= _NEW_LIGHT | _NEW_BUFFERS;
+ brw->NewGLState |= _NEW_LIGHT | _NEW_BUFFERS;
brw->ctx.NewDriverState |= BRW_NEW_FRAGMENT_PROGRAM;
}
@@ -602,7 +602,7 @@ brw_meta_fast_clear(struct brw_context *brw, struct gl_framebuffer *fb,
* color before resolve and sets irb->mt->fast_clear_state to UNRESOLVED if
* we render to it.
*/
- brw->state.dirty.mesa |= _NEW_BUFFERS;
+ brw->NewGLState |= _NEW_BUFFERS;
/* Set the custom state back to normal and dirty the same bits as above */
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index bb920b2216..cfa67b694d 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -155,7 +155,7 @@ extern const struct brw_tracked_state gen8_vs_state;
static inline bool
brw_state_dirty(struct brw_context *brw, GLuint mesa_flags, uint64_t brw_flags)
{
- return ((brw->state.dirty.mesa & mesa_flags) |
+ return ((brw->NewGLState & mesa_flags) |
(brw->ctx.NewDriverState & brw_flags)) != 0;
}
diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c b/src/mesa/drivers/dri/i965/brw_state_cache.c
index bfe7e51496..89508e4bd2 100644
--- a/src/mesa/drivers/dri/i965/brw_state_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_state_cache.c
@@ -399,7 +399,7 @@ brw_clear_cache(struct brw_context *brw, struct brw_cache *cache)
/* We need to make sure that the programs get regenerated, since
* any offsets leftover in brw_context will no longer be valid.
*/
- brw->state.dirty.mesa |= ~0;
+ brw->NewGLState |= ~0;
brw->ctx.NewDriverState |= ~0ull;
intel_batchbuffer_flush(brw);
}
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index e71c0ace15..e75ae2ee96 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -428,7 +428,7 @@ void brw_init_state( struct brw_context *brw )
brw_upload_initial_gpu_state(brw);
- brw->state.dirty.mesa = ~0;
+ brw->NewGLState = ~0;
brw->ctx.NewDriverState = ~0ull;
/* ~0 is a nonsensical value which won't match anything we program, so
@@ -613,7 +613,8 @@ static inline void
merge_ctx_state(struct brw_context *brw,
struct brw_state_flags *state)
{
- state->mesa |= brw->state.dirty.mesa;
+ state->mesa |= brw->NewGLState;
+ assert(brw->state.dirty.mesa == 0);
state->brw |= brw->ctx.NewDriverState;
assert(brw->state.dirty.brw == 0ull);
}
@@ -639,12 +640,9 @@ brw_upload_pipeline_state(struct brw_context *brw,
static int dirty_count = 0;
struct brw_state_flags state = brw->state.pipelines[pipeline];
- brw_state->mesa |= brw->NewGLState;
- brw->NewGLState = 0;
-
if (0) {
/* Always re-emit all state. */
- brw_state->mesa |= ~0;
+ brw->NewGLState = ~0;
ctx->NewDriverState = ~0ull;
}
@@ -755,13 +753,14 @@ brw_pipeline_state_finished(struct brw_context *brw,
/* Save all dirty state into the other pipelines */
for (int i = 0; i < BRW_NUM_PIPELINES; i++) {
if (i != pipeline) {
- brw->state.pipelines[i].mesa |= state->mesa;
+ brw->state.pipelines[i].mesa |= brw->NewGLState;
brw->state.pipelines[i].brw |= brw->ctx.NewDriverState;
} else {
memset(&brw->state.pipelines[i], 0, sizeof(struct brw_state_flags));
}
}
+ brw->NewGLState = 0;
brw->ctx.NewDriverState = 0ull;
memset(state, 0, sizeof(*state));
}
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index c6494c9eca..490dd97182 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -504,5 +504,5 @@ gen8_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
*
* Setting _NEW_DEPTH and _NEW_BUFFERS covers it, but is rather overkill.
*/
- brw->state.dirty.mesa |= _NEW_DEPTH | _NEW_BUFFERS;
+ brw->NewGLState |= _NEW_DEPTH | _NEW_BUFFERS;
}