diff options
| author | Jordan Justen <jordan.l.justen@intel.com> | 2014-05-28 10:19:37 -0700 |
|---|---|---|
| committer | Jordan Justen <jordan.l.justen@intel.com> | 2014-07-14 17:38:22 -0700 |
| commit | 9d08d6180fa69108a4245bbcbe905664064735ce (patch) | |
| tree | 10fdc32ff12a6f378a9c6d86b612d7e5a7d42063 | |
| parent | d042576adb1493992cdf98c804c11e4124b2fbe2 (diff) | |
i965/gen6: Stencil/hiz needs an offset for LOD > 0
Since gen6 separate stencil & hiz only supports LOD0, we need to
program an offset to the LOD when emitting the separate stencil/hiz.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen6_blorp.cpp | 10 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen6_depth_state.c | 32 |
2 files changed, 39 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp index 5a56442afd..4dab56947d 100644 --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp @@ -871,13 +871,21 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw, /* 3DSTATE_HIER_DEPTH_BUFFER */ { struct intel_mipmap_tree *hiz_mt = params->depth.mt->hiz_mt; + uint32_t offset = 0; + + if (hiz_mt->non_mip_arrays) { + offset = intel_miptree_get_aligned_offset(hiz_mt, + hiz_mt->level[lod].level_x, + hiz_mt->level[lod].level_y, + false); + } BEGIN_BATCH(3); OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2)); OUT_BATCH(hiz_mt->pitch - 1); OUT_RELOC(hiz_mt->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, - 0); + offset); ADVANCE_BATCH(); } diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c b/src/mesa/drivers/dri/i965/gen6_depth_state.c index b58f9709b1..f83291c006 100644 --- a/src/mesa/drivers/dri/i965/gen6_depth_state.c +++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c @@ -183,12 +183,21 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw, /* Emit hiz buffer. */ if (hiz) { struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_mt; + uint32_t offset = 0; + + if (hiz_mt->non_mip_arrays) { + offset = intel_miptree_get_aligned_offset(hiz_mt, + hiz_mt->level[lod].level_x, + hiz_mt->level[lod].level_y, + false); + } + BEGIN_BATCH(3); OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2)); OUT_BATCH(hiz_mt->pitch - 1); OUT_RELOC(hiz_mt->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, - 0); + offset); ADVANCE_BATCH(); } else { BEGIN_BATCH(3); @@ -200,6 +209,25 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw, /* Emit stencil buffer. */ if (separate_stencil) { + uint32_t offset = 0; + + if (stencil_mt->non_mip_arrays) { + if (stencil_mt->format == MESA_FORMAT_S_UINT8) { + /* Note: we can't compute the stencil offset using + * intel_region_get_aligned_offset(), because stencil_region claims + * that the region is untiled even though it's W tiled. + */ + offset = + stencil_mt->level[lod].level_y * stencil_mt->pitch + + stencil_mt->level[lod].level_x * 64; + } else { + offset = intel_miptree_get_aligned_offset(stencil_mt, + stencil_mt->level[lod].level_x, + stencil_mt->level[lod].level_y, + false); + } + } + BEGIN_BATCH(3); OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2)); /* The stencil buffer has quirky pitch requirements. From Vol 2a, @@ -210,7 +238,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw, OUT_BATCH(2 * stencil_mt->pitch - 1); OUT_RELOC(stencil_mt->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, - 0); + offset); ADVANCE_BATCH(); } else { BEGIN_BATCH(3); |