~jljusten/libdrm - jljusten's DRM repo

Age	Commit message (Collapse)	Author	Files	Lines
2012-06-17	radeon/surface: free version after using it.	Dave Airlie	1	-0/+2
	fixes leak in valgrind. Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-06-12	radeon: force 1D array mode for z/stencil surface	Jerome Glisse	1	-0/+37
	On r6xx or evergreen z/stencil surface don't support linear or linear aligned surface, force 1D tiled mode for those. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-06-11	radeon: enabled 2D tiling for evergreen only on fixed kernel	Jerome Glisse	1	-1/+1
	Due to a kernel bug, enabled 2D tiling for evergreen only on newer fixed kernel. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-06-11	radeon: always properly initialize stencil_offset field	Jerome Glisse	1	-3/+3
	Reported-by: Vadim Girlin <vadimgirlin@gmail.com> Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-06-07	radeon: fall back to 1D tiling only with broken kernels	Alex Deucher	1	-7/+21
	Certain cards report the the wrong bank setup which causes surface init to fail in the ddx and leads to no accel. If we hit an invalid tiling parameter, just set a default value and disable 2D tiling. Should fix: https://bugs.freedesktop.org/show_bug.cgi?id=43448 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-05-16	radeon: Add Southern Islands PCI IDs.	Michel Dänzer	1	-0/+3
	Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-03-20	radeon: add TN surface support	Alex Deucher	1	-0/+1
	Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-02-13	radeon: fix pitch alignment for scanout buffer	Jerome Glisse	1	-1/+13
	Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-02-03	radeon: fix surface API for good before anyone start relying on it	Jerome Glisse	1	-17/+8
	The mipmap level computation was wrong, we need to know the block width, height, depth of compressed texture to properly compute this. Change API to provide block width, height, depth instead of nblk_x, nblk_y, nblk_z. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-02-02	radeon: surface fix macro -> micro tile fallback	Jerome Glisse	1	-58/+67
	We need to force 1D tiling only on old kernel the fallback was broken along the way. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-02-01	radeon: add surface allocator helper v10	Jerome Glisse	1	-0/+995
	The surface allocator is able to build complete miptree when allocating surface for r600/r700/evergreen/northern islands GPU family. It also compute bo size and alignment for render buffer, depth buffer and scanout buffer. v2 fix r6xx/r7xx 2D tiling width align computation v3 add tile split support and fix 1d texture alignment v4 rework to more properly support compressed format, split surface pixel size and surface element size in separate fields v5 support texture array (still issue on r6xx) v6 split surface value computation and mipmap tree building, rework eg and newer computation v7 add a check for tile split and 2d tiled v8 initialize mode value before testing it in all case, reenable 2D macro tile mode on r6xx for cubemap and array. Fix cubemap to force array size to the number of face. v9 fix handling of stencil buffer on evergreen v10 on evergreen depth buffer need to have enough room for a stencil buffer just after depth one Signed-off-by: Jerome Glisse <jglisse@redhat.com>