diff options
Diffstat (limited to 'shared-core')
| -rw-r--r-- | shared-core/mga_drv.h | 36 | ||||
| -rw-r--r-- | shared-core/r128_cce.c | 1 | ||||
| -rw-r--r-- | shared-core/r128_drv.h | 34 | ||||
| -rw-r--r-- | shared-core/r128_state.c | 118 | ||||
| -rw-r--r-- | shared-core/radeon_cp.c | 63 | ||||
| -rw-r--r-- | shared-core/radeon_drv.h | 79 | ||||
| -rw-r--r-- | shared-core/radeon_mem.c | 22 |
7 files changed, 175 insertions, 178 deletions
diff --git a/shared-core/mga_drv.h b/shared-core/mga_drv.h index 0e650b42..a5085b06 100644 --- a/shared-core/mga_drv.h +++ b/shared-core/mga_drv.h @@ -90,14 +90,14 @@ typedef struct drm_mga_private { unsigned int texture_offset; unsigned int texture_size; - drm_local_map_t *sarea; - drm_local_map_t *fb; - drm_local_map_t *mmio; - drm_local_map_t *status; - drm_local_map_t *warp; - drm_local_map_t *primary; - drm_local_map_t *buffers; - drm_local_map_t *agp_textures; + drm_map_t *sarea; + drm_map_t *fb; + drm_map_t *mmio; + drm_map_t *status; + drm_map_t *warp; + drm_map_t *primary; + drm_map_t *buffers; + drm_map_t *agp_textures; } drm_mga_private_t; /* mga_dma.c */ @@ -131,30 +131,32 @@ extern int mga_getparam( DRM_IOCTL_ARGS ); extern int mga_warp_install_microcode( drm_mga_private_t *dev_priv ); extern int mga_warp_init( drm_mga_private_t *dev_priv ); -#define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER(dev_priv->primary) +#define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER() + -#if defined(__linux__) && defined(__alpha__) #define MGA_BASE( reg ) ((unsigned long)(dev_priv->mmio->handle)) #define MGA_ADDR( reg ) (MGA_BASE(reg) + reg) #define MGA_DEREF( reg ) *(volatile u32 *)MGA_ADDR( reg ) #define MGA_DEREF8( reg ) *(volatile u8 *)MGA_ADDR( reg ) +#ifdef __alpha__ #define MGA_READ( reg ) (_MGA_READ((u32 *)MGA_ADDR(reg))) #define MGA_READ8( reg ) (_MGA_READ((u8 *)MGA_ADDR(reg))) -#define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(dev_priv->mmio); MGA_DEREF( reg ) = val; } while (0) -#define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(dev_priv->mmio); MGA_DEREF8( reg ) = val; } while (0) +#define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0) +#define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8( reg ) = val; } while (0) static inline u32 _MGA_READ(u32 *addr) { - DRM_READMEMORYBARRIER(dev_priv->mmio); + DRM_READMEMORYBARRIER(); return *(volatile u32 *)addr; } + #else -#define MGA_READ8( reg ) DRM_READ8(dev_priv->mmio, (reg)) -#define MGA_READ( reg ) DRM_READ32(dev_priv->mmio, (reg)) -#define MGA_WRITE8( reg, val ) DRM_WRITE8(dev_priv->mmio, (reg), (val)) -#define MGA_WRITE( reg, val ) DRM_WRITE32(dev_priv->mmio, (reg), (val)) +#define MGA_READ( reg ) MGA_DEREF( reg ) +#define MGA_READ8( reg ) MGA_DEREF8( reg ) +#define MGA_WRITE( reg, val ) do { MGA_DEREF( reg ) = val; } while (0) +#define MGA_WRITE8( reg, val ) do { MGA_DEREF8( reg ) = val; } while (0) #endif #define DWGREG0 0x1c00 diff --git a/shared-core/r128_cce.c b/shared-core/r128_cce.c index 8d305b75..5175885e 100644 --- a/shared-core/r128_cce.c +++ b/shared-core/r128_cce.c @@ -579,7 +579,6 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init ) (dev_priv->ring.size / sizeof(u32)) - 1; dev_priv->ring.high_mark = 128; - dev_priv->ring.ring_rptr = dev_priv->ring_rptr; dev_priv->sarea_priv->last_frame = 0; R128_WRITE( R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame ); diff --git a/shared-core/r128_drv.h b/shared-core/r128_drv.h index 5e6f1215..763fcb3a 100644 --- a/shared-core/r128_drv.h +++ b/shared-core/r128_drv.h @@ -34,8 +34,8 @@ #ifndef __R128_DRV_H__ #define __R128_DRV_H__ -#define GET_RING_HEAD(ring) DRM_READ32( (ring)->ring_rptr, 0 ) /* (ring)->head */ -#define SET_RING_HEAD(ring,val) DRM_WRITE32( (ring)->ring_rptr, 0, (val) ) /* (ring)->head */ +#define GET_RING_HEAD(ring) DRM_READ32( (volatile u32 *) (ring)->head ) +#define SET_RING_HEAD(ring,val) DRM_WRITE32( (volatile u32 *) (ring)->head, (val) ) typedef struct drm_r128_freelist { unsigned int age; @@ -56,7 +56,6 @@ typedef struct drm_r128_ring_buffer { int space; int high_mark; - drm_local_map_t *ring_rptr; } drm_r128_ring_buffer_t; typedef struct drm_r128_private { @@ -99,13 +98,13 @@ typedef struct drm_r128_private { u32 depth_pitch_offset_c; u32 span_pitch_offset_c; - drm_local_map_t *sarea; - drm_local_map_t *fb; - drm_local_map_t *mmio; - drm_local_map_t *cce_ring; - drm_local_map_t *ring_rptr; - drm_local_map_t *buffers; - drm_local_map_t *agp_textures; + drm_map_t *sarea; + drm_map_t *fb; + drm_map_t *mmio; + drm_map_t *cce_ring; + drm_map_t *ring_rptr; + drm_map_t *buffers; + drm_map_t *agp_textures; } drm_r128_private_t; typedef struct drm_r128_buf_priv { @@ -371,10 +370,15 @@ extern int r128_cce_indirect( DRM_IOCTL_ARGS ); #define R128_PERFORMANCE_BOXES 0 -#define R128_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) -#define R128_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) -#define R128_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) -#define R128_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) + +#define R128_BASE(reg) ((unsigned long)(dev_priv->mmio->handle)) +#define R128_ADDR(reg) (R128_BASE( reg ) + reg) + +#define R128_READ(reg) DRM_READ32( (volatile u32 *) R128_ADDR(reg) ) +#define R128_WRITE(reg,val) DRM_WRITE32( (volatile u32 *) R128_ADDR(reg), (val) ) + +#define R128_READ8(reg) DRM_READ8( (volatile u8 *) R128_ADDR(reg) ) +#define R128_WRITE8(reg,val) DRM_WRITE8( (volatile u8 *) R128_ADDR(reg), (val) ) #define R128_WRITE_PLL(addr,val) \ do { \ @@ -449,7 +453,7 @@ do { \ #if defined(__powerpc__) #define r128_flush_write_combine() (void) GET_RING_HEAD( &dev_priv->ring ) #else -#define r128_flush_write_combine() DRM_WRITEMEMORYBARRIER(dev_priv->ring_rptr) +#define r128_flush_write_combine() DRM_WRITEMEMORYBARRIER() #endif diff --git a/shared-core/r128_state.c b/shared-core/r128_state.c index 20307c04..68f73061 100644 --- a/shared-core/r128_state.c +++ b/shared-core/r128_state.c @@ -896,7 +896,7 @@ static int r128_cce_dispatch_write_span( drm_device_t *dev, int count, x, y; u32 *buffer; u8 *mask; - int i, buffer_size, mask_size; + int i; RING_LOCALS; DRM_DEBUG( "\n" ); @@ -908,25 +908,25 @@ static int r128_cce_dispatch_write_span( drm_device_t *dev, return DRM_ERR(EFAULT); } - buffer_size = depth->n * sizeof(u32); - buffer = DRM_MALLOC( buffer_size ); + buffer = DRM_MALLOC( depth->n * sizeof(u32) ); if ( buffer == NULL ) return DRM_ERR(ENOMEM); - if ( DRM_COPY_FROM_USER( buffer, depth->buffer, buffer_size ) ) { - DRM_FREE( buffer, buffer_size); + if ( DRM_COPY_FROM_USER( buffer, depth->buffer, + depth->n * sizeof(u32) ) ) { + DRM_FREE( buffer ); return DRM_ERR(EFAULT); } - mask_size = depth->n * sizeof(u8); if ( depth->mask ) { - mask = DRM_MALLOC( mask_size ); + mask = DRM_MALLOC( depth->n * sizeof(u8) ); if ( mask == NULL ) { - DRM_FREE( buffer, buffer_size ); + DRM_FREE( buffer ); return DRM_ERR(ENOMEM); } - if ( DRM_COPY_FROM_USER( mask, depth->mask, mask_size ) ) { - DRM_FREE( buffer, buffer_size ); - DRM_FREE( mask, mask_size ); + if ( DRM_COPY_FROM_USER( mask, depth->mask, + depth->n * sizeof(u8) ) ) { + DRM_FREE( buffer ); + DRM_FREE( mask ); return DRM_ERR(EFAULT); } @@ -953,7 +953,7 @@ static int r128_cce_dispatch_write_span( drm_device_t *dev, } } - DRM_FREE( mask, mask_size ); + DRM_FREE( mask ); } else { for ( i = 0 ; i < count ; i++, x++ ) { BEGIN_RING( 6 ); @@ -977,7 +977,7 @@ static int r128_cce_dispatch_write_span( drm_device_t *dev, } } - DRM_FREE( buffer, buffer_size ); + DRM_FREE( buffer ); return 0; } @@ -989,62 +989,60 @@ static int r128_cce_dispatch_write_pixels( drm_device_t *dev, int count, *x, *y; u32 *buffer; u8 *mask; - int i, xbuf_size, ybuf_size, buffer_size, mask_size; + int i; RING_LOCALS; DRM_DEBUG( "\n" ); count = depth->n; - xbuf_size = count * sizeof(*x); - ybuf_size = count * sizeof(*y); - x = DRM_MALLOC( xbuf_size ); + x = DRM_MALLOC( count * sizeof(*x) ); if ( x == NULL ) { return DRM_ERR(ENOMEM); } - y = DRM_MALLOC( ybuf_size ); + y = DRM_MALLOC( count * sizeof(*y) ); if ( y == NULL ) { - DRM_FREE( x, xbuf_size ); + DRM_FREE( x ); return DRM_ERR(ENOMEM); } - if ( DRM_COPY_FROM_USER( x, depth->x, xbuf_size ) ) { - DRM_FREE( x, xbuf_size ); - DRM_FREE( y, ybuf_size ); + if ( DRM_COPY_FROM_USER( x, depth->x, count * sizeof(int) ) ) { + DRM_FREE( x ); + DRM_FREE( y ); return DRM_ERR(EFAULT); } - if ( DRM_COPY_FROM_USER( y, depth->y, xbuf_size ) ) { - DRM_FREE( x, xbuf_size ); - DRM_FREE( y, ybuf_size ); + if ( DRM_COPY_FROM_USER( y, depth->y, count * sizeof(int) ) ) { + DRM_FREE( x ); + DRM_FREE( y ); return DRM_ERR(EFAULT); } - buffer_size = depth->n * sizeof(u32); - buffer = DRM_MALLOC( buffer_size ); + buffer = DRM_MALLOC( depth->n * sizeof(u32) ); if ( buffer == NULL ) { - DRM_FREE( x, xbuf_size ); - DRM_FREE( y, ybuf_size ); + DRM_FREE( x ); + DRM_FREE( y ); return DRM_ERR(ENOMEM); } - if ( DRM_COPY_FROM_USER( buffer, depth->buffer, buffer_size ) ) { - DRM_FREE( x, xbuf_size ); - DRM_FREE( y, ybuf_size ); - DRM_FREE( buffer, buffer_size ); + if ( DRM_COPY_FROM_USER( buffer, depth->buffer, + depth->n * sizeof(u32) ) ) { + DRM_FREE( x ); + DRM_FREE( y ); + DRM_FREE( buffer ); return DRM_ERR(EFAULT); } if ( depth->mask ) { - mask_size = depth->n * sizeof(u8); - mask = DRM_MALLOC( mask_size ); + mask = DRM_MALLOC( depth->n * sizeof(u8) ); if ( mask == NULL ) { - DRM_FREE( x, xbuf_size ); - DRM_FREE( y, ybuf_size ); - DRM_FREE( buffer, buffer_size ); + DRM_FREE( x ); + DRM_FREE( y ); + DRM_FREE( buffer ); return DRM_ERR(ENOMEM); } - if ( DRM_COPY_FROM_USER( mask, depth->mask, mask_size ) ) { - DRM_FREE( x, xbuf_size ); - DRM_FREE( y, ybuf_size ); - DRM_FREE( buffer, buffer_size ); - DRM_FREE( mask, mask_size ); + if ( DRM_COPY_FROM_USER( mask, depth->mask, + depth->n * sizeof(u8) ) ) { + DRM_FREE( x ); + DRM_FREE( y ); + DRM_FREE( buffer ); + DRM_FREE( mask ); return DRM_ERR(EFAULT); } @@ -1071,7 +1069,7 @@ static int r128_cce_dispatch_write_pixels( drm_device_t *dev, } } - DRM_FREE( mask, mask_size ); + DRM_FREE( mask ); } else { for ( i = 0 ; i < count ; i++ ) { BEGIN_RING( 6 ); @@ -1095,9 +1093,9 @@ static int r128_cce_dispatch_write_pixels( drm_device_t *dev, } } - DRM_FREE( x, xbuf_size ); - DRM_FREE( y, ybuf_size ); - DRM_FREE( buffer, buffer_size ); + DRM_FREE( x ); + DRM_FREE( y ); + DRM_FREE( buffer ); return 0; } @@ -1148,7 +1146,7 @@ static int r128_cce_dispatch_read_pixels( drm_device_t *dev, { drm_r128_private_t *dev_priv = dev->dev_private; int count, *x, *y; - int i, xbuf_size, ybuf_size; + int i; RING_LOCALS; DRM_DEBUG( "%s\n", __FUNCTION__ ); @@ -1157,25 +1155,23 @@ static int r128_cce_dispatch_read_pixels( drm_device_t *dev, count = dev_priv->depth_pitch; } - xbuf_size = count * sizeof(*x); - ybuf_size = count * sizeof(*y); - x = DRM_MALLOC( xbuf_size ); + x = DRM_MALLOC( count * sizeof(*x) ); if ( x == NULL ) { return DRM_ERR(ENOMEM); } - y = DRM_MALLOC( ybuf_size ); + y = DRM_MALLOC( count * sizeof(*y) ); if ( y == NULL ) { - DRM_FREE( x, xbuf_size ); + DRM_FREE( x ); return DRM_ERR(ENOMEM); } - if ( DRM_COPY_FROM_USER( x, depth->x, xbuf_size ) ) { - DRM_FREE( x, xbuf_size ); - DRM_FREE( y, ybuf_size ); + if ( DRM_COPY_FROM_USER( x, depth->x, count * sizeof(int) ) ) { + DRM_FREE( x ); + DRM_FREE( y ); return DRM_ERR(EFAULT); } - if ( DRM_COPY_FROM_USER( y, depth->y, ybuf_size ) ) { - DRM_FREE( x, xbuf_size ); - DRM_FREE( y, ybuf_size ); + if ( DRM_COPY_FROM_USER( y, depth->y, count * sizeof(int) ) ) { + DRM_FREE( x ); + DRM_FREE( y ); return DRM_ERR(EFAULT); } @@ -1203,8 +1199,8 @@ static int r128_cce_dispatch_read_pixels( drm_device_t *dev, ADVANCE_RING(); } - DRM_FREE( x, xbuf_size ); - DRM_FREE( y, ybuf_size ); + DRM_FREE( x ); + DRM_FREE( y ); return 0; } diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c index 89c9eab1..b4d0e4b6 100644 --- a/shared-core/radeon_cp.c +++ b/shared-core/radeon_cp.c @@ -36,11 +36,6 @@ #define RADEON_FIFO_DEBUG 0 -#if defined(__alpha__) || defined(__powerpc__) -# define PCIGART_ENABLED -#else -# undef PCIGART_ENABLED -#endif /* CP microcode (from ATI) */ @@ -885,6 +880,7 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev, /* Set the write pointer delay */ RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 ); + RADEON_READ( RADEON_CP_RB_WPTR_DELAY ); /* read back to propagate */ /* Initialize the ring buffer's read and write pointers */ cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR ); @@ -926,11 +922,11 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev, RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 ); /* Writeback doesn't seem to work everywhere, test it first */ - DRM_WRITE32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0 ); + DRM_WRITE32( &dev_priv->scratch[1], 0 ); RADEON_WRITE( RADEON_SCRATCH_REG1, 0xdeadbeef ); for ( tmp = 0 ; tmp < dev_priv->usec_timeout ; tmp++ ) { - if ( DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1) ) == 0xdeadbeef ) + if ( DRM_READ32( &dev_priv->scratch[1] ) == 0xdeadbeef ) break; DRM_UDELAY( 1 ); } @@ -990,17 +986,6 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) dev_priv->is_pci = init->is_pci; -#if !defined(PCIGART_ENABLED) - /* PCI support is not 100% working, so we disable it here. - */ - if ( dev_priv->is_pci ) { - DRM_ERROR( "PCI GART not yet supported for Radeon!\n" ); - dev->dev_private = (void *)dev_priv; - radeon_do_cleanup_cp(dev); - return DRM_ERR(EINVAL); - } -#endif - if ( dev_priv->is_pci && !dev->sg ) { DRM_ERROR( "PCI GART memory not allocated!\n" ); dev->dev_private = (void *)dev_priv; @@ -1217,7 +1202,6 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) (dev_priv->ring.size / sizeof(u32)) - 1; dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; - dev_priv->ring.ring_rptr = dev_priv->ring_rptr; #if __REALLY_HAVE_SG if ( dev_priv->is_pci ) { @@ -1355,9 +1339,6 @@ int radeon_cp_stop( DRM_IOCTL_ARGS ) DRM_COPY_FROM_USER_IOCTL( stop, (drm_radeon_cp_stop_t *)data, sizeof(stop) ); - if (!dev_priv->cp_running) - return 0; - /* Flush any pending CP commands. This ensures any outstanding * commands are exectuted by the engine before we turn it off. */ @@ -1385,39 +1366,6 @@ int radeon_cp_stop( DRM_IOCTL_ARGS ) return 0; } - -void radeon_do_release( drm_device_t *dev ) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - int ret; - - if (dev_priv) { - if (dev_priv->cp_running) { - /* Stop the cp */ - while ((ret = radeon_do_cp_idle( dev_priv )) != 0) { - DRM_DEBUG("radeon_do_cp_idle %d\n", ret); -#ifdef __linux__ - schedule(); -#else - tsleep(&ret, PZERO, "rdnrel", 1); -#endif - } - radeon_do_cp_stop( dev_priv ); - radeon_do_engine_reset( dev ); - } - - /* Disable *all* interrupts */ - RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 ); - - /* Free memory heap structures */ - radeon_mem_takedown( &(dev_priv->agp_heap) ); - radeon_mem_takedown( &(dev_priv->fb_heap) ); - - /* deallocate kernel resources */ - radeon_do_cleanup_cp( dev ); - } -} - /* Just reset the CP ring. Called as part of an X Server engine reset. */ int radeon_cp_reset( DRM_IOCTL_ARGS ) @@ -1449,6 +1397,9 @@ int radeon_cp_idle( DRM_IOCTL_ARGS ) LOCK_TEST_WITH_RETURN( dev ); +/* if (dev->irq) */ +/* radeon_emit_and_wait_irq( dev ); */ + return radeon_do_cp_idle( dev_priv ); } @@ -1543,7 +1494,7 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev ) drm_buf_t *buf; int i, t; int start; - u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)); + u32 done_age = DRM_READ32(&dev_priv->scratch[1]); if ( ++dev_priv->last_buf >= dma->buf_count ) dev_priv->last_buf = 0; diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index 502ba89b..635ad14b 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -31,8 +31,8 @@ #ifndef __RADEON_DRV_H__ #define __RADEON_DRV_H__ -#define GET_RING_HEAD(ring) DRM_READ32( (ring)->ring_rptr, 0 ) /* (ring)->head */ -#define SET_RING_HEAD(ring,val) DRM_WRITE32( (ring)->ring_rptr, 0, (val) ) /* (ring)->head */ +#define GET_RING_HEAD(ring) DRM_READ32( (volatile u32 *) (ring)->head ) +#define SET_RING_HEAD(ring,val) DRM_WRITE32( (volatile u32 *) (ring)->head , (val)) typedef struct drm_radeon_freelist { unsigned int age; @@ -53,7 +53,6 @@ typedef struct drm_radeon_ring_buffer { int space; int high_mark; - drm_local_map_t *ring_rptr; } drm_radeon_ring_buffer_t; typedef struct drm_radeon_depth_clear_t { @@ -127,13 +126,13 @@ typedef struct drm_radeon_private { drm_radeon_depth_clear_t depth_clear; - drm_local_map_t *sarea; - drm_local_map_t *fb; - drm_local_map_t *mmio; - drm_local_map_t *cp_ring; - drm_local_map_t *ring_rptr; - drm_local_map_t *buffers; - drm_local_map_t *agp_textures; + drm_map_t *sarea; + drm_map_t *fb; + drm_map_t *mmio; + drm_map_t *cp_ring; + drm_map_t *ring_rptr; + drm_map_t *buffers; + drm_map_t *agp_textures; struct mem_block *agp_heap; struct mem_block *fb_heap; @@ -194,7 +193,6 @@ extern int radeon_emit_and_wait_irq(drm_device_t *dev); extern int radeon_wait_irq(drm_device_t *dev, int swi_nr); extern int radeon_emit_irq(drm_device_t *dev); -extern void radeon_do_release(drm_device_t *dev); /* Flags for stats.boxes */ @@ -268,10 +266,8 @@ extern void radeon_do_release(drm_device_t *dev); #define RADEON_SCRATCH_UMSK 0x0770 #define RADEON_SCRATCH_ADDR 0x0774 -#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x)) - #define GET_SCRATCH( x ) (dev_priv->writeback_works \ - ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \ + ? DRM_READ32( &dev_priv->scratch[(x)] ) \ : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) ) @@ -690,10 +686,15 @@ extern void radeon_do_release(drm_device_t *dev); #define RADEON_RING_HIGH_MARK 128 -#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) -#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) -#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) -#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) + +#define RADEON_BASE(reg) ((unsigned long)(dev_priv->mmio->handle)) +#define RADEON_ADDR(reg) (RADEON_BASE( reg ) + reg) + +#define RADEON_READ(reg) DRM_READ32( (volatile u32 *) RADEON_ADDR(reg) ) +#define RADEON_WRITE(reg,val) DRM_WRITE32( (volatile u32 *) RADEON_ADDR(reg), (val) ) + +#define RADEON_READ8(reg) DRM_READ8( (volatile u8 *) RADEON_ADDR(reg) ) +#define RADEON_WRITE8(reg,val) DRM_WRITE8( (volatile u8 *) RADEON_ADDR(reg), (val) ) #define RADEON_WRITE_PLL( addr, val ) \ do { \ @@ -826,10 +827,43 @@ do { \ #define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring; -#define BEGIN_RING( n ) do { \ +#if defined(__alpha__) +# define RADEON_PAD_RING 16 /* pad ring requests to 16 lw boundaries */ +#else +# define RADEON_PAD_RING 0 +#endif + +#if RADEON_PAD_RING +# define radeon_pad_size(n) \ + (((RADEON_PAD_RING) - ((n) % (RADEON_PAD_RING))) % (RADEON_PAD_RING)) +# define radeon_pad_ring() do { \ + if (RADEON_VERBOSE) { \ + DRM_INFO("Padding ring from %d (%x) with %d words\n", \ + write, write, radeon_pad_size(write)); \ + } \ + switch (radeon_pad_size(write)) { \ + case 0: /* aligned */ \ + break; \ + case 1: /* 1 word */ \ + OUT_RING(CP_PACKET2()); \ + break; \ + default: /* >= 2 words */ \ + OUT_RING(CP_PACKET3(0x1000, radeon_pad_size(write) - 1));\ + write = (write + radeon_pad_size(write)) & mask; \ + write &= mask; \ + break; \ + } \ +} while(0) +#else +# define radeon_pad_size(n) 0 +# define radeon_pad_ring() +#endif + +#define BEGIN_RING( req_n ) do { \ + int n = req_n + radeon_pad_size(req_n); \ if ( RADEON_VERBOSE ) { \ - DRM_INFO( "BEGIN_RING( %d ) in %s\n", \ - n, __FUNCTION__ ); \ + DRM_INFO( "BEGIN_RING( %d (%d) ) in %s\n", \ + n, req_n, __FUNCTION__ ); \ } \ if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \ COMMIT_RING(); \ @@ -846,6 +880,7 @@ do { \ DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ write, dev_priv->ring.tail ); \ } \ + radeon_pad_ring(); \ if (((dev_priv->ring.tail + _nr) & mask) != write) { \ DRM_ERROR( \ "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ @@ -857,7 +892,7 @@ do { \ #define COMMIT_RING() do { \ /* Flush writes to ring */ \ - DRM_READMEMORYBARRIER(dev_priv->mmio); \ + DRM_READMEMORYBARRIER(); \ GET_RING_HEAD( &dev_priv->ring ); \ RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \ /* read from PCI bus to ensure correct posting */ \ diff --git a/shared-core/radeon_mem.c b/shared-core/radeon_mem.c index 3a2c8969..5c07c1af 100644 --- a/shared-core/radeon_mem.c +++ b/shared-core/radeon_mem.c @@ -118,7 +118,7 @@ static void free_block( struct mem_block *p ) p->size += q->size; p->next = q->next; p->next->prev = p; - DRM_FREE(q, sizeof(*q)); + DRM_FREE(q); } if (p->prev->pid == 0) { @@ -126,10 +126,20 @@ static void free_block( struct mem_block *p ) q->size += p->size; q->next = p->next; q->next->prev = q; - DRM_FREE(p, sizeof(*q)); + DRM_FREE(p); } } +static void print_heap( struct mem_block *heap ) +{ + struct mem_block *p; + + for (p = heap->next ; p != heap ; p = p->next) + DRM_DEBUG("0x%x..0x%x (0x%x) -- owner %d\n", + p->start, p->start + p->size, + p->size, p->pid); +} + /* Initialize. How to check for an uninitialized heap? */ static int init_heap(struct mem_block **heap, int start, int size) @@ -141,7 +151,7 @@ static int init_heap(struct mem_block **heap, int start, int size) *heap = DRM_MALLOC(sizeof(**heap)); if (!*heap) { - DRM_FREE( blocks, sizeof(*blocks) ); + DRM_FREE( blocks ); return -ENOMEM; } @@ -181,7 +191,7 @@ void radeon_mem_release( struct mem_block *heap ) p->size += q->size; p->next = q->next; p->next->prev = p; - DRM_FREE(q, sizeof(*q)); + DRM_FREE(q); } } } @@ -198,10 +208,10 @@ void radeon_mem_takedown( struct mem_block **heap ) for (p = (*heap)->next ; p != *heap ; ) { struct mem_block *q = p; p = p->next; - DRM_FREE(q, sizeof(*q)); + DRM_FREE(q); } - DRM_FREE( *heap, sizeof(**heap) ); + DRM_FREE( *heap ); *heap = 0; } |