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2011-05-08target-mips: Do not check CPU_INTERRUPT_TIMER.Richard Henderson1-4/+0
This bit is never set, therefore we should not read it either. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-04-20Remove unused function parameter from cpu_restore_stateStefan Weil1-2/+2
The previous patch removed the need for parameter puc. Is is now unused, so remove it. Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Weil <weil@mail.berlios.de>
2011-04-20Remove unused function parameters from gen_pc_load and rename the functionStefan Weil1-2/+1
Function gen_pc_load was introduced in commit d2856f1ad4c259e5766847c49acbb4e390731bd4. The only reason for parameter searched_pc was a debug statement in target-i386/translate.c. Parameter puc was needed by target-sparc until commit d7da2a10402f1644128b66414ca8f86bdea9ae7c. Remove searched_pc from the debug statement and remove both parameters from the parameter list of gen_pc_load. As the function name gen_pc_load was also misleading, it is now called restore_state_to_opc. This new name was suggested by Peter Maydell, thanks. v2: Remove last parameter, too, and rename the function. v3: Fix [] typo in target-arm/translate.c. Fix wrong SHA1 object name in commit message (copy+paste error). Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Weil <weil@mail.berlios.de>
2011-04-17target-mips: clear softfpu exception state for comparison instructionsAurelien Jarno1-16/+25
MIPS FPU instructions should start with a clean softfpu status. This is done for the most instructions, but not for comparison ones. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-17target-mips: fix c.ps.* instructionsAurelien Jarno1-4/+4
Contrary to cabs.ps.* instructions, c.ps.* should not compare the absolute value of the operand, but directly the operands. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-17target-mips: don't hardcode softfloat exception bitsAurelien Jarno1-15/+20
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-17target-mips: simplify FP comparisonsAurelien Jarno1-36/+36
As the softfloat comparison functions already test for NaN, there is no need to always call the float*_unordered*() functions. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-17softfloat: rename float*_eq() into float*_eq_quiet()Aurelien Jarno1-16/+16
float*_eq functions have a different semantics than other comparison functions. Fix that by first renaming float*_quiet() into float*_eq_quiet(). Note that it is purely mechanical, and the behaviour should be unchanged. That said it clearly highlight problems due to this different semantics, they are fixed later in this patch series. Cc: Alexander Graf <agraf@suse.de> Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-17target-mips: use new float*_unordered*() functionsAurelien Jarno1-98/+70
Use the new float*_unordered*() functions from softfloat instead of redefining a private version. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-10Fix conversions from pointer to tcg_target_longStefan Weil1-1/+1
tcg_gen_exit_tb takes a parameter of type tcg_target_long, so the type casts of pointer to long should be replaced by type casts of pointer to tcg_target_long (suggested by Blue Swirl). These changes are needed for build environments where sizeof(long) != sizeof(void *), especially for w64. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-03Fix trivial "endianness bugs"Stefan Weil1-1/+1
Replace endianess -> endianness. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-13inline cpu_halted into sole callerPaolo Bonzini1-11/+0
All implementations are now the same, and there is only one caller, so inline the function there. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-02-09[PATCH] [MIPS] Clear softfpu exception state for round, trunc, ceil and floorChris Dearman1-0/+16
MIPS FPU instructions should start with a clean softfpu status. This is done for the arithmetic operations and cvt instructions, but not for round, trunc, ceil and floor. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-24target-mips: fix save_cpu_state() callsAurelien Jarno1-6/+6
The rule is: - don't save PC if the exception is only triggered by softmmu. - save PC if the exception can be triggered by an helper. Fix a 64-bit kernel crash when loading modules. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-18mips: Break TBs after mfc0_countEdgar E. Iglesias1-2/+6
Break the TB after reading the count register. This makes it possible to take timer interrupts immediately after a read of a possibly expired timer. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-01-02softfloat: Rename float*_is_nan() functions to float*_is_quiet_nan()Peter Maydell1-4/+4
The softfloat functions float*_is_nan() were badly misnamed, because they return true only for quiet NaNs, not for all NaNs. Rename them to float*_is_quiet_nan() to more accurately reflect what they do. This change was produced by: perl -p -i -e 's/_is_nan/_is_quiet_nan/g' $(git grep -l is_nan) (with the results manually checked.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com> Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27target-mips: fix host CPU consumption when guest is idleAurelien Jarno2-3/+23
When the CPU is in wait state, do not wake-up if an interrupt can't be taken. This avoid host CPU running at 100% if a device (e.g. timer) has an interrupt line left enabled. Also factorize code to check if interrupts are enabled in cpu_mips_hw_interrupts_pending(). Based on a patch from Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2010-12-22target-mips: fix translation of MT instructionsNathan Froyd3-28/+16
The translation of dmt/emt/dvpe/evpe was doing the moral equivalent of: int x; ... /* no initialization of x */ x = f (x); which confused later bits of TCG rather badly, leading to crashes. Fix the helpers to only return results (those instructions have no inputs), and fix the translation code accordingly. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-10-30target-xxx: Use fprintf_function (format checking)Stefan Weil3-9/+8
fprintf_function uses format checking with GCC_FMT_ATTR. Format errors were fixed in * target-i386/helper.c * target-mips/translate.c * target-ppc/translate.c Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-10-13mips: avoid write only variablesBlue Swirl1-0/+29
Compiling with GCC 4.6.0 20100925 produced a lot of warnings like: /src/qemu/target-mips/translate.c: In function 'gen_ld': /src/qemu/target-mips/translate.c:1039:17: error: variable 'opn' set but not used [-Werror=unused-but-set-variable] Fix by adding a dummy cast so that the variable is not unused. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-09-18MIPS: fix yield handlingBlue Swirl1-1/+3
The parameter for yield should be handled as a signed integer for the comparisons to have any effect. This also avoids a gcc warning with -Wtype-limits. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-08-06mips: Add support for VInt and VEIC irq modesEdgar E. Iglesias2-0/+50
Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-07-31Correctly identify multiple cpus in SMP systemsHervé Poussineau2-4/+2
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-31Remove unused constantHervé Poussineau1-4/+0
Remove unused constant MIPS_FCR0 Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-25mips: more fixes to the MIPS interrupt glue logicAurelien Jarno4-15/+21
Commit 36388314febad3d7675ab919287f03733a560ff6 moved most of the interrupt logic to cpu-exec.c. Remove the remaining useless code and fix software interrupts. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: Edgar E. Iglesias <edgar@axis.com> Tested-by: Edgar E. Iglesias <edgar@axis.com>
2010-07-24mips: Correct MIPS interrupt glue logic for icountEdgar E. Iglesias2-14/+0
When hw interrupt pending bits in CP0_Cause are set, the CPU should see the hw interrupt line as active. The CPU may or may not take the interrupt based on internal state (global irq mask etc) but the glue logic shouldn't care. This fixes MIPS external hw interrupts in combination with -icount. Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-07-17target-mips: fix xtlb exception for loongsonAurelien Jarno1-2/+4
Loongson 2E and 2F use the same entry for xtlb and tlb exception, at offset 0x000. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-11target-mips: add loongson 2E & 2F integer instructionsAurelien Jarno1-0/+271
This patch adds support for loongson 2E & 2F instructions. They are the same instructions, but differ by the opcode encoding. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-03remove exec-all.h inclusion from cpu.hPaolo Bonzini1-1/+0
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-03move cpu_pc_from_tb to target-*/exec.hPaolo Bonzini2-7/+7
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-03remove unused stuff from */exec.hPaolo Bonzini2-9/+6
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-01target-mips: add Loongson support prefetchAurelien Jarno1-35/+43
Loongson CPU uses a load to zero register for prefetch. Emulate it as a NOP. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-01target-mips: split load and storeAurelien Jarno1-155/+183
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-30target-mips: fix DINSU instructionAurelien Jarno1-1/+1
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-29target-mips: enable movn/movz on loongson 2E & 2FAurelien Jarno1-1/+2
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-29MIPS: Initial support of fulong mini pc (CPU definition)Huacai Chen2-0/+39
Signed-off-by: Huacai Chen <zltjiangshi@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09target-mips: Fix compilationStefan Weil1-1/+1
TCGv t1 needs tcg_temp_free instead of tcg_temp_free_i32. Cc: Nathan Froyd <froydnj@codesourcery.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09target-mips: add microMIPS exception handler supportNathan Froyd2-6/+16
Unlike MIPS16, microMIPS lets you choose the ISA mode for your exception handlers. The ISA mode is selectable via a user-writable CP0.Config3 flag. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09target-mips: microMIPS ASE supportNathan Froyd4-5/+2531
Add instruction decoding for the microMIPS ASE. All we do is decode and then forward to the existing gen_* routines. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09target-mips: mips16 cleanupsNathan Froyd1-7/+17
Change code handling mips16-specific branches to use ISA-neutral special opcodes. Since there are several places where the delay slot requirements for microMIPS branches differ from mips16 branches, using opcodes is easier than checking hflags, then checking mips16 vs. microMIPS. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09target-mips: refactor c{, abs}.cond.fmt insnsNathan Froyd1-83/+81
Move all knowledge about coprocessor-checking and register numbering into the gen_cmp* helper functions. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09target-mips: move FP FMT comments closer to the definitionsAurelien Jarno1-14/+14
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09target-mips: define constants for magic numbersNathan Froyd1-142/+295
Add FMT_* constants for the floating-point format field in opcodes and tweak a few places to use them. Add enums for various invocations of FOP and tweak gen_farith and its lone caller accordingly. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-08target-mips: break out [ls][wd]c1 and rdhwr insn generationNathan Froyd1-47/+59
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Acked-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-05target-mips: Remove duplicate CPU log.Richard Henderson1-6/+0
Logging for -d cpu is done in generic code. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-09target-mips: Fix format specifiers for fpu_fprintfStefan Weil1-14/+20
In the previous patch which introduced fprintf_function to allow parameter checking by gcc some compiler warnings remained unfixed. These warnings are fixed here. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08target-mips: Fix one more format specifier for cpu_fprintfStefan Weil1-1/+3
env->bcond must be printed using TARGET_FMT_ld. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08remove TARGET_* defines from translate-all.cPaolo Bonzini1-0/+2
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-17Large page TLB flushPaul Brook1-3/+4
QEMU uses a fixed page size for the CPU TLB. If the guest uses large pages then we effectively split these into multiple smaller pages, and populate the corresponding TLB entries on demand. When the guest invalidates the TLB by virtual address we must invalidate all entries covered by the large page. However the address used to invalidate the entry may not be present in the QEMU TLB, so we do not know which regions to clear. Implementing a full vaiable size TLB is hard and slow, so just keep a simple address/mask pair to record which addresses may have been mapped by large pages. If the guest invalidates this region then flush the whole TLB. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-13target-mips: update address space definitionsAurelien Jarno1-4/+4
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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