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path: root/target-i386/translate.c
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2008-10-04Fix crc32w decoding, fix a constant width in blendvpd.balrog1-4/+3
2008-10-04x86 "popcnt" affects flags.balrog1-0/+2
2008-10-04Implement SSE4.1, SSE4.2 (x86).balrog1-31/+300
2008-10-01x86 pextrw destination operand can be r64.balrog1-1/+2
2008-09-25SYSENTER/SYSEXIT IA-32e implementation (Alexander Graf).balrog1-3/+5
2008-09-25Implement x86 SSSE3 instructions.balrog1-2/+107
2008-07-18Small cleanup of gen_intermediate_code(_internal), by Laurent Desnogues.ths1-8/+7
2008-07-07fix cvtsq2s[sd] (Juergen Lock)bellard1-2/+6
2008-07-05Re-add static qualifier. Fix annother occurance of "const static".pbrook1-1/+1
2008-06-30Fix rdtsc instruction counting.pbrook1-0/+6
2008-06-29Add instruction counter.pbrook1-4/+61
2008-06-18HLT, MWAIT and MONITOR insn fixes (initial patch by Alexander Graf)bellard1-4/+6
2008-06-06undocumented 0x82 opcode is invalid in 64 bit codebellard1-1/+3
2008-06-04fixed exceptions for cpuid and invlpgbellard1-0/+6
2008-06-04reworked SVM interrupt handling logic - fixed vmrun EIP saved value - reworke...bellard1-4/+5
2008-06-0432 bit SVM fixes - INVLPG and INVLPGA updatesbellard1-4/+8
2008-05-28SVM reworkbellard1-137/+101
2008-05-25fixed x86_64 regressionbellard1-4/+4
2008-05-25transformed TN into temporaries - add local temporaries usage when needed - o...bellard1-215/+253
2008-05-24Fix ARM conditional branch bug.pbrook1-28/+25
2008-05-22use debug_insn_start to have nicer debug tracesbellard1-5/+2
2008-05-22proper helper definition registering (all targets must do that)bellard1-0/+5
2008-05-22optimization of shifts by a constantbellard1-4/+68
2008-05-22lahf/sahf cpuid testbellard1-2/+4
2008-05-22cmpxchg8b fix - added cmpxchg16bbellard1-5/+20
2008-05-22cmpxchg 64 bit fixbellard1-4/+10
2008-05-21converted conditional jumps, SET and CMOVx to TCGbellard1-392/+421
2008-05-21converted env access to TCGbellard1-32/+32
2008-05-21convert eflags manipulation insns to TCGbellard1-13/+29
2008-05-21convert remaining segment handling to TCGbellard1-9/+36
2008-05-21converted LSL/LAR/VERW/VERR to TCG - force 16 bit memory access for LSL/LARbellard1-17/+23
2008-05-21suppressed no longer used opsbellard1-6/+0
2008-05-21converted INTO/CMPXCHG8B to TCGbellard1-2/+2
2008-05-21converted BCD ops to TCGbellard1-6/+6
2008-05-21converted MUL/IMUL to TCGbellard1-11/+129
2008-05-18converted string OPs and LOOP insns to TCGbellard1-192/+147
2008-05-18fixed INC/DEC condition codesbellard1-1/+1
2008-05-17converted sign extension ops to TCGbellard1-15/+31
2008-05-17MONITOR insn address generation fix - converted XLAT to TCGbellard1-16/+20
2008-05-17BSR/BSF TCG conversionbellard1-27/+21
2008-05-17converted bit test operations to TCGbellard1-55/+53
2008-05-17converted adc, sbb, cmpxchg to TCGbellard1-172/+151
2008-05-17converted condition code supprot to TCG - converted shift ops to TCGbellard1-640/+597
2008-05-15converted more helpers to TCG - fixed some SVM issuesbellard1-147/+153
2008-05-12compilation fixbellard1-1/+3
2008-05-12converted more helpers to TCGbellard1-58/+62
2008-05-12FPU fixesbellard1-11/+11
2008-05-12converted x87 FPU ops to TCGbellard1-142/+228
2008-05-12converted SSE/MMX ops to TCGbellard1-121/+200
2008-05-12use TCG for MMX/SSE memory accessesbellard1-52/+58
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