summaryrefslogtreecommitdiff
path: root/target-arm
AgeCommit message (Expand)AuthorFilesLines
2016-07-04target-arm/arm-semi.c: Fix SYS_HEAPINFO for 64-bit guestsPeter Maydell1-21/+26
2016-06-29Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell1-2/+0
2016-06-29target-*: Don't redefine cpu_exec()Peter Crosthwaite1-2/+0
2016-06-24softfloat: Implement run-time-configurable meaning of signaling NaN bitAleksandar Markovic2-27/+27
2016-06-20exec: [tcg] Track which vCPU is performing translation and executionLluís Vilanova1-0/+1
2016-06-17target-arm/monitor.c: Advertise emulated GICv3 in capabilitiesPeter Maydell1-2/+1
2016-06-17target-arm/machine.c: Allow user to request GICv3 emulationPeter Maydell1-2/+1
2016-06-17target-arm: Add mp-affinity property for ARM CPU classPavel Fedin1-0/+1
2016-06-17target-arm: Provide hook to tell GICv3 about changes of security statePeter Maydell5-0/+57
2016-06-17target-arm: Define new arm_is_el3_or_mon() functionPeter Maydell1-2/+11
2016-06-16os-posix: include sys/mman.hPaolo Bonzini3-3/+0
2016-06-14target-arm: Don't permit ARMv8-only Neon insns on ARMv7Peter Maydell1-0/+28
2016-06-14target-arm: Fix reset and migration of TTBCR(S)Peter Maydell1-1/+4
2016-06-14hw/arm/virt: Add PMU node for virt machineShannon Zhao3-0/+54
2016-06-14target-arm: kvm64: set guest PMUv3 feature bit if supportedShannon Zhao2-0/+7
2016-06-07virtio: move bi-endian target support to a single locationGreg Kurz1-2/+0
2016-06-06target-arm: Fix TTBR selecting logic on AArch32 Stage 2 translationSergey Sorokin1-16/+22
2016-06-06target-arm: Don't try to set ESR IL bit in arm_cpu_do_interrupt_aarch64()Peter Maydell1-3/+0
2016-06-06target-arm: Set IL bit in syndromes for insn abort, watchpoint, swstepPeter Maydell1-3/+3
2016-06-06target-arm: A64: Create Instruction Syndromes for Data AbortsEdgar E. Iglesias5-30/+180
2016-06-06target-arm: Add the HSTR_EL2 registerAlistair Francis2-0/+8
2016-05-19cpu: move exec-all.h inclusion out of cpu.hPaolo Bonzini10-2/+9
2016-05-19hw: explicitly include qemu/log.hPaolo Bonzini3-0/+3
2016-05-19arm: move arm_log_exception into .c filePaolo Bonzini2-15/+15
2016-05-19qemu-common: push cpu.h inclusion out of qemu-common.hPaolo Bonzini6-2/+7
2016-05-19hw: move CPU state serialization to migration/cpu.hPaolo Bonzini1-0/+1
2016-05-19target-arm: make cpu-qom.h not target specificPaolo Bonzini2-178/+179
2016-05-19cpu: make cpu-qom.h only include-able from cpu.hPaolo Bonzini1-1/+0
2016-05-12tcg: Allow goto_tb to any target PC in user modeSergey Fedorov2-6/+14
2016-05-12tcg: Clean up direct block chaining safety checksSergey Fedorov1-1/+2
2016-05-12tb: consistently use uint32_t for tb->flagsEmilio G. Cota1-1/+1
2016-05-12target-arm: Avoid unnecessary TLB flush on TCR_EL2, TCR_EL3 writesPeter Maydell1-4/+8
2016-05-12ARM: Factor out ARM on/off PSCI control functionsJean-Christophe DUBOIS4-63/+307
2016-05-12target-arm/translate-a64.c: Unify some of the ldst_reg decodingEdgar E. Iglesias1-18/+23
2016-05-12target-arm/translate-a64.c: Use extract32 in disas_ldst_reg_imm9Edgar E. Iglesias1-2/+2
2016-05-12target-arm: Split data abort syndrome generatorPeter Maydell2-5/+25
2016-05-12target-arm: Fix descriptor address masking in ARM address translationSergey Sorokin1-18/+11
2016-05-12target-arm: Stage 2 permission fault was fixed in AArch32 stateSergey Sorokin1-1/+3
2016-04-04target-arm: Make the 64-bit version of VTCR do the migrationPeter Maydell1-1/+5
2016-04-04target-arm: Remove incorrect ALIAS tags from ESR_EL2 and ESR_EL3Peter Maydell1-2/+0
2016-04-04target-arm: Correctly reset SCTLR_EL3 for 64-bit CPUsPeter Maydell1-10/+13
2016-03-30arm: implement query-gic-capabilitiesPeter Xu1-1/+57
2016-03-30arm: enhance kvm_arm_create_scratch_host_vcpuPeter Xu2-3/+18
2016-03-30arm: qmp: add query-gic-capabilities interfacePeter Xu2-1/+29
2016-03-22target-arm: dfilter support for in_asmAlex Bennée2-2/+4
2016-03-22util: move declarations out of qemu-common.hVeronia Bahaa1-0/+1
2016-03-22include/qemu/osdep.h: Don't include qapi/error.hMarkus Armbruster2-0/+2
2016-03-16target-arm: Fix translation level on early translation faultsSergey Sorokin1-10/+12
2016-03-16target-arm: Implement MRS (banked) and MSR (banked) instructionsPeter Maydell3-3/+366
2016-03-04target-arm: Only trap SRS from S-EL1 if specified mode is MONRalf-Philipp Weinmann1-1/+2
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-02 08:45:58 +0000