diff options
| author | Miodrag Dinic <miodrag.dinic@imgtec.com> | 2017-06-15 16:20:33 +0200 |
|---|---|---|
| committer | Yongbok Kim <yongbok.kim@imgtec.com> | 2017-07-11 15:06:34 +0100 |
| commit | cab4888136a92250fdd401402622824994f7ce0b (patch) | |
| tree | 6441f5e3fdf4526da86578445560850868af535d /target | |
| parent | b5ed2e11ef39a308dcbef46f66774557b4a41fce (diff) | |
target/mips: fix msa copy_[s|u]_df rd = 0 corner case
This patch fixes the msa copy_[s|u]_df instruction emulation when
the destination register rd is zero. Without this patch the zero
register would get clobbered, which should never happen because it
is supposed to be hardwired to 0.
Fix this corner case by explicitly checking rd = 0 and effectively
making these instructions emulation no-op in that case.
Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/mips/translate.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index 559f8fed89..befb87f814 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -18712,10 +18712,14 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df, #endif switch (MASK_MSA_ELM(ctx->opcode)) { case OPC_COPY_S_df: - gen_helper_msa_copy_s_df(cpu_env, tdf, twd, tws, tn); + if (likely(wd != 0)) { + gen_helper_msa_copy_s_df(cpu_env, tdf, twd, tws, tn); + } break; case OPC_COPY_U_df: - gen_helper_msa_copy_u_df(cpu_env, tdf, twd, tws, tn); + if (likely(wd != 0)) { + gen_helper_msa_copy_u_df(cpu_env, tdf, twd, tws, tn); + } break; case OPC_INSERT_df: gen_helper_msa_insert_df(cpu_env, tdf, twd, tws, tn); |