diff options
| author | Nathan Froyd <froydnj@codesourcery.com> | 2009-06-04 13:46:41 -0700 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2009-07-12 23:36:21 +0200 |
| commit | 33890b3e0deb8891d5b1241671eb3979f8896bf3 (patch) | |
| tree | 1b3d467066ab7e5aa2db1ef31a956f269a8d1d75 /target-ppc | |
| parent | f55e9d9a40acd3b0e364844017fa14f3aab76645 (diff) | |
target-ppc: fix evmergelo and evmergelohi
For 32-bit PPC targets, we translated:
evmergelo rX, rX, rY
as:
rX-lo = rY-lo
rX-hi = rX-lo
which is wrong, because we should be transferring rX-lo first. This
problem is fixed by swapping the order in which we write the parts of
rX.
Similarly, we translated:
evmergelohi rX, rX, rY
as:
rX-lo = rY-hi
rX-hi = rX-lo
In this case, we can't swap the assignment statements, because that
would just cause problems for:
evmergelohi rX, rY, rX
Instead, we detect the first case and save rX-lo in a temporary
variable:
tmp = rX-lo
rX-lo = rY-hi
rX-hi = tmp
These problems don't occur on PPC64 targets because we don't split the
SPE registers into hi/lo parts for such targets.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/translate.c | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index a14d197e41..b278638557 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -6908,8 +6908,8 @@ static always_inline void gen_evmergelo (DisasContext *ctx) tcg_temp_free(t0); tcg_temp_free(t1); #else - tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); #endif } static always_inline void gen_evmergehilo (DisasContext *ctx) @@ -6946,8 +6946,16 @@ static always_inline void gen_evmergelohi (DisasContext *ctx) tcg_temp_free(t0); tcg_temp_free(t1); #else - tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); - tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); + if (rD(ctx->opcode) == rA(ctx->opcode)) { + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); + tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp); + tcg_temp_free_i32(tmp); + } else { + tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); + tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); + } #endif } static always_inline void gen_evsplati (DisasContext *ctx) |