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authorPeter Maydell <peter.maydell@linaro.org>2017-09-07 13:34:32 +0100
committerPeter Maydell <peter.maydell@linaro.org>2017-09-07 13:34:32 +0100
commite6533b57d7d17a365bfc5e517bd096b7d405b5b5 (patch)
treefb8baed53b7d0599b16a5d741e7a1058571a9891 /include
parent8ee5f9b3ecc94e3eb7a8235f4b2c3ec9024807f6 (diff)
parent4609190b5f7f68a5e2a8738029594f45a062d4c9 (diff)
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20170906' into staging
Queued tcg patches # gpg: Signature made Wed 06 Sep 2017 15:27:16 BST # gpg: using RSA key 0xAD1270CC4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" # Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B * remotes/rth/tags/pull-tcg-20170906: tcg/s390: Use slbgr for setcond le and leu tcg/s390: Use load-on-condition-2 facility tcg/s390: Use distinct-operands facility tcg/s390: Merge ori+xori facilities check to tcg_target_op_def tcg/s390: Merge add2i facilities check to tcg_target_op_def tcg/s390: Merge muli facilities check to tcg_target_op_def tcg/s390: Merge cmpi facilities check to tcg_target_op_def tcg/s390: Fully convert tcg_target_op_def disas/i386: Add disassembly of rorx disas/i386: Add disassembly of vex.0f38.f5 disas/i386: Fix disassembly of two-byte vex prefixes tcg: Implement implicit ordering semantics tcg: Add tcg target default memory ordering tcg: Remove support for ia64 as host Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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