diff options
| author | Keith Whitwell <keith@tungstengraphics.com> | 2007-03-13 16:48:44 +0000 |
|---|---|---|
| committer | Keith Whitwell <keith@tungstengraphics.com> | 2007-03-13 16:48:44 +0000 |
| commit | 402ff99f15bd36e8454a1e3eea9d0085fe3154af (patch) | |
| tree | 24d21dec3be28b576e5cee39f84dc93a593d1e16 | |
| parent | c11f0148aca6bb8c03b8715c58eb2d4d2da8cc6c (diff) | |
Major state rework to match i965 driver. Builds.
44 files changed, 1449 insertions, 5391 deletions
diff --git a/src/mesa/drivers/dri/i915tex/Makefile b/src/mesa/drivers/dri/i915tex/Makefile index 89fd30de82..c8fee7dfb5 100644 --- a/src/mesa/drivers/dri/i915tex/Makefile +++ b/src/mesa/drivers/dri/i915tex/Makefile @@ -8,28 +8,22 @@ MINIGLX_SOURCES = server/intel_dri.c DRIVER_SOURCES = \ i915_context.c \ - i915_fp.c \ - i915_fp_debug.c \ - i915_fp_emit.c \ - i915_fp_state.c \ - i915_fp_translate.c \ - i915_metaops.c \ + i915_fpc.c \ + i915_fpc_debug.c \ + i915_fpc_emit.c \ + i915_fpc_translate.c \ i915_program.c \ i915_state.c \ + i915_state_fp.c \ + i915_state_fp_inputs.c \ + i915_state_fallback.c \ + i915_state_invarient.c \ i915_state_immediate.c \ - i915_state_indirect.c \ + i915_state_map.c \ i915_state_misc.c \ - i915_tex.c \ + i915_state_sampler.c \ i915_tex_layout.c \ - i915_tex_state.c \ i915_vtbl.c \ - i830_context.c \ - i830_metaops.c \ - i830_state.c \ - i830_texblend.c \ - i830_tex.c \ - i830_texstate.c \ - i830_vtbl.c \ intel_render.c \ intel_idx_render.c \ intel_regions.c \ @@ -43,6 +37,7 @@ DRIVER_SOURCES = \ intel_tex_validate.c \ intel_tex_format.c \ intel_tex.c \ + intel_metaops.c \ intel_pixel.c \ intel_pixel_copy.c \ intel_pixel_read.c \ @@ -55,6 +50,7 @@ DRIVER_SOURCES = \ intel_screen.c \ intel_span.c \ intel_state.c \ + intel_state_callbacks.c \ intel_tris.c \ intel_fbo.c \ intel_depthstencil.c \ diff --git a/src/mesa/drivers/dri/i915tex/i830_metaops.c b/src/mesa/drivers/dri/i915tex/i830_metaops.c deleted file mode 100644 index f76646d89d..0000000000 --- a/src/mesa/drivers/dri/i915tex/i830_metaops.c +++ /dev/null @@ -1,457 +0,0 @@ -/************************************************************************** - * - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - **************************************************************************/ - -#include "glheader.h" -#include "enums.h" -#include "mtypes.h" -#include "macros.h" -#include "utils.h" - -#include "intel_screen.h" -#include "intel_batchbuffer.h" -#include "intel_ioctl.h" -#include "intel_regions.h" - -#include "i830_context.h" -#include "i830_reg.h" - -/* A large amount of state doesn't need to be uploaded. - */ -#define ACTIVE (I830_UPLOAD_INVARIENT | \ - I830_UPLOAD_CTX | \ - I830_UPLOAD_BUFFERS | \ - I830_UPLOAD_STIPPLE | \ - I830_UPLOAD_TEXBLEND(0) | \ - I830_UPLOAD_TEX(0)) - - -#define SET_STATE( i830, STATE ) \ -do { \ - i830->current->emitted &= ~ACTIVE; \ - i830->current = &i830->STATE; \ - i830->current->emitted &= ~ACTIVE; \ -} while (0) - - -static void -set_no_stencil_write(struct intel_context *intel) -{ - struct i830_context *i830 = i830_context(&intel->ctx); - - /* ctx->Driver.Enable( ctx, GL_STENCIL_TEST, GL_FALSE ) - */ - i830->meta.Ctx[I830_CTXREG_ENABLES_1] &= ~ENABLE_STENCIL_TEST; - i830->meta.Ctx[I830_CTXREG_ENABLES_2] &= ~ENABLE_STENCIL_WRITE; - i830->meta.Ctx[I830_CTXREG_ENABLES_1] |= DISABLE_STENCIL_TEST; - i830->meta.Ctx[I830_CTXREG_ENABLES_2] |= DISABLE_STENCIL_WRITE; - - i830->meta.emitted &= ~I830_UPLOAD_CTX; -} - -static void -set_no_depth_write(struct intel_context *intel) -{ - struct i830_context *i830 = i830_context(&intel->ctx); - - /* ctx->Driver.Enable( ctx, GL_DEPTH_TEST, GL_FALSE ) - */ - i830->meta.Ctx[I830_CTXREG_ENABLES_1] &= ~ENABLE_DIS_DEPTH_TEST_MASK; - i830->meta.Ctx[I830_CTXREG_ENABLES_2] &= ~ENABLE_DIS_DEPTH_WRITE_MASK; - i830->meta.Ctx[I830_CTXREG_ENABLES_1] |= DISABLE_DEPTH_TEST; - i830->meta.Ctx[I830_CTXREG_ENABLES_2] |= DISABLE_DEPTH_WRITE; - - i830->meta.emitted &= ~I830_UPLOAD_CTX; -} - -/* Set depth unit to replace. - */ -static void -set_depth_replace(struct intel_context *intel) -{ - struct i830_context *i830 = i830_context(&intel->ctx); - - /* ctx->Driver.Enable( ctx, GL_DEPTH_TEST, GL_FALSE ) - * ctx->Driver.DepthMask( ctx, GL_TRUE ) - */ - i830->meta.Ctx[I830_CTXREG_ENABLES_1] &= ~ENABLE_DIS_DEPTH_TEST_MASK; - i830->meta.Ctx[I830_CTXREG_ENABLES_2] &= ~ENABLE_DIS_DEPTH_WRITE_MASK; - i830->meta.Ctx[I830_CTXREG_ENABLES_1] |= ENABLE_DEPTH_TEST; - i830->meta.Ctx[I830_CTXREG_ENABLES_2] |= ENABLE_DEPTH_WRITE; - - /* ctx->Driver.DepthFunc( ctx, GL_ALWAYS ) - */ - i830->meta.Ctx[I830_CTXREG_STATE3] &= ~DEPTH_TEST_FUNC_MASK; - i830->meta.Ctx[I830_CTXREG_STATE3] |= (ENABLE_DEPTH_TEST_FUNC | - DEPTH_TEST_FUNC - (COMPAREFUNC_ALWAYS)); - - i830->meta.emitted &= ~I830_UPLOAD_CTX; -} - - -/* Set stencil unit to replace always with the reference value. - */ -static void -set_stencil_replace(struct intel_context *intel, - GLuint s_mask, GLuint s_clear) -{ - struct i830_context *i830 = i830_context(&intel->ctx); - - /* ctx->Driver.Enable( ctx, GL_STENCIL_TEST, GL_TRUE ) - */ - i830->meta.Ctx[I830_CTXREG_ENABLES_1] |= ENABLE_STENCIL_TEST; - i830->meta.Ctx[I830_CTXREG_ENABLES_2] |= ENABLE_STENCIL_WRITE; - - /* ctx->Driver.StencilMask( ctx, s_mask ) - */ - i830->meta.Ctx[I830_CTXREG_STATE4] &= ~MODE4_ENABLE_STENCIL_WRITE_MASK; - i830->meta.Ctx[I830_CTXREG_STATE4] |= (ENABLE_STENCIL_WRITE_MASK | - STENCIL_WRITE_MASK((s_mask & - 0xff))); - - /* ctx->Driver.StencilOp( ctx, GL_REPLACE, GL_REPLACE, GL_REPLACE ) - */ - i830->meta.Ctx[I830_CTXREG_STENCILTST] &= ~(STENCIL_OPS_MASK); - i830->meta.Ctx[I830_CTXREG_STENCILTST] |= - (ENABLE_STENCIL_PARMS | - STENCIL_FAIL_OP(STENCILOP_REPLACE) | - STENCIL_PASS_DEPTH_FAIL_OP(STENCILOP_REPLACE) | - STENCIL_PASS_DEPTH_PASS_OP(STENCILOP_REPLACE)); - - /* ctx->Driver.StencilFunc( ctx, GL_ALWAYS, s_clear, ~0 ) - */ - i830->meta.Ctx[I830_CTXREG_STATE4] &= ~MODE4_ENABLE_STENCIL_TEST_MASK; - i830->meta.Ctx[I830_CTXREG_STATE4] |= (ENABLE_STENCIL_TEST_MASK | - STENCIL_TEST_MASK(0xff)); - - i830->meta.Ctx[I830_CTXREG_STENCILTST] &= ~(STENCIL_REF_VALUE_MASK | - ENABLE_STENCIL_TEST_FUNC_MASK); - i830->meta.Ctx[I830_CTXREG_STENCILTST] |= - (ENABLE_STENCIL_REF_VALUE | - ENABLE_STENCIL_TEST_FUNC | - STENCIL_REF_VALUE((s_clear & 0xff)) | - STENCIL_TEST_FUNC(COMPAREFUNC_ALWAYS)); - - - - i830->meta.emitted &= ~I830_UPLOAD_CTX; -} - - -static void -set_color_mask(struct intel_context *intel, GLboolean state) -{ - struct i830_context *i830 = i830_context(&intel->ctx); - - const GLuint mask = ((1 << WRITEMASK_RED_SHIFT) | - (1 << WRITEMASK_GREEN_SHIFT) | - (1 << WRITEMASK_BLUE_SHIFT) | - (1 << WRITEMASK_ALPHA_SHIFT)); - - i830->meta.Ctx[I830_CTXREG_ENABLES_2] &= ~mask; - - if (state) { - i830->meta.Ctx[I830_CTXREG_ENABLES_2] |= - (i830->state.Ctx[I830_CTXREG_ENABLES_2] & mask); - } - - i830->meta.emitted &= ~I830_UPLOAD_CTX; -} - -/* Installs a one-stage passthrough texture blend pipeline. Is there - * more that can be done to turn off texturing? - */ -static void -set_no_texture(struct intel_context *intel) -{ - struct i830_context *i830 = i830_context(&intel->ctx); - static const struct gl_tex_env_combine_state comb = { - GL_NONE, GL_NONE, - {GL_TEXTURE, 0, 0,}, {GL_TEXTURE, 0, 0,}, - {GL_SRC_COLOR, 0, 0}, {GL_SRC_ALPHA, 0, 0}, - 0, 0, 0, 0 - }; - - i830->meta.TexBlendWordsUsed[0] = - i830SetTexEnvCombine(i830, &comb, 0, TEXBLENDARG_TEXEL0, - i830->meta.TexBlend[0], NULL); - - i830->meta.TexBlend[0][0] |= TEXOP_LAST_STAGE; - i830->meta.emitted &= ~I830_UPLOAD_TEXBLEND(0); -} - -/* Set up a single element blend stage for 'replace' texturing with no - * funny ops. - */ -static void -set_texture_blend_replace(struct intel_context *intel) -{ - struct i830_context *i830 = i830_context(&intel->ctx); - static const struct gl_tex_env_combine_state comb = { - GL_REPLACE, GL_REPLACE, - {GL_TEXTURE, GL_TEXTURE, GL_TEXTURE,}, {GL_TEXTURE, GL_TEXTURE, - GL_TEXTURE,}, - {GL_SRC_COLOR, GL_SRC_COLOR, GL_SRC_COLOR}, {GL_SRC_ALPHA, GL_SRC_ALPHA, - GL_SRC_ALPHA}, - 0, 0, 1, 1 - }; - - i830->meta.TexBlendWordsUsed[0] = - i830SetTexEnvCombine(i830, &comb, 0, TEXBLENDARG_TEXEL0, - i830->meta.TexBlend[0], NULL); - - i830->meta.TexBlend[0][0] |= TEXOP_LAST_STAGE; - i830->meta.emitted &= ~I830_UPLOAD_TEXBLEND(0); - -/* fprintf(stderr, "%s: TexBlendWordsUsed[0]: %d\n", */ -/* __FUNCTION__, i830->meta.TexBlendWordsUsed[0]); */ -} - - - -/* Set up an arbitary piece of memory as a rectangular texture - * (including the front or back buffer). - */ -static GLboolean -set_tex_rect_source(struct intel_context *intel, - struct _DriBufferObject *buffer, - GLuint offset, - GLuint pitch, GLuint height, GLenum format, GLenum type) -{ - struct i830_context *i830 = i830_context(&intel->ctx); - GLuint *setup = i830->meta.Tex[0]; - GLint numLevels = 1; - GLuint textureFormat; - GLuint cpp; - - /* A full implementation of this would do the upload through - * glTexImage2d, and get all the conversion operations at that - * point. We are restricted, but still at least have access to the - * fragment program swizzle. - */ - switch (format) { - case GL_BGRA: - switch (type) { - case GL_UNSIGNED_INT_8_8_8_8_REV: - case GL_UNSIGNED_BYTE: - textureFormat = (MAPSURF_32BIT | MT_32BIT_ARGB8888); - cpp = 4; - break; - default: - return GL_FALSE; - } - break; - case GL_RGBA: - switch (type) { - case GL_UNSIGNED_INT_8_8_8_8_REV: - case GL_UNSIGNED_BYTE: - textureFormat = (MAPSURF_32BIT | MT_32BIT_ABGR8888); - cpp = 4; - break; - default: - return GL_FALSE; - } - break; - case GL_BGR: - switch (type) { - case GL_UNSIGNED_SHORT_5_6_5_REV: - textureFormat = (MAPSURF_16BIT | MT_16BIT_RGB565); - cpp = 2; - break; - default: - return GL_FALSE; - } - break; - case GL_RGB: - switch (type) { - case GL_UNSIGNED_SHORT_5_6_5: - textureFormat = (MAPSURF_16BIT | MT_16BIT_RGB565); - cpp = 2; - break; - default: - return GL_FALSE; - } - break; - - default: - return GL_FALSE; - } - - i830->meta.tex_buffer[0] = buffer; - i830->meta.tex_offset[0] = offset; - - setup[I830_TEXREG_TM0LI] = (_3DSTATE_LOAD_STATE_IMMEDIATE_2 | - (LOAD_TEXTURE_MAP0 << 0) | 4); - setup[I830_TEXREG_TM0S1] = (((height - 1) << TM0S1_HEIGHT_SHIFT) | - ((pitch - 1) << TM0S1_WIDTH_SHIFT) | - textureFormat); - setup[I830_TEXREG_TM0S2] = - (((((pitch * cpp) / 4) - - 1) << TM0S2_PITCH_SHIFT) | TM0S2_CUBE_FACE_ENA_MASK); - - setup[I830_TEXREG_TM0S3] = - ((((numLevels - - 1) * - 4) << TM0S3_MIN_MIP_SHIFT) | (FILTER_NEAREST << - TM0S3_MIN_FILTER_SHIFT) | - (MIPFILTER_NONE << TM0S3_MIP_FILTER_SHIFT) | (FILTER_NEAREST << - TM0S3_MAG_FILTER_SHIFT)); - - setup[I830_TEXREG_CUBE] = (_3DSTATE_MAP_CUBE | MAP_UNIT(0)); - - setup[I830_TEXREG_MCS] = (_3DSTATE_MAP_COORD_SET_CMD | - MAP_UNIT(0) | - ENABLE_TEXCOORD_PARAMS | - TEXCOORDS_ARE_IN_TEXELUNITS | - TEXCOORDTYPE_CARTESIAN | - ENABLE_ADDR_V_CNTL | - TEXCOORD_ADDR_V_MODE(TEXCOORDMODE_WRAP) | - ENABLE_ADDR_U_CNTL | - TEXCOORD_ADDR_U_MODE(TEXCOORDMODE_WRAP)); - - i830->meta.emitted &= ~I830_UPLOAD_TEX(0); - return GL_TRUE; -} - - -static void -set_vertex_format(struct intel_context *intel) -{ - struct i830_context *i830 = i830_context(&intel->ctx); - i830->meta.Ctx[I830_CTXREG_VF] = (_3DSTATE_VFT0_CMD | - VFT0_TEX_COUNT(1) | - VFT0_DIFFUSE | VFT0_XYZ); - i830->meta.Ctx[I830_CTXREG_VF2] = (_3DSTATE_VFT1_CMD | - VFT1_TEX0_FMT(TEXCOORDFMT_2D) | - VFT1_TEX1_FMT(TEXCOORDFMT_2D) | - VFT1_TEX2_FMT(TEXCOORDFMT_2D) | - VFT1_TEX3_FMT(TEXCOORDFMT_2D)); - i830->meta.emitted &= ~I830_UPLOAD_CTX; -} - - -static void -meta_import_pixel_state(struct intel_context *intel) -{ - struct i830_context *i830 = i830_context(&intel->ctx); - - i830->meta.Ctx[I830_CTXREG_STATE1] = i830->state.Ctx[I830_CTXREG_STATE1]; - i830->meta.Ctx[I830_CTXREG_STATE2] = i830->state.Ctx[I830_CTXREG_STATE2]; - i830->meta.Ctx[I830_CTXREG_STATE3] = i830->state.Ctx[I830_CTXREG_STATE3]; - i830->meta.Ctx[I830_CTXREG_STATE4] = i830->state.Ctx[I830_CTXREG_STATE4]; - i830->meta.Ctx[I830_CTXREG_STATE5] = i830->state.Ctx[I830_CTXREG_STATE5]; - i830->meta.Ctx[I830_CTXREG_IALPHAB] = i830->state.Ctx[I830_CTXREG_IALPHAB]; - i830->meta.Ctx[I830_CTXREG_STENCILTST] = - i830->state.Ctx[I830_CTXREG_STENCILTST]; - i830->meta.Ctx[I830_CTXREG_ENABLES_1] = - i830->state.Ctx[I830_CTXREG_ENABLES_1]; - i830->meta.Ctx[I830_CTXREG_ENABLES_2] = - i830->state.Ctx[I830_CTXREG_ENABLES_2]; - i830->meta.Ctx[I830_CTXREG_AA] = i830->state.Ctx[I830_CTXREG_AA]; - i830->meta.Ctx[I830_CTXREG_FOGCOLOR] = - i830->state.Ctx[I830_CTXREG_FOGCOLOR]; - i830->meta.Ctx[I830_CTXREG_BLENDCOLOR0] = - i830->state.Ctx[I830_CTXREG_BLENDCOLOR0]; - i830->meta.Ctx[I830_CTXREG_BLENDCOLOR1] = - i830->state.Ctx[I830_CTXREG_BLENDCOLOR1]; - i830->meta.Ctx[I830_CTXREG_MCSB0] = i830->state.Ctx[I830_CTXREG_MCSB0]; - i830->meta.Ctx[I830_CTXREG_MCSB1] = i830->state.Ctx[I830_CTXREG_MCSB1]; - - - i830->meta.Ctx[I830_CTXREG_STATE3] &= ~CULLMODE_MASK; - i830->meta.Stipple[I830_STPREG_ST1] &= ~ST1_ENABLE; - i830->meta.emitted &= ~I830_UPLOAD_CTX; - - - i830->meta.Buffer[I830_DESTREG_SENABLE] = - i830->state.Buffer[I830_DESTREG_SENABLE]; - i830->meta.Buffer[I830_DESTREG_SR1] = i830->state.Buffer[I830_DESTREG_SR1]; - i830->meta.Buffer[I830_DESTREG_SR2] = i830->state.Buffer[I830_DESTREG_SR2]; - i830->meta.emitted &= ~I830_UPLOAD_BUFFERS; -} - - - -/* Select between front and back draw buffers. - */ -static void -meta_draw_region(struct intel_context *intel, - struct intel_region *color_region, - struct intel_region *depth_region) -{ - struct i830_context *i830 = i830_context(&intel->ctx); - - i830_state_draw_region(intel, &i830->meta, color_region, depth_region); -} - - -/* Operations where the 3D engine is decoupled temporarily from the - * current GL state and used for other purposes than simply rendering - * incoming triangles. - */ -static void -install_meta_state(struct intel_context *intel) -{ - struct i830_context *i830 = i830_context(&intel->ctx); - memcpy(&i830->meta, &i830->initial, sizeof(i830->meta)); - - i830->meta.active = ACTIVE; - i830->meta.emitted = 0; - - SET_STATE(i830, meta); - set_vertex_format(intel); - set_no_texture(intel); -} - -static void -leave_meta_state(struct intel_context *intel) -{ - struct i830_context *i830 = i830_context(&intel->ctx); - intel_region_release(&i830->meta.draw_region); - intel_region_release(&i830->meta.depth_region); -/* intel_region_release(intel, &i830->meta.tex_region[0]); */ - SET_STATE(i830, state); -} - - - -void -i830InitMetaFuncs(struct i830_context *i830) -{ - i830->intel.vtbl.install_meta_state = install_meta_state; - i830->intel.vtbl.leave_meta_state = leave_meta_state; - i830->intel.vtbl.meta_no_depth_write = set_no_depth_write; - i830->intel.vtbl.meta_no_stencil_write = set_no_stencil_write; - i830->intel.vtbl.meta_stencil_replace = set_stencil_replace; - i830->intel.vtbl.meta_depth_replace = set_depth_replace; - i830->intel.vtbl.meta_color_mask = set_color_mask; - i830->intel.vtbl.meta_no_texture = set_no_texture; - i830->intel.vtbl.meta_texture_blend_replace = set_texture_blend_replace; - i830->intel.vtbl.meta_tex_rect_source = set_tex_rect_source; - i830->intel.vtbl.meta_draw_region = meta_draw_region; - i830->intel.vtbl.meta_import_pixel_state = meta_import_pixel_state; -} diff --git a/src/mesa/drivers/dri/i915tex/i830_state.c b/src/mesa/drivers/dri/i915tex/i830_state.c index 812daa6524..4643767d70 100644 --- a/src/mesa/drivers/dri/i915tex/i830_state.c +++ b/src/mesa/drivers/dri/i915tex/i830_state.c @@ -1101,8 +1101,6 @@ i830InitState(struct i830_context *i830) i830_init_packets(i830); - intelInitState(ctx); - memcpy(&i830->initial, &i830->state, sizeof(i830->state)); i830->current = &i830->state; diff --git a/src/mesa/drivers/dri/i915tex/i915_context.c b/src/mesa/drivers/dri/i915tex/i915_context.c index fd2943e4e1..4ea8d1d1df 100644 --- a/src/mesa/drivers/dri/i915tex/i915_context.c +++ b/src/mesa/drivers/dri/i915tex/i915_context.c @@ -39,6 +39,7 @@ #include "utils.h" #include "i915_reg.h" +#include "i915_state.h" #include "intel_regions.h" #include "intel_batchbuffer.h" @@ -60,26 +61,12 @@ static const struct dri_extension i915_extensions[] = { {NULL, NULL} }; -/* Override intel default. - */ -static void -i915InvalidateState(GLcontext * ctx, GLuint new_state) -{ - _swrast_InvalidateState(ctx, new_state); - _swsetup_InvalidateState(ctx, new_state); - _vbo_InvalidateState(ctx, new_state); - _tnl_InvalidateState(ctx, new_state); - _tnl_invalidate_vertex_state(ctx, new_state); - intel_context(ctx)->NewGLState |= new_state; -} - static void i915InitDriverFunctions(struct dd_function_table *functions) { intelInitDriverFunctions(functions); i915InitFragProgFuncs(functions); - functions->UpdateState = i915InvalidateState; } @@ -98,13 +85,9 @@ i915CreateContext(const __GLcontextModes * mesaVis, if (!i915) return GL_FALSE; - if (0) - _mesa_printf("\ntexmem-0-3 branch\n\n"); - i915InitVtbl(i915); - i915InitMetaFuncs(i915); - i915InitDriverFunctions(&functions); + i915_init_state(i915); if (!intelInitContext(intel, mesaVis, driContextPriv, sharedContextPrivate, &functions)) { @@ -158,7 +141,5 @@ i915CreateContext(const __GLcontextModes * mesaVis, intel->verts = TNL_CONTEXT(ctx)->clipspace.vertex_buf; - i915InitState(i915); - return GL_TRUE; } diff --git a/src/mesa/drivers/dri/i915tex/i915_context.h b/src/mesa/drivers/dri/i915tex/i915_context.h index 3dc0f9d81c..68530d7d5d 100644 --- a/src/mesa/drivers/dri/i915tex/i915_context.h +++ b/src/mesa/drivers/dri/i915tex/i915_context.h @@ -30,85 +30,16 @@ #include "intel_context.h" -#define I915_FALLBACK_TEXTURE 0x1000 -#define I915_FALLBACK_COLORMASK 0x2000 -#define I915_FALLBACK_STENCIL 0x4000 -#define I915_FALLBACK_STIPPLE 0x8000 -#define I915_FALLBACK_PROGRAM 0x10000 -#define I915_FALLBACK_LOGICOP 0x20000 -#define I915_FALLBACK_POLYGON_SMOOTH 0x40000 -#define I915_FALLBACK_POINT_SMOOTH 0x80000 - -#define I915_UPLOAD_CTX 0x1 -#define I915_UPLOAD_BUFFERS 0x2 -#define I915_UPLOAD_STIPPLE 0x4 -#define I915_UPLOAD_PROGRAM 0x8 -#define I915_UPLOAD_CONSTANTS 0x10 -#define I915_UPLOAD_FOG 0x20 -#define I915_UPLOAD_INVARIENT 0x40 -#define I915_UPLOAD_DEFAULTS 0x80 -#define I915_UPLOAD_TEX(i) (0x00010000<<(i)) -#define I915_UPLOAD_TEX_ALL (0x00ff0000) -#define I915_UPLOAD_TEX_0_SHIFT 16 - - -/* State structure offsets - these will probably disappear. - */ -#define I915_DESTREG_CBUFADDR0 0 -#define I915_DESTREG_CBUFADDR1 1 -#define I915_DESTREG_DBUFADDR0 3 -#define I915_DESTREG_DBUFADDR1 4 -#define I915_DESTREG_DV0 6 -#define I915_DESTREG_DV1 7 -#define I915_DESTREG_SENABLE 8 -#define I915_DESTREG_SR0 9 -#define I915_DESTREG_SR1 10 -#define I915_DESTREG_SR2 11 -#define I915_DEST_SETUP_SIZE 12 - -#define I915_CTXREG_STATE4 0 -#define I915_CTXREG_LI 1 -#define I915_CTXREG_LIS2 2 -#define I915_CTXREG_LIS4 3 -#define I915_CTXREG_LIS5 4 -#define I915_CTXREG_LIS6 5 -#define I915_CTXREG_IAB 6 -#define I915_CTXREG_BLENDCOLOR0 7 -#define I915_CTXREG_BLENDCOLOR1 8 -#define I915_CTX_SETUP_SIZE 9 - -#define I915_FOGREG_COLOR 0 -#define I915_FOGREG_MODE0 1 -#define I915_FOGREG_MODE1 2 -#define I915_FOGREG_MODE2 3 -#define I915_FOGREG_MODE3 4 -#define I915_FOG_SETUP_SIZE 5 - -#define I915_STPREG_ST0 0 -#define I915_STPREG_ST1 1 -#define I915_STP_SETUP_SIZE 2 - -#define I915_TEXREG_MS3 1 -#define I915_TEXREG_MS4 2 -#define I915_TEXREG_SS2 3 -#define I915_TEXREG_SS3 4 -#define I915_TEXREG_SS4 5 -#define I915_TEX_SETUP_SIZE 6 - -#define I915_DEFREG_C0 0 -#define I915_DEFREG_C1 1 -#define I915_DEFREG_S0 2 -#define I915_DEFREG_S1 3 -#define I915_DEFREG_Z0 4 -#define I915_DEFREG_Z1 5 -#define I915_DEF_SETUP_SIZE 6 - #define I915_MAX_CONSTANT 32 #define I915_CONSTANT_SIZE (2+(4*I915_MAX_CONSTANT)) +#define I915_PROGRAM_SIZE 192 -#define I915_PROGRAM_SIZE 192 +#define I915_NEW_INPUT_SIZES (INTEL_NEW_DRIVER0<<0) +#define I915_NEW_VERTEX_FORMAT (INTEL_NEW_DRIVER0<<1) +#define I915_NEW_FRAGMENT_PROGRAM (INTEL_NEW_DRIVER0<<2) + /* Hardware version of a parsed fragment program. "Derived" from the @@ -116,27 +47,24 @@ */ struct i915_fragment_program { - struct gl_fragment_program FragProg; - - GLboolean translated; + struct gl_fragment_program Base; GLboolean error; /* If program is malformed for any reason. */ - GLuint nr_tex_indirect; - GLuint nr_tex_insn; - GLuint nr_alu_insn; - GLuint nr_decl_insn; - + GLuint id; /* String id */ + GLboolean translated; + /* Decls + instructions: + */ + GLuint program[I915_PROGRAM_SIZE]; + GLuint program_size; + + /* Constant buffer: + */ GLfloat constant[I915_MAX_CONSTANT][4]; - GLuint constant_flags[I915_MAX_CONSTANT]; GLuint nr_constants; - - - /* Helpers for i915_fragprog.c: + /* Some of which are parameters: */ - GLuint wpos_tex; - struct { GLuint reg; /* Hardware constant idx */ @@ -144,6 +72,8 @@ struct i915_fragment_program } param[I915_MAX_CONSTANT]; GLuint nr_params; + GLuint param_state; + GLuint wpos_tex; }; @@ -155,35 +85,6 @@ struct i915_fragment_program #define I915_TEX_UNITS 8 -struct i915_hw_state -{ - GLuint Ctx[I915_CTX_SETUP_SIZE]; - GLuint Buffer[I915_DEST_SETUP_SIZE]; - GLuint Stipple[I915_STP_SETUP_SIZE]; - GLuint Fog[I915_FOG_SETUP_SIZE]; - GLuint Defaults[I915_DEF_SETUP_SIZE]; - GLuint Tex[I915_TEX_UNITS][I915_TEX_SETUP_SIZE]; - GLuint Constant[I915_CONSTANT_SIZE]; - GLuint ConstantSize; - GLuint Program[I915_PROGRAM_SIZE]; - GLuint ProgramSize; - - /* Region pointers for relocation: - */ - struct intel_region *draw_region; - struct intel_region *depth_region; - - /* Regions aren't actually that appropriate here as the memory may - * be from a PBO or FBO. Just use the buffer id. Will have to do - * this for draw and depth for FBO's... - */ - struct _DriBufferObject *tex_buffer[I915_TEX_UNITS]; - GLuint tex_offset[I915_TEX_UNITS]; - - - GLuint active; /* I915_UPLOAD_* */ - GLuint emitted; /* I915_UPLOAD_* */ -}; @@ -191,9 +92,37 @@ struct i915_context { struct intel_context intel; - struct i915_fragment_program *current_program; - - struct i915_hw_state meta, initial, state, *current; + struct i915_fragment_program *fragment_program; + + struct { + /* Regions aren't actually that appropriate here as the memory may + * be from a PBO or FBO. Just use the buffer id. Will have to do + * this for draw and depth for FBO's... + */ + struct _DriBufferObject *tex_buffer[I915_TEX_UNITS]; + GLuint tex_offset[I915_TEX_UNITS]; + } state; + + struct { + struct intel_tracked_state tracked_state; + + /* For short-circuiting + */ + GLfloat last_buf[I915_MAX_CONSTANT][4]; + GLuint last_bufsz; + } constants; + + struct { + /* I915_NEW_INPUT_DIMENSIONS + */ + GLubyte input_sizes[FRAG_ATTRIB_MAX]; + + GLuint LIS2; + GLuint LIS4; + } fragprog; + + + GLuint program_id; }; @@ -203,34 +132,6 @@ struct i915_context */ extern void i915InitVtbl(struct i915_context *i915); -extern void -i915_state_draw_region(struct intel_context *intel, - struct i915_hw_state *state, - struct intel_region *color_region, - struct intel_region *depth_region); - - - -#define SZ_TO_HW(sz) ((sz-2)&0x3) -#define EMIT_SZ(sz) (EMIT_1F + (sz) - 1) -#define EMIT_ATTR( ATTR, STYLE, S4, SZ ) \ -do { \ - intel->vertex_attrs[intel->vertex_attr_count].attrib = (ATTR); \ - intel->vertex_attrs[intel->vertex_attr_count].format = (STYLE); \ - s4 |= S4; \ - intel->vertex_attr_count++; \ - offset += (SZ); \ -} while (0) - -#define EMIT_PAD( N ) \ -do { \ - intel->vertex_attrs[intel->vertex_attr_count].attrib = 0; \ - intel->vertex_attrs[intel->vertex_attr_count].format = EMIT_PAD; \ - intel->vertex_attrs[intel->vertex_attr_count].offset = (N); \ - intel->vertex_attr_count++; \ - offset += (N); \ -} while (0) - /*====================================================================== @@ -242,24 +143,9 @@ extern GLboolean i915CreateContext(const __GLcontextModes * mesaVis, /*====================================================================== - * i915_texprog.c - */ -extern void i915ValidateTextureProgram(struct i915_context *i915); - - -/*====================================================================== - * i915_debug.c - */ -extern void i915_disassemble_program(const GLuint * program, GLuint sz); -extern void i915_print_ureg(const char *msg, GLuint ureg); - - -/*====================================================================== * i915_state.c */ extern void i915InitStateFunctions(struct dd_function_table *functions); -extern void i915InitState(struct i915_context *i915); -extern void i915_update_fog(GLcontext * ctx); /*====================================================================== @@ -268,16 +154,11 @@ extern void i915_update_fog(GLcontext * ctx); extern void i915UpdateTextureState(struct intel_context *intel); extern void i915InitTextureFuncs(struct dd_function_table *functions); -/*====================================================================== - * i915_metaops.c - */ -void i915InitMetaFuncs(struct i915_context *i915); /*====================================================================== - * i915_fragprog.c + * i915_program.c */ -extern void i915ValidateFragmentProgram(struct i915_context *i915); extern void i915InitFragProgFuncs(struct dd_function_table *functions); /*====================================================================== diff --git a/src/mesa/drivers/dri/i915tex/i915_fp.c b/src/mesa/drivers/dri/i915tex/i915_fp.c deleted file mode 100644 index 5b2ccda191..0000000000 --- a/src/mesa/drivers/dri/i915tex/i915_fp.c +++ /dev/null @@ -1,295 +0,0 @@ -/************************************************************************** - * - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - **************************************************************************/ - -#include "glheader.h" -#include "macros.h" -#include "enums.h" - -#include "tnl/tnl.h" -#include "tnl/t_context.h" -#include "intel_batchbuffer.h" - -#include "i915_reg.h" -#include "i915_context.h" -#include "i915_program.h" - -#include "program_instruction.h" -#include "program.h" -#include "programopt.h" - - - -static void -track_params(struct i915_fragment_program *p) -{ - GLint i; - - if (p->nr_params) - _mesa_load_state_parameters(p->ctx, p->FragProg.Base.Parameters); - - for (i = 0; i < p->nr_params; i++) { - GLint reg = p->param[i].reg; - COPY_4V(p->constant[reg], p->param[i].values); - } -} - - -static void -i915BindProgram(GLcontext * ctx, GLenum target, struct gl_program *prog) -{ - if (target == GL_FRAGMENT_PROGRAM_ARB) { - struct i915_context *i915 = I915_CONTEXT(ctx); - struct i915_fragment_program *p = (struct i915_fragment_program *) prog; - - if (i915->current_program == p) - return; - - i915->current_program = p; - - assert(p->on_hardware == 0); - assert(p->params_uptodate == 0); - - /* Hack: make sure fog is correctly enabled according to this - * fragment program's fog options. - */ - ctx->Driver.Enable(ctx, GL_FRAGMENT_PROGRAM_ARB, - ctx->FragmentProgram.Enabled); - } -} - -static struct gl_program * -i915NewProgram(GLcontext * ctx, GLenum target, GLuint id) -{ - switch (target) { - case GL_VERTEX_PROGRAM_ARB: - return _mesa_init_vertex_program(ctx, CALLOC_STRUCT(gl_vertex_program), - target, id); - - case GL_FRAGMENT_PROGRAM_ARB:{ - struct i915_fragment_program *prog = - CALLOC_STRUCT(i915_fragment_program); - if (prog) { - i915_init_program(I915_CONTEXT(ctx), prog); - - return _mesa_init_fragment_program(ctx, &prog->FragProg, - target, id); - } - else - return NULL; - } - - default: - /* Just fallback: - */ - return _mesa_new_program(ctx, target, id); - } -} - -static void -i915DeleteProgram(GLcontext * ctx, struct gl_program *prog) -{ - if (prog->Target == GL_FRAGMENT_PROGRAM_ARB) { - struct i915_context *i915 = I915_CONTEXT(ctx); - struct i915_fragment_program *p = (struct i915_fragment_program *) prog; - - if (i915->current_program == p) - i915->current_program = 0; - } - - _mesa_delete_program(ctx, prog); -} - - -static GLboolean -i915IsProgramNative(GLcontext * ctx, GLenum target, struct gl_program *prog) -{ - if (target == GL_FRAGMENT_PROGRAM_ARB) { - struct i915_fragment_program *p = (struct i915_fragment_program *) prog; - - if (!p->translated) - translate_program(p); - - return !p->error; - } - else - return GL_TRUE; -} - -static void -i915ProgramStringNotify(GLcontext * ctx, - GLenum target, struct gl_program *prog) -{ - if (target == GL_FRAGMENT_PROGRAM_ARB) { - struct i915_fragment_program *p = (struct i915_fragment_program *) prog; - p->translated = 0; - - /* Hack: make sure fog is correctly enabled according to this - * fragment program's fog options. - */ - ctx->Driver.Enable(ctx, GL_FRAGMENT_PROGRAM_ARB, - ctx->FragmentProgram.Enabled); - - if (p->FragProg.FogOption) { - /* add extra instructions to do fog, then turn off FogOption field */ - _mesa_append_fog_code(ctx, &p->FragProg); - p->FragProg.FogOption = GL_NONE; - } - } - - _tnl_program_string(ctx, target, prog); -} - - -void -i915ValidateFragmentProgram(struct i915_context *i915) -{ - GLcontext *ctx = &i915->intel.ctx; - struct intel_context *intel = intel_context(ctx); - TNLcontext *tnl = TNL_CONTEXT(ctx); - struct vertex_buffer *VB = &tnl->vb; - - struct i915_fragment_program *p = - (struct i915_fragment_program *) ctx->FragmentProgram._Current; - - const GLuint inputsRead = p->FragProg.Base.InputsRead; - GLuint s4 = i915->state.Ctx[I915_CTXREG_LIS4] & ~S4_VFMT_MASK; - GLuint s2 = S2_TEXCOORD_NONE; - int i, offset = 0; - - if (i915->current_program != p) { - i915->current_program = p; - } - - - /* Important: - */ - VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr; - - if (!p->translated) - translate_program(p); - - intel->vertex_attr_count = 0; - intel->wpos_offset = 0; - intel->wpos_size = 0; - intel->coloroffset = 0; - intel->specoffset = 0; - - if (inputsRead & FRAG_BITS_TEX_ANY) { - EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_4F_VIEWPORT, S4_VFMT_XYZW, 16); - } - else { - EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_3F_VIEWPORT, S4_VFMT_XYZ, 12); - } - - if (inputsRead & FRAG_BIT_COL0) { - intel->coloroffset = offset / 4; - EMIT_ATTR(_TNL_ATTRIB_COLOR0, EMIT_4UB_4F_BGRA, S4_VFMT_COLOR, 4); - } - - if ((inputsRead & (FRAG_BIT_COL1 | FRAG_BIT_FOGC)) || - i915->vertex_fog != I915_FOG_NONE) { - - if (inputsRead & FRAG_BIT_COL1) { - intel->specoffset = offset / 4; - EMIT_ATTR(_TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR, S4_VFMT_SPEC_FOG, 3); - } - else - EMIT_PAD(3); - - if ((inputsRead & FRAG_BIT_FOGC) || i915->vertex_fog != I915_FOG_NONE) - EMIT_ATTR(_TNL_ATTRIB_FOG, EMIT_1UB_1F, S4_VFMT_SPEC_FOG, 1); - else - EMIT_PAD(1); - } - - /* XXX this was disabled, but enabling this code helped fix the Glean - * tfragprog1 fog tests. - */ - if ((inputsRead & FRAG_BIT_FOGC) || i915->vertex_fog != I915_FOG_NONE) { - EMIT_ATTR(_TNL_ATTRIB_FOG, EMIT_1F, S4_VFMT_FOG_PARAM, 4); - } - - for (i = 0; i < p->ctx->Const.MaxTextureCoordUnits; i++) { - if (inputsRead & FRAG_BIT_TEX(i)) { - int sz = VB->TexCoordPtr[i]->size; - - s2 &= ~S2_TEXCOORD_FMT(i, S2_TEXCOORD_FMT0_MASK); - s2 |= S2_TEXCOORD_FMT(i, SZ_TO_HW(sz)); - - EMIT_ATTR(_TNL_ATTRIB_TEX0 + i, EMIT_SZ(sz), 0, sz * 4); - } - else if (i == p->wpos_tex) { - - /* If WPOS is required, duplicate the XYZ position data in an - * unused texture coordinate: - */ - s2 &= ~S2_TEXCOORD_FMT(i, S2_TEXCOORD_FMT0_MASK); - s2 |= S2_TEXCOORD_FMT(i, SZ_TO_HW(3)); - - intel->wpos_offset = offset; - intel->wpos_size = 3 * sizeof(GLuint); - - EMIT_PAD(intel->wpos_size); - } - } - - if (s2 != i915->state.Ctx[I915_CTXREG_LIS2] || - s4 != i915->state.Ctx[I915_CTXREG_LIS4]) { - int k; - - I915_STATECHANGE(i915, I915_UPLOAD_CTX); - - /* Must do this *after* statechange, so as not to affect - * buffered vertices reliant on the old state: - */ - intel->vertex_size = _tnl_install_attrs(&intel->ctx, - intel->vertex_attrs, - intel->vertex_attr_count, - intel->ViewportMatrix.m, 0); - - intel->vertex_size >>= 2; - - i915->state.Ctx[I915_CTXREG_LIS2] = s2; - i915->state.Ctx[I915_CTXREG_LIS4] = s4; - } - - if (!p->params_uptodate) - track_params(p); - - - i915_upload_program(i915, p); -} - -void -i915InitFragProgFuncs(struct dd_function_table *functions) -{ - functions->BindProgram = i915BindProgram; - functions->NewProgram = i915NewProgram; - functions->DeleteProgram = i915DeleteProgram; - functions->IsProgramNative = i915IsProgramNative; - functions->ProgramStringNotify = i915ProgramStringNotify; -} diff --git a/src/mesa/drivers/dri/i915tex/i915_fp.h b/src/mesa/drivers/dri/i915tex/i915_fp.h deleted file mode 100644 index 8af92c82be..0000000000 --- a/src/mesa/drivers/dri/i915tex/i915_fp.h +++ /dev/null @@ -1,44 +0,0 @@ - -struct i915_fp_compile { - GLcontext *ctx; - - struct i915_fragment_program *fp; - - GLuint declarations[I915_PROGRAM_SIZE]; - GLuint program[I915_PROGRAM_SIZE]; - - GLfloat constant[I915_MAX_CONSTANT][4]; - GLuint constant_flags[I915_MAX_CONSTANT]; - GLuint nr_constants; - - GLuint *csr; /* Cursor, points into program. - */ - - GLuint *decl; /* Cursor, points into declarations. - */ - - GLuint decl_s; /* flags for which s regs need to be decl'd */ - GLuint decl_t; /* flags for which t regs need to be decl'd */ - - GLuint temp_flag; /* Tracks temporary regs which are in - * use. - */ - - GLuint utemp_flag; /* Tracks TYPE_U temporary regs which are in - * use. - */ - - - - /* Helpers for i915_fragprog.c: - */ - GLuint wpos_tex; - - struct - { - GLuint reg; /* Hardware constant idx */ - const GLfloat *values; /* Pointer to tracked values */ - } param[I915_MAX_CONSTANT]; - GLuint nr_params; - -}; diff --git a/src/mesa/drivers/dri/i915tex/i915_fp_debug.c b/src/mesa/drivers/dri/i915tex/i915_fp_debug.c deleted file mode 100644 index 974527e14c..0000000000 --- a/src/mesa/drivers/dri/i915tex/i915_fp_debug.c +++ /dev/null @@ -1,334 +0,0 @@ -/************************************************************************** - * - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - **************************************************************************/ - -#include "i915_reg.h" -#include "i915_context.h" -#include <stdio.h> - - -static const char *opcodes[0x20] = { - "NOP", - "ADD", - "MOV", - "MUL", - "MAD", - "DP2ADD", - "DP3", - "DP4", - "FRC", - "RCP", - "RSQ", - "EXP", - "LOG", - "CMP", - "MIN", - "MAX", - "FLR", - "MOD", - "TRC", - "SGE", - "SLT", - "TEXLD", - "TEXLDP", - "TEXLDB", - "TEXKILL", - "DCL", - "0x1a", - "0x1b", - "0x1c", - "0x1d", - "0x1e", - "0x1f", -}; - - -static const int args[0x20] = { - 0, /* 0 nop */ - 2, /* 1 add */ - 1, /* 2 mov */ - 2, /* 3 m ul */ - 3, /* 4 mad */ - 3, /* 5 dp2add */ - 2, /* 6 dp3 */ - 2, /* 7 dp4 */ - 1, /* 8 frc */ - 1, /* 9 rcp */ - 1, /* a rsq */ - 1, /* b exp */ - 1, /* c log */ - 3, /* d cmp */ - 2, /* e min */ - 2, /* f max */ - 1, /* 10 flr */ - 1, /* 11 mod */ - 1, /* 12 trc */ - 2, /* 13 sge */ - 2, /* 14 slt */ - 1, - 1, - 1, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 0, -}; - - -static const char *regname[0x8] = { - "R", - "T", - "CONST", - "S", - "OC", - "OD", - "U", - "UNKNOWN", -}; - -static void -print_reg_type_nr(GLuint type, GLuint nr) -{ - switch (type) { - case REG_TYPE_T: - switch (nr) { - case T_DIFFUSE: - fprintf(stderr, "T_DIFFUSE"); - return; - case T_SPECULAR: - fprintf(stderr, "T_SPECULAR"); - return; - case T_FOG_W: - fprintf(stderr, "T_FOG_W"); - return; - default: - fprintf(stderr, "T_TEX%d", nr); - return; - } - case REG_TYPE_OC: - if (nr == 0) { - fprintf(stderr, "oC"); - return; - } - break; - case REG_TYPE_OD: - if (nr == 0) { - fprintf(stderr, "oD"); - return; - } - break; - default: - break; - } - - fprintf(stderr, "%s[%d]", regname[type], nr); -} - -#define REG_SWIZZLE_MASK 0x7777 -#define REG_NEGATE_MASK 0x8888 - -#define REG_SWIZZLE_XYZW ((SRC_X << A2_SRC2_CHANNEL_X_SHIFT) | \ - (SRC_Y << A2_SRC2_CHANNEL_Y_SHIFT) | \ - (SRC_Z << A2_SRC2_CHANNEL_Z_SHIFT) | \ - (SRC_W << A2_SRC2_CHANNEL_W_SHIFT)) - - -static void -print_reg_neg_swizzle(GLuint reg) -{ - int i; - - if ((reg & REG_SWIZZLE_MASK) == REG_SWIZZLE_XYZW && - (reg & REG_NEGATE_MASK) == 0) - return; - - fprintf(stderr, "."); - - for (i = 3; i >= 0; i--) { - if (reg & (1 << ((i * 4) + 3))) - fprintf(stderr, "-"); - - switch ((reg >> (i * 4)) & 0x7) { - case 0: - fprintf(stderr, "x"); - break; - case 1: - fprintf(stderr, "y"); - break; - case 2: - fprintf(stderr, "z"); - break; - case 3: - fprintf(stderr, "w"); - break; - case 4: - fprintf(stderr, "0"); - break; - case 5: - fprintf(stderr, "1"); - break; - default: - fprintf(stderr, "?"); - break; - } - } -} - - -static void -print_src_reg(GLuint dword) -{ - GLuint nr = (dword >> A2_SRC2_NR_SHIFT) & REG_NR_MASK; - GLuint type = (dword >> A2_SRC2_TYPE_SHIFT) & REG_TYPE_MASK; - print_reg_type_nr(type, nr); - print_reg_neg_swizzle(dword); -} - -void -i915_print_ureg(const char *msg, GLuint ureg) -{ - fprintf(stderr, "%s: ", msg); - print_src_reg(ureg >> 8); - fprintf(stderr, "\n"); -} - -static void -print_dest_reg(GLuint dword) -{ - GLuint nr = (dword >> A0_DEST_NR_SHIFT) & REG_NR_MASK; - GLuint type = (dword >> A0_DEST_TYPE_SHIFT) & REG_TYPE_MASK; - print_reg_type_nr(type, nr); - if ((dword & A0_DEST_CHANNEL_ALL) == A0_DEST_CHANNEL_ALL) - return; - fprintf(stderr, "."); - if (dword & A0_DEST_CHANNEL_X) - fprintf(stderr, "x"); - if (dword & A0_DEST_CHANNEL_Y) - fprintf(stderr, "y"); - if (dword & A0_DEST_CHANNEL_Z) - fprintf(stderr, "z"); - if (dword & A0_DEST_CHANNEL_W) - fprintf(stderr, "w"); -} - - -#define GET_SRC0_REG(r0, r1) ((r0<<14)|(r1>>A1_SRC0_CHANNEL_W_SHIFT)) -#define GET_SRC1_REG(r0, r1) ((r0<<8)|(r1>>A2_SRC1_CHANNEL_W_SHIFT)) -#define GET_SRC2_REG(r) (r) - - -static void -print_arith_op(GLuint opcode, const GLuint * program) -{ - if (opcode != A0_NOP) { - print_dest_reg(program[0]); - if (program[0] & A0_DEST_SATURATE) - fprintf(stderr, " = SATURATE "); - else - fprintf(stderr, " = "); - } - - fprintf(stderr, "%s ", opcodes[opcode]); - - print_src_reg(GET_SRC0_REG(program[0], program[1])); - if (args[opcode] == 1) { - fprintf(stderr, "\n"); - return; - } - - fprintf(stderr, ", "); - print_src_reg(GET_SRC1_REG(program[1], program[2])); - if (args[opcode] == 2) { - fprintf(stderr, "\n"); - return; - } - - fprintf(stderr, ", "); - print_src_reg(GET_SRC2_REG(program[2])); - fprintf(stderr, "\n"); - return; -} - - -static void -print_tex_op(GLuint opcode, const GLuint * program) -{ - print_dest_reg(program[0] | A0_DEST_CHANNEL_ALL); - fprintf(stderr, " = "); - - fprintf(stderr, "%s ", opcodes[opcode]); - - fprintf(stderr, "S[%d],", program[0] & T0_SAMPLER_NR_MASK); - - print_reg_type_nr((program[1] >> T1_ADDRESS_REG_TYPE_SHIFT) & - REG_TYPE_MASK, - (program[1] >> T1_ADDRESS_REG_NR_SHIFT) & REG_NR_MASK); - fprintf(stderr, "\n"); -} - -static void -print_dcl_op(GLuint opcode, const GLuint * program) -{ - fprintf(stderr, "%s ", opcodes[opcode]); - print_dest_reg(program[0] | A0_DEST_CHANNEL_ALL); - fprintf(stderr, "\n"); -} - - -void -i915_disassemble_program(const GLuint * program, GLuint sz) -{ - GLuint size = program[0] & 0x1ff; - GLint i; - - fprintf(stderr, "BEGIN\n"); - - if (size + 2 != sz) { - fprintf(stderr, "%s: program size mismatch %d/%d\n", __FUNCTION__, - size + 2, sz); - exit(1); - } - - program++; - for (i = 1; i < sz; i += 3, program += 3) { - GLuint opcode = program[0] & (0x1f << 24); - - if ((GLint) opcode >= A0_NOP && opcode <= A0_SLT) - print_arith_op(opcode >> 24, program); - else if (opcode >= T0_TEXLD && opcode <= T0_TEXKILL) - print_tex_op(opcode >> 24, program); - else if (opcode == D0_DCL) - print_dcl_op(opcode >> 24, program); - else - fprintf(stderr, "Unknown opcode 0x%x\n", opcode); - } - - fprintf(stderr, "END\n\n"); -} diff --git a/src/mesa/drivers/dri/i915tex/i915_fp_emit.c b/src/mesa/drivers/dri/i915tex/i915_fp_emit.c deleted file mode 100644 index 9e4d598942..0000000000 --- a/src/mesa/drivers/dri/i915tex/i915_fp_emit.c +++ /dev/null @@ -1,487 +0,0 @@ -/************************************************************************** - * - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - **************************************************************************/ - -#include <strings.h> - -#include "glheader.h" -#include "macros.h" -#include "enums.h" - -#include "tnl/t_context.h" -#include "intel_batchbuffer.h" - -#include "i915_reg.h" -#include "i915_context.h" -#include "i915_program.h" - - -#define A0_DEST( reg ) (((reg)&UREG_TYPE_NR_MASK)>>UREG_A0_DEST_SHIFT_LEFT) -#define D0_DEST( reg ) (((reg)&UREG_TYPE_NR_MASK)>>UREG_A0_DEST_SHIFT_LEFT) -#define T0_DEST( reg ) (((reg)&UREG_TYPE_NR_MASK)>>UREG_A0_DEST_SHIFT_LEFT) -#define A0_SRC0( reg ) (((reg)&UREG_MASK)>>UREG_A0_SRC0_SHIFT_LEFT) -#define A1_SRC0( reg ) (((reg)&UREG_MASK)<<UREG_A1_SRC0_SHIFT_RIGHT) -#define A1_SRC1( reg ) (((reg)&UREG_MASK)>>UREG_A1_SRC1_SHIFT_LEFT) -#define A2_SRC1( reg ) (((reg)&UREG_MASK)<<UREG_A2_SRC1_SHIFT_RIGHT) -#define A2_SRC2( reg ) (((reg)&UREG_MASK)>>UREG_A2_SRC2_SHIFT_LEFT) - -/* These are special, and don't have swizzle/negate bits. - */ -#define T0_SAMPLER( reg ) (GET_UREG_NR(reg)<<T0_SAMPLER_NR_SHIFT) -#define T1_ADDRESS_REG( reg ) ((GET_UREG_NR(reg)<<T1_ADDRESS_REG_NR_SHIFT) | \ - (GET_UREG_TYPE(reg)<<T1_ADDRESS_REG_TYPE_SHIFT)) - - -/* Macros for translating UREG's into the various register fields used - * by the I915 programmable unit. - */ -#define UREG_A0_DEST_SHIFT_LEFT (UREG_TYPE_SHIFT - A0_DEST_TYPE_SHIFT) -#define UREG_A0_SRC0_SHIFT_LEFT (UREG_TYPE_SHIFT - A0_SRC0_TYPE_SHIFT) -#define UREG_A1_SRC0_SHIFT_RIGHT (A1_SRC0_CHANNEL_W_SHIFT - UREG_CHANNEL_W_SHIFT) -#define UREG_A1_SRC1_SHIFT_LEFT (UREG_TYPE_SHIFT - A1_SRC1_TYPE_SHIFT) -#define UREG_A2_SRC1_SHIFT_RIGHT (A2_SRC1_CHANNEL_W_SHIFT - UREG_CHANNEL_W_SHIFT) -#define UREG_A2_SRC2_SHIFT_LEFT (UREG_TYPE_SHIFT - A2_SRC2_TYPE_SHIFT) - -#define UREG_MASK 0xffffff00 -#define UREG_TYPE_NR_MASK ((REG_TYPE_MASK << UREG_TYPE_SHIFT) | \ - (REG_NR_MASK << UREG_NR_SHIFT)) - - -#define I915_CONSTFLAG_PARAM 0x1f - -GLuint -i915_get_temp(struct i915_fragment_program *p) -{ - int bit = ffs(~p->temp_flag); - if (!bit) { - fprintf(stderr, "%s: out of temporaries\n", __FILE__); - exit(1); - } - - p->temp_flag |= 1 << (bit - 1); - return UREG(REG_TYPE_R, (bit - 1)); -} - - -GLuint -i915_get_utemp(struct i915_fragment_program * p) -{ - int bit = ffs(~p->utemp_flag); - if (!bit) { - fprintf(stderr, "%s: out of temporaries\n", __FILE__); - exit(1); - } - - p->utemp_flag |= 1 << (bit - 1); - return UREG(REG_TYPE_U, (bit - 1)); -} - -void -i915_release_utemps(struct i915_fragment_program *p) -{ - p->utemp_flag = ~0x7; -} - - -GLuint -i915_emit_decl(struct i915_fragment_program *p, - GLuint type, GLuint nr, GLuint d0_flags) -{ - GLuint reg = UREG(type, nr); - - if (type == REG_TYPE_T) { - if (p->decl_t & (1 << nr)) - return reg; - - p->decl_t |= (1 << nr); - } - else if (type == REG_TYPE_S) { - if (p->decl_s & (1 << nr)) - return reg; - - p->decl_s |= (1 << nr); - } - else - return reg; - - *(p->decl++) = (D0_DCL | D0_DEST(reg) | d0_flags); - *(p->decl++) = D1_MBZ; - *(p->decl++) = D2_MBZ; - - p->nr_decl_insn++; - return reg; -} - -GLuint -i915_emit_arith(struct i915_fragment_program * p, - GLuint op, - GLuint dest, - GLuint mask, - GLuint saturate, GLuint src0, GLuint src1, GLuint src2) -{ - GLuint c[3]; - GLuint nr_const = 0; - - assert(GET_UREG_TYPE(dest) != REG_TYPE_CONST); - dest = UREG(GET_UREG_TYPE(dest), GET_UREG_NR(dest)); - assert(dest); - - if (GET_UREG_TYPE(src0) == REG_TYPE_CONST) - c[nr_const++] = 0; - if (GET_UREG_TYPE(src1) == REG_TYPE_CONST) - c[nr_const++] = 1; - if (GET_UREG_TYPE(src2) == REG_TYPE_CONST) - c[nr_const++] = 2; - - /* Recursively call this function to MOV additional const values - * into temporary registers. Use utemp registers for this - - * currently shouldn't be possible to run out, but keep an eye on - * this. - */ - if (nr_const > 1) { - GLuint s[3], first, i, old_utemp_flag; - - s[0] = src0; - s[1] = src1; - s[2] = src2; - old_utemp_flag = p->utemp_flag; - - first = GET_UREG_NR(s[c[0]]); - for (i = 1; i < nr_const; i++) { - if (GET_UREG_NR(s[c[i]]) != first) { - GLuint tmp = i915_get_utemp(p); - - i915_emit_arith(p, A0_MOV, tmp, A0_DEST_CHANNEL_ALL, 0, - s[c[i]], 0, 0); - s[c[i]] = tmp; - } - } - - src0 = s[0]; - src1 = s[1]; - src2 = s[2]; - p->utemp_flag = old_utemp_flag; /* restore */ - } - - *(p->csr++) = (op | A0_DEST(dest) | mask | saturate | A0_SRC0(src0)); - *(p->csr++) = (A1_SRC0(src0) | A1_SRC1(src1)); - *(p->csr++) = (A2_SRC1(src1) | A2_SRC2(src2)); - - p->nr_alu_insn++; - return dest; -} - -GLuint i915_emit_texld( struct i915_fragment_program *p, - GLuint dest, - GLuint destmask, - GLuint sampler, - GLuint coord, - GLuint op ) -{ - if (coord != UREG(GET_UREG_TYPE(coord), GET_UREG_NR(coord))) { - /* No real way to work around this in the general case - need to - * allocate and declare a new temporary register (a utemp won't - * do). Will fallback for now. - */ - i915_program_error(p, "Can't (yet) swizzle TEX arguments"); - return 0; - } - - /* Don't worry about saturate as we only support - */ - if (destmask != A0_DEST_CHANNEL_ALL) { - GLuint tmp = i915_get_utemp(p); - i915_emit_texld( p, tmp, A0_DEST_CHANNEL_ALL, sampler, coord, op ); - i915_emit_arith( p, A0_MOV, dest, destmask, 0, tmp, 0, 0 ); - return dest; - } - else { - assert(GET_UREG_TYPE(dest) != REG_TYPE_CONST); - assert(dest = UREG(GET_UREG_TYPE(dest), GET_UREG_NR(dest))); - - if (GET_UREG_TYPE(coord) != REG_TYPE_T) { - p->nr_tex_indirect++; - } - - *(p->csr++) = (op | - T0_DEST( dest ) | - T0_SAMPLER( sampler )); - - *(p->csr++) = T1_ADDRESS_REG( coord ); - *(p->csr++) = T2_MBZ; - - p->nr_tex_insn++; - return dest; - } -} - - -GLuint -i915_emit_const1f(struct i915_fragment_program * p, GLfloat c0) -{ - GLint reg, idx; - - if (c0 == 0.0) - return swizzle(UREG(REG_TYPE_R, 0), ZERO, ZERO, ZERO, ZERO); - if (c0 == 1.0) - return swizzle(UREG(REG_TYPE_R, 0), ONE, ONE, ONE, ONE); - - for (reg = 0; reg < I915_MAX_CONSTANT; reg++) { - if (p->constant_flags[reg] == I915_CONSTFLAG_PARAM) - continue; - for (idx = 0; idx < 4; idx++) { - if (!(p->constant_flags[reg] & (1 << idx)) || - p->constant[reg][idx] == c0) { - p->constant[reg][idx] = c0; - p->constant_flags[reg] |= 1 << idx; - if (reg + 1 > p->nr_constants) - p->nr_constants = reg + 1; - return swizzle(UREG(REG_TYPE_CONST, reg), idx, ZERO, ZERO, ONE); - } - } - } - - fprintf(stderr, "%s: out of constants\n", __FUNCTION__); - p->error = 1; - return 0; -} - -GLuint -i915_emit_const2f(struct i915_fragment_program * p, GLfloat c0, GLfloat c1) -{ - GLint reg, idx; - - if (c0 == 0.0) - return swizzle(i915_emit_const1f(p, c1), ZERO, X, Z, W); - if (c0 == 1.0) - return swizzle(i915_emit_const1f(p, c1), ONE, X, Z, W); - - if (c1 == 0.0) - return swizzle(i915_emit_const1f(p, c0), X, ZERO, Z, W); - if (c1 == 1.0) - return swizzle(i915_emit_const1f(p, c0), X, ONE, Z, W); - - for (reg = 0; reg < I915_MAX_CONSTANT; reg++) { - if (p->constant_flags[reg] == 0xf || - p->constant_flags[reg] == I915_CONSTFLAG_PARAM) - continue; - for (idx = 0; idx < 3; idx++) { - if (!(p->constant_flags[reg] & (3 << idx))) { - p->constant[reg][idx] = c0; - p->constant[reg][idx + 1] = c1; - p->constant_flags[reg] |= 3 << idx; - if (reg + 1 > p->nr_constants) - p->nr_constants = reg + 1; - return swizzle(UREG(REG_TYPE_CONST, reg), idx, idx + 1, ZERO, - ONE); - } - } - } - - fprintf(stderr, "%s: out of constants\n", __FUNCTION__); - p->error = 1; - return 0; -} - - - -GLuint -i915_emit_const4f(struct i915_fragment_program * p, - GLfloat c0, GLfloat c1, GLfloat c2, GLfloat c3) -{ - GLint reg; - - for (reg = 0; reg < I915_MAX_CONSTANT; reg++) { - if (p->constant_flags[reg] == 0xf && - p->constant[reg][0] == c0 && - p->constant[reg][1] == c1 && - p->constant[reg][2] == c2 && p->constant[reg][3] == c3) { - return UREG(REG_TYPE_CONST, reg); - } - else if (p->constant_flags[reg] == 0) { - p->constant[reg][0] = c0; - p->constant[reg][1] = c1; - p->constant[reg][2] = c2; - p->constant[reg][3] = c3; - p->constant_flags[reg] = 0xf; - if (reg + 1 > p->nr_constants) - p->nr_constants = reg + 1; - return UREG(REG_TYPE_CONST, reg); - } - } - - fprintf(stderr, "%s: out of constants\n", __FUNCTION__); - p->error = 1; - return 0; -} - - -GLuint -i915_emit_const4fv(struct i915_fragment_program * p, const GLfloat * c) -{ - return i915_emit_const4f(p, c[0], c[1], c[2], c[3]); -} - - -GLuint -i915_emit_param4fv(struct i915_fragment_program * p, const GLfloat * values) -{ - GLint reg, i; - - for (i = 0; i < p->nr_params; i++) { - if (p->param[i].values == values) - return UREG(REG_TYPE_CONST, p->param[i].reg); - } - - - for (reg = 0; reg < I915_MAX_CONSTANT; reg++) { - if (p->constant_flags[reg] == 0) { - p->constant_flags[reg] = I915_CONSTFLAG_PARAM; - i = p->nr_params++; - - p->param[i].values = values; - p->param[i].reg = reg; - p->params_uptodate = 0; - - if (reg + 1 > p->nr_constants) - p->nr_constants = reg + 1; - return UREG(REG_TYPE_CONST, reg); - } - } - - fprintf(stderr, "%s: out of constants\n", __FUNCTION__); - p->error = 1; - return 0; -} - - - -void -i915_program_error(struct i915_fragment_program *p, const char *msg) -{ - _mesa_problem(NULL, "i915_program_error: %s", msg); - p->error = 1; -} - - -void -i915_init_program(struct i915_context *i915, struct i915_fragment_program *p) -{ - GLcontext *ctx = &i915->intel.ctx; - TNLcontext *tnl = TNL_CONTEXT(ctx); - - p->translated = 0; - p->params_uptodate = 0; - p->error = 0; - - p->nr_tex_indirect = 1; /* correct? */ - p->nr_tex_insn = 0; - p->nr_alu_insn = 0; - p->nr_decl_insn = 0; - - p->ctx = ctx; - memset(p->constant_flags, 0, sizeof(p->constant_flags)); - - p->nr_constants = 0; - p->csr = p->program; - p->decl = p->declarations; - p->decl_s = 0; - p->decl_t = 0; - p->temp_flag = 0xffff000; - p->utemp_flag = ~0x7; - p->wpos_tex = -1; - p->nr_params = 0; - - p->src_texture = UREG_BAD; - p->src_previous = UREG(REG_TYPE_T, T_DIFFUSE); - p->last_tex_stage = 0; - p->VB = &tnl->vb; - - *(p->decl++) = _3DSTATE_PIXEL_SHADER_PROGRAM; -} - - -void -i915_fini_program(struct i915_fragment_program *p) -{ - GLuint program_size = p->csr - p->program; - GLuint decl_size = p->decl - p->declarations; - - if (p->nr_tex_indirect > I915_MAX_TEX_INDIRECT) - i915_program_error(p, "Exceeded max nr indirect texture lookups"); - - if (p->nr_tex_insn > I915_MAX_TEX_INSN) - i915_program_error(p, "Exceeded max TEX instructions"); - - if (p->nr_alu_insn > I915_MAX_ALU_INSN) - i915_program_error(p, "Exceeded max ALU instructions"); - - if (p->nr_decl_insn > I915_MAX_DECL_INSN) - i915_program_error(p, "Exceeded max DECL instructions"); - - if (p->error) { - p->FragProg.Base.NumNativeInstructions = 0; - p->FragProg.NumNativeAluInstructions = 0; - p->FragProg.NumNativeTexInstructions = 0; - p->FragProg.NumNativeTexIndirections = 0; - } - else { - p->FragProg.Base.NumNativeInstructions = (p->nr_alu_insn + - p->nr_tex_insn + - p->nr_decl_insn); - p->FragProg.NumNativeAluInstructions = p->nr_alu_insn; - p->FragProg.NumNativeTexInstructions = p->nr_tex_insn; - p->FragProg.NumNativeTexIndirections = p->nr_tex_indirect; - } - - p->declarations[0] |= program_size + decl_size - 2; -} - -void -i915_upload_program(struct i915_context *i915, - struct i915_fragment_program *p) -{ - GLuint program_size = p->csr - p->program; - GLuint decl_size = p->decl - p->declarations; - - FALLBACK(&i915->intel, I915_FALLBACK_PROGRAM, p->error); - - /* Could just go straight to the batchbuffer from here: - */ - if (i915->state.ProgramSize != (program_size + decl_size) || - memcmp(i915->state.Program + decl_size, p->program, - program_size * sizeof(int)) != 0) { - I915_STATECHANGE(i915, I915_UPLOAD_PROGRAM); - memcpy(i915->state.Program, p->declarations, decl_size * sizeof(int)); - memcpy(i915->state.Program + decl_size, p->program, - program_size * sizeof(int)); - i915->state.ProgramSize = decl_size + program_size; - } - - - /* Set dependent state variables - */ -} diff --git a/src/mesa/drivers/dri/i915tex/i915_fp_emit.h b/src/mesa/drivers/dri/i915tex/i915_fp_emit.h deleted file mode 100644 index 3c12b34f16..0000000000 --- a/src/mesa/drivers/dri/i915tex/i915_fp_emit.h +++ /dev/null @@ -1,160 +0,0 @@ -/************************************************************************** - * - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - **************************************************************************/ - - -#ifndef I915_PROGRAM_H -#define I915_PROGRAM_H - -#include "i915_context.h" -#include "i915_reg.h" - - - -/* Having zero and one in here makes the definition of swizzle a lot - * easier. - */ -#define UREG_TYPE_SHIFT 29 -#define UREG_NR_SHIFT 24 -#define UREG_CHANNEL_X_NEGATE_SHIFT 23 -#define UREG_CHANNEL_X_SHIFT 20 -#define UREG_CHANNEL_Y_NEGATE_SHIFT 19 -#define UREG_CHANNEL_Y_SHIFT 16 -#define UREG_CHANNEL_Z_NEGATE_SHIFT 15 -#define UREG_CHANNEL_Z_SHIFT 12 -#define UREG_CHANNEL_W_NEGATE_SHIFT 11 -#define UREG_CHANNEL_W_SHIFT 8 -#define UREG_CHANNEL_ZERO_NEGATE_MBZ 5 -#define UREG_CHANNEL_ZERO_SHIFT 4 -#define UREG_CHANNEL_ONE_NEGATE_MBZ 1 -#define UREG_CHANNEL_ONE_SHIFT 0 - -#define UREG_BAD 0xffffffff /* not a valid ureg */ - -#define X SRC_X -#define Y SRC_Y -#define Z SRC_Z -#define W SRC_W -#define ZERO SRC_ZERO -#define ONE SRC_ONE - -/* Construct a ureg: - */ -#define UREG( type, nr ) (((type)<< UREG_TYPE_SHIFT) | \ - ((nr) << UREG_NR_SHIFT) | \ - (X << UREG_CHANNEL_X_SHIFT) | \ - (Y << UREG_CHANNEL_Y_SHIFT) | \ - (Z << UREG_CHANNEL_Z_SHIFT) | \ - (W << UREG_CHANNEL_W_SHIFT) | \ - (ZERO << UREG_CHANNEL_ZERO_SHIFT) | \ - (ONE << UREG_CHANNEL_ONE_SHIFT)) - -#define GET_CHANNEL_SRC( reg, channel ) ((reg<<(channel*4)) & (0xf<<20)) -#define CHANNEL_SRC( src, channel ) (src>>(channel*4)) - -#define GET_UREG_TYPE(reg) (((reg)>>UREG_TYPE_SHIFT)®_TYPE_MASK) -#define GET_UREG_NR(reg) (((reg)>>UREG_NR_SHIFT)®_NR_MASK) - - - -#define UREG_XYZW_CHANNEL_MASK 0x00ffff00 - -/* One neat thing about the UREG representation: - */ -static INLINE int -swizzle(int reg, int x, int y, int z, int w) -{ - return ((reg & ~UREG_XYZW_CHANNEL_MASK) | - CHANNEL_SRC(GET_CHANNEL_SRC(reg, x), 0) | - CHANNEL_SRC(GET_CHANNEL_SRC(reg, y), 1) | - CHANNEL_SRC(GET_CHANNEL_SRC(reg, z), 2) | - CHANNEL_SRC(GET_CHANNEL_SRC(reg, w), 3)); -} - -/* Another neat thing about the UREG representation: - */ -static INLINE int -negate(int reg, int x, int y, int z, int w) -{ - return reg ^ (((x & 1) << UREG_CHANNEL_X_NEGATE_SHIFT) | - ((y & 1) << UREG_CHANNEL_Y_NEGATE_SHIFT) | - ((z & 1) << UREG_CHANNEL_Z_NEGATE_SHIFT) | - ((w & 1) << UREG_CHANNEL_W_NEGATE_SHIFT)); -} - - -extern GLuint i915_get_temp(struct i915_fragment_program *p); -extern GLuint i915_get_utemp(struct i915_fragment_program *p); -extern void i915_release_utemps(struct i915_fragment_program *p); - - -extern GLuint i915_emit_texld(struct i915_fragment_program *p, - GLuint dest, - GLuint destmask, - GLuint sampler, GLuint coord, GLuint op); - -extern GLuint i915_emit_arith(struct i915_fragment_program *p, - GLuint op, - GLuint dest, - GLuint mask, - GLuint saturate, - GLuint src0, GLuint src1, GLuint src2); - -extern GLuint i915_emit_decl(struct i915_fragment_program *p, - GLuint type, GLuint nr, GLuint d0_flags); - - -extern GLuint i915_emit_const1f(struct i915_fragment_program *p, GLfloat c0); - -extern GLuint i915_emit_const2f(struct i915_fragment_program *p, - GLfloat c0, GLfloat c1); - -extern GLuint i915_emit_const4fv(struct i915_fragment_program *p, - const GLfloat * c); - -extern GLuint i915_emit_const4f(struct i915_fragment_program *p, - GLfloat c0, GLfloat c1, - GLfloat c2, GLfloat c3); - - -extern GLuint i915_emit_param4fv(struct i915_fragment_program *p, - const GLfloat * values); - -extern void i915_program_error(struct i915_fragment_program *p, - const char *msg); - -extern void i915_init_program(struct i915_context *i915, - struct i915_fragment_program *p); - -extern void i915_upload_program(struct i915_context *i915, - struct i915_fragment_program *p); - -extern void i915_fini_program(struct i915_fragment_program *p); - - - - -#endif diff --git a/src/mesa/drivers/dri/i915tex/i915_fp_translate.c b/src/mesa/drivers/dri/i915tex/i915_fp_translate.c deleted file mode 100644 index bbcca2ef37..0000000000 --- a/src/mesa/drivers/dri/i915tex/i915_fp_translate.c +++ /dev/null @@ -1,802 +0,0 @@ -/************************************************************************** - * - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - **************************************************************************/ - -#include "glheader.h" -#include "macros.h" -#include "enums.h" - -#include "tnl/tnl.h" -#include "tnl/t_context.h" -#include "intel_batchbuffer.h" - -#include "i915_reg.h" -#include "i915_context.h" -#include "i915_program.h" - -#include "program_instruction.h" -#include "program.h" -#include "programopt.h" - - - -/* 1, -1/3!, 1/5!, -1/7! */ -static const GLfloat sin_constants[4] = { 1.0, - -1.0 / (3 * 2 * 1), - 1.0 / (5 * 4 * 3 * 2 * 1), - -1.0 / (7 * 6 * 5 * 4 * 3 * 2 * 1) -}; - -/* 1, -1/2!, 1/4!, -1/6! */ -static const GLfloat cos_constants[4] = { 1.0, - -1.0 / (2 * 1), - 1.0 / (4 * 3 * 2 * 1), - -1.0 / (6 * 5 * 4 * 3 * 2 * 1) -}; - -/** - * Retrieve a ureg for the given source register. Will emit - * constants, apply swizzling and negation as needed. - */ -static GLuint -src_vector(struct i915_fragment_program *p, - const struct prog_src_register *source, - const struct gl_fragment_program *program) -{ - GLuint src; - - switch (source->File) { - - /* Registers: - */ - case PROGRAM_TEMPORARY: - if (source->Index >= I915_MAX_TEMPORARY) { - i915_program_error(p, "Exceeded max temporary reg"); - return 0; - } - src = UREG(REG_TYPE_R, source->Index); - break; - case PROGRAM_INPUT: - /* XXX: Packing COL1, FOGC into a single attribute works for - * texenv programs, but will fail for real fragment programs - * that use these attributes and expect them to be a full 4 - * components wide. Could use a texcoord to pass these - * attributes if necessary, but that won't work in the general - * case. - * - * We also use a texture coordinate to pass wpos when possible. - */ - switch (source->Index) { - case FRAG_ATTRIB_WPOS: - src = i915_emit_decl(p, REG_TYPE_T, p->wpos_tex, D0_CHANNEL_ALL); - break; - case FRAG_ATTRIB_COL0: - src = i915_emit_decl(p, REG_TYPE_T, T_DIFFUSE, D0_CHANNEL_ALL); - break; - case FRAG_ATTRIB_COL1: - src = i915_emit_decl(p, REG_TYPE_T, T_SPECULAR, D0_CHANNEL_XYZ); - src = swizzle(src, X, Y, Z, ONE); - break; - case FRAG_ATTRIB_FOGC: - src = i915_emit_decl(p, REG_TYPE_T, T_FOG_W, D0_CHANNEL_W); - src = swizzle(src, W, W, W, W); - break; - case FRAG_ATTRIB_TEX0: - case FRAG_ATTRIB_TEX1: - case FRAG_ATTRIB_TEX2: - case FRAG_ATTRIB_TEX3: - case FRAG_ATTRIB_TEX4: - case FRAG_ATTRIB_TEX5: - case FRAG_ATTRIB_TEX6: - case FRAG_ATTRIB_TEX7: - src = i915_emit_decl(p, REG_TYPE_T, - T_TEX0 + (source->Index - FRAG_ATTRIB_TEX0), - D0_CHANNEL_ALL); - break; - - default: - i915_program_error(p, "Bad source->Index"); - return 0; - } - break; - - /* Various paramters and env values. All emitted to - * hardware as program constants. - */ - case PROGRAM_LOCAL_PARAM: - src = i915_emit_param4fv(p, program->Base.LocalParams[source->Index]); - break; - - case PROGRAM_ENV_PARAM: - src = i915_emit_param4fv( - p, p->ctx->FragmentProgram.Parameters[source->Index]); - break; - - case PROGRAM_CONSTANT: - case PROGRAM_STATE_VAR: - case PROGRAM_NAMED_PARAM: - src = i915_emit_param4fv( - p, program->Base.Parameters->ParameterValues[source->Index]); - break; - - default: - i915_program_error(p, "Bad source->File"); - return 0; - } - - src = swizzle(src, - GET_SWZ(source->Swizzle, 0), - GET_SWZ(source->Swizzle, 1), - GET_SWZ(source->Swizzle, 2), GET_SWZ(source->Swizzle, 3)); - - if (source->NegateBase) - src = negate(src, - GET_BIT(source->NegateBase, 0), - GET_BIT(source->NegateBase, 1), - GET_BIT(source->NegateBase, 2), - GET_BIT(source->NegateBase, 3)); - - return src; -} - - -static GLuint -get_result_vector(struct i915_fragment_program *p, - const struct prog_instruction *inst) -{ - switch (inst->DstReg.File) { - case PROGRAM_OUTPUT: - switch (inst->DstReg.Index) { - case FRAG_RESULT_COLR: - return UREG(REG_TYPE_OC, 0); - case FRAG_RESULT_DEPR: - return UREG(REG_TYPE_OD, 0); - default: - i915_program_error(p, "Bad inst->DstReg.Index"); - return 0; - } - case PROGRAM_TEMPORARY: - return UREG(REG_TYPE_R, inst->DstReg.Index); - default: - i915_program_error(p, "Bad inst->DstReg.File"); - return 0; - } -} - -static GLuint -get_result_flags(const struct prog_instruction *inst) -{ - GLuint flags = 0; - - if (inst->SaturateMode == SATURATE_ZERO_ONE) - flags |= A0_DEST_SATURATE; - if (inst->DstReg.WriteMask & WRITEMASK_X) - flags |= A0_DEST_CHANNEL_X; - if (inst->DstReg.WriteMask & WRITEMASK_Y) - flags |= A0_DEST_CHANNEL_Y; - if (inst->DstReg.WriteMask & WRITEMASK_Z) - flags |= A0_DEST_CHANNEL_Z; - if (inst->DstReg.WriteMask & WRITEMASK_W) - flags |= A0_DEST_CHANNEL_W; - - return flags; -} - -static GLuint -translate_tex_src_target(struct i915_fragment_program *p, GLubyte bit) -{ - switch (bit) { - case TEXTURE_1D_INDEX: - return D0_SAMPLE_TYPE_2D; - case TEXTURE_2D_INDEX: - return D0_SAMPLE_TYPE_2D; - case TEXTURE_RECT_INDEX: - return D0_SAMPLE_TYPE_2D; - case TEXTURE_3D_INDEX: - return D0_SAMPLE_TYPE_VOLUME; - case TEXTURE_CUBE_INDEX: - return D0_SAMPLE_TYPE_CUBE; - default: - i915_program_error(p, "TexSrcBit"); - return 0; - } -} - -#define EMIT_TEX( OP ) \ -do { \ - GLuint dim = translate_tex_src_target( p, inst->TexSrcTarget ); \ - GLuint sampler = i915_emit_decl(p, REG_TYPE_S, \ - inst->TexSrcUnit, dim); \ - GLuint coord = src_vector( p, &inst->SrcReg[0], program); \ - /* Texel lookup */ \ - \ - i915_emit_texld( p, \ - get_result_vector( p, inst ), \ - get_result_flags( inst ), \ - sampler, \ - coord, \ - OP); \ -} while (0) - -#define EMIT_ARITH( OP, N ) \ -do { \ - i915_emit_arith( p, \ - OP, \ - get_result_vector( p, inst ), \ - get_result_flags( inst ), 0, \ - (N<1)?0:src_vector( p, &inst->SrcReg[0], program), \ - (N<2)?0:src_vector( p, &inst->SrcReg[1], program), \ - (N<3)?0:src_vector( p, &inst->SrcReg[2], program)); \ -} while (0) - -#define EMIT_1ARG_ARITH( OP ) EMIT_ARITH( OP, 1 ) -#define EMIT_2ARG_ARITH( OP ) EMIT_ARITH( OP, 2 ) -#define EMIT_3ARG_ARITH( OP ) EMIT_ARITH( OP, 3 ) - - -/* Possible concerns: - * - * SIN, COS -- could use another taylor step? - * LIT -- results seem a little different to sw mesa - * LOG -- different to mesa on negative numbers, but this is conformant. - * - * Parse failures -- Mesa doesn't currently give a good indication - * internally whether a particular program string parsed or not. This - * can lead to confusion -- hopefully we cope with it ok now. - * - */ -static void -upload_program(struct i915_fragment_program *p) -{ - const struct gl_fragment_program *program = - p->ctx->FragmentProgram._Current; - const struct prog_instruction *inst = program->Base.Instructions; - -/* _mesa_debug_fp_inst(program->Base.NumInstructions, inst); */ - - /* Is this a parse-failed program? Ensure a valid program is - * loaded, as the flagging of an error isn't sufficient to stop - * this being uploaded to hardware. - */ - if (inst[0].Opcode == OPCODE_END) { - GLuint tmp = i915_get_utemp(p); - i915_emit_arith(p, - A0_MOV, - UREG(REG_TYPE_OC, 0), - A0_DEST_CHANNEL_ALL, 0, - swizzle(tmp, ONE, ZERO, ONE, ONE), 0, 0); - return; - } - - while (1) { - GLuint src0, src1, src2, flags; - GLuint tmp = 0; - - switch (inst->Opcode) { - case OPCODE_ABS: - src0 = src_vector(p, &inst->SrcReg[0], program); - i915_emit_arith(p, - A0_MAX, - get_result_vector(p, inst), - get_result_flags(inst), 0, - src0, negate(src0, 1, 1, 1, 1), 0); - break; - - case OPCODE_ADD: - EMIT_2ARG_ARITH(A0_ADD); - break; - - case OPCODE_CMP: - src0 = src_vector(p, &inst->SrcReg[0], program); - src1 = src_vector(p, &inst->SrcReg[1], program); - src2 = src_vector(p, &inst->SrcReg[2], program); - i915_emit_arith(p, A0_CMP, get_result_vector(p, inst), get_result_flags(inst), 0, src0, src2, src1); /* NOTE: order of src2, src1 */ - break; - - case OPCODE_COS: - src0 = src_vector(p, &inst->SrcReg[0], program); - tmp = i915_get_utemp(p); - - i915_emit_arith(p, - A0_MUL, - tmp, A0_DEST_CHANNEL_X, 0, - src0, i915_emit_const1f(p, 1.0 / (M_PI * 2)), 0); - - i915_emit_arith(p, A0_MOD, tmp, A0_DEST_CHANNEL_X, 0, tmp, 0, 0); - - /* By choosing different taylor constants, could get rid of this mul: - */ - i915_emit_arith(p, - A0_MUL, - tmp, A0_DEST_CHANNEL_X, 0, - tmp, i915_emit_const1f(p, (M_PI * 2)), 0); - - /* - * t0.xy = MUL x.xx11, x.x1111 ; x^2, x, 1, 1 - * t0 = MUL t0.xyxy t0.xx11 ; x^4, x^3, x^2, 1 - * t0 = MUL t0.xxz1 t0.z111 ; x^6 x^4 x^2 1 - * result = DP4 t0, cos_constants - */ - i915_emit_arith(p, - A0_MUL, - tmp, A0_DEST_CHANNEL_XY, 0, - swizzle(tmp, X, X, ONE, ONE), - swizzle(tmp, X, ONE, ONE, ONE), 0); - - i915_emit_arith(p, - A0_MUL, - tmp, A0_DEST_CHANNEL_XYZ, 0, - swizzle(tmp, X, Y, X, ONE), - swizzle(tmp, X, X, ONE, ONE), 0); - - i915_emit_arith(p, - A0_MUL, - tmp, A0_DEST_CHANNEL_XYZ, 0, - swizzle(tmp, X, X, Z, ONE), - swizzle(tmp, Z, ONE, ONE, ONE), 0); - - i915_emit_arith(p, - A0_DP4, - get_result_vector(p, inst), - get_result_flags(inst), 0, - swizzle(tmp, ONE, Z, Y, X), - i915_emit_const4fv(p, cos_constants), 0); - - break; - - case OPCODE_DP3: - EMIT_2ARG_ARITH(A0_DP3); - break; - - case OPCODE_DP4: - EMIT_2ARG_ARITH(A0_DP4); - break; - - case OPCODE_DPH: - src0 = src_vector(p, &inst->SrcReg[0], program); - src1 = src_vector(p, &inst->SrcReg[1], program); - - i915_emit_arith(p, - A0_DP4, - get_result_vector(p, inst), - get_result_flags(inst), 0, - swizzle(src0, X, Y, Z, ONE), src1, 0); - break; - - case OPCODE_DST: - src0 = src_vector(p, &inst->SrcReg[0], program); - src1 = src_vector(p, &inst->SrcReg[1], program); - - /* result[0] = 1 * 1; - * result[1] = a[1] * b[1]; - * result[2] = a[2] * 1; - * result[3] = 1 * b[3]; - */ - i915_emit_arith(p, - A0_MUL, - get_result_vector(p, inst), - get_result_flags(inst), 0, - swizzle(src0, ONE, Y, Z, ONE), - swizzle(src1, ONE, Y, ONE, W), 0); - break; - - case OPCODE_EX2: - src0 = src_vector(p, &inst->SrcReg[0], program); - - i915_emit_arith(p, - A0_EXP, - get_result_vector(p, inst), - get_result_flags(inst), 0, - swizzle(src0, X, X, X, X), 0, 0); - break; - - case OPCODE_FLR: - EMIT_1ARG_ARITH(A0_FLR); - break; - - case OPCODE_FRC: - EMIT_1ARG_ARITH(A0_FRC); - break; - - case OPCODE_KIL: - src0 = src_vector(p, &inst->SrcReg[0], program); - tmp = i915_get_utemp(p); - - i915_emit_texld(p, tmp, A0_DEST_CHANNEL_ALL, /* use a dummy dest reg */ - 0, src0, T0_TEXKILL); - break; - - case OPCODE_LG2: - src0 = src_vector(p, &inst->SrcReg[0], program); - - i915_emit_arith(p, - A0_LOG, - get_result_vector(p, inst), - get_result_flags(inst), 0, - swizzle(src0, X, X, X, X), 0, 0); - break; - - case OPCODE_LIT: - src0 = src_vector(p, &inst->SrcReg[0], program); - tmp = i915_get_utemp(p); - - /* tmp = max( a.xyzw, a.00zw ) - * XXX: Clamp tmp.w to -128..128 - * tmp.y = log(tmp.y) - * tmp.y = tmp.w * tmp.y - * tmp.y = exp(tmp.y) - * result = cmp (a.11-x1, a.1x01, a.1xy1 ) - */ - i915_emit_arith(p, A0_MAX, tmp, A0_DEST_CHANNEL_ALL, 0, - src0, swizzle(src0, ZERO, ZERO, Z, W), 0); - - i915_emit_arith(p, A0_LOG, tmp, A0_DEST_CHANNEL_Y, 0, - swizzle(tmp, Y, Y, Y, Y), 0, 0); - - i915_emit_arith(p, A0_MUL, tmp, A0_DEST_CHANNEL_Y, 0, - swizzle(tmp, ZERO, Y, ZERO, ZERO), - swizzle(tmp, ZERO, W, ZERO, ZERO), 0); - - i915_emit_arith(p, A0_EXP, tmp, A0_DEST_CHANNEL_Y, 0, - swizzle(tmp, Y, Y, Y, Y), 0, 0); - - i915_emit_arith(p, A0_CMP, - get_result_vector(p, inst), - get_result_flags(inst), 0, - negate(swizzle(tmp, ONE, ONE, X, ONE), 0, 0, 1, 0), - swizzle(tmp, ONE, X, ZERO, ONE), - swizzle(tmp, ONE, X, Y, ONE)); - - break; - - case OPCODE_LRP: - src0 = src_vector(p, &inst->SrcReg[0], program); - src1 = src_vector(p, &inst->SrcReg[1], program); - src2 = src_vector(p, &inst->SrcReg[2], program); - flags = get_result_flags(inst); - tmp = i915_get_utemp(p); - - /* b*a + c*(1-a) - * - * b*a + c - ca - * - * tmp = b*a + c, - * result = (-c)*a + tmp - */ - i915_emit_arith(p, A0_MAD, tmp, - flags & A0_DEST_CHANNEL_ALL, 0, src1, src0, src2); - - i915_emit_arith(p, A0_MAD, - get_result_vector(p, inst), - flags, 0, negate(src2, 1, 1, 1, 1), src0, tmp); - break; - - case OPCODE_MAD: - EMIT_3ARG_ARITH(A0_MAD); - break; - - case OPCODE_MAX: - EMIT_2ARG_ARITH(A0_MAX); - break; - - case OPCODE_MIN: - src0 = src_vector(p, &inst->SrcReg[0], program); - src1 = src_vector(p, &inst->SrcReg[1], program); - tmp = i915_get_utemp(p); - flags = get_result_flags(inst); - - i915_emit_arith(p, - A0_MAX, - tmp, flags & A0_DEST_CHANNEL_ALL, 0, - negate(src0, 1, 1, 1, 1), - negate(src1, 1, 1, 1, 1), 0); - - i915_emit_arith(p, - A0_MOV, - get_result_vector(p, inst), - flags, 0, negate(tmp, 1, 1, 1, 1), 0, 0); - break; - - case OPCODE_MOV: - EMIT_1ARG_ARITH(A0_MOV); - break; - - case OPCODE_MUL: - EMIT_2ARG_ARITH(A0_MUL); - break; - - case OPCODE_POW: - src0 = src_vector(p, &inst->SrcReg[0], program); - src1 = src_vector(p, &inst->SrcReg[1], program); - tmp = i915_get_utemp(p); - flags = get_result_flags(inst); - - /* XXX: masking on intermediate values, here and elsewhere. - */ - i915_emit_arith(p, - A0_LOG, - tmp, A0_DEST_CHANNEL_X, 0, - swizzle(src0, X, X, X, X), 0, 0); - - i915_emit_arith(p, A0_MUL, tmp, A0_DEST_CHANNEL_X, 0, tmp, src1, 0); - - - i915_emit_arith(p, - A0_EXP, - get_result_vector(p, inst), - flags, 0, swizzle(tmp, X, X, X, X), 0, 0); - - break; - - case OPCODE_RCP: - src0 = src_vector(p, &inst->SrcReg[0], program); - - i915_emit_arith(p, - A0_RCP, - get_result_vector(p, inst), - get_result_flags(inst), 0, - swizzle(src0, X, X, X, X), 0, 0); - break; - - case OPCODE_RSQ: - - src0 = src_vector(p, &inst->SrcReg[0], program); - - i915_emit_arith(p, - A0_RSQ, - get_result_vector(p, inst), - get_result_flags(inst), 0, - swizzle(src0, X, X, X, X), 0, 0); - break; - - case OPCODE_SCS: - src0 = src_vector(p, &inst->SrcReg[0], program); - tmp = i915_get_utemp(p); - - /* - * t0.xy = MUL x.xx11, x.x1111 ; x^2, x, 1, 1 - * t0 = MUL t0.xyxy t0.xx11 ; x^4, x^3, x^2, x - * t1 = MUL t0.xyyw t0.yz11 ; x^7 x^5 x^3 x - * scs.x = DP4 t1, sin_constants - * t1 = MUL t0.xxz1 t0.z111 ; x^6 x^4 x^2 1 - * scs.y = DP4 t1, cos_constants - */ - i915_emit_arith(p, - A0_MUL, - tmp, A0_DEST_CHANNEL_XY, 0, - swizzle(src0, X, X, ONE, ONE), - swizzle(src0, X, ONE, ONE, ONE), 0); - - i915_emit_arith(p, - A0_MUL, - tmp, A0_DEST_CHANNEL_ALL, 0, - swizzle(tmp, X, Y, X, Y), - swizzle(tmp, X, X, ONE, ONE), 0); - - if (inst->DstReg.WriteMask & WRITEMASK_Y) { - GLuint tmp1; - - if (inst->DstReg.WriteMask & WRITEMASK_X) - tmp1 = i915_get_utemp(p); - else - tmp1 = tmp; - - i915_emit_arith(p, - A0_MUL, - tmp1, A0_DEST_CHANNEL_ALL, 0, - swizzle(tmp, X, Y, Y, W), - swizzle(tmp, X, Z, ONE, ONE), 0); - - i915_emit_arith(p, - A0_DP4, - get_result_vector(p, inst), - A0_DEST_CHANNEL_Y, 0, - swizzle(tmp1, W, Z, Y, X), - i915_emit_const4fv(p, sin_constants), 0); - } - - if (inst->DstReg.WriteMask & WRITEMASK_X) { - i915_emit_arith(p, - A0_MUL, - tmp, A0_DEST_CHANNEL_XYZ, 0, - swizzle(tmp, X, X, Z, ONE), - swizzle(tmp, Z, ONE, ONE, ONE), 0); - - i915_emit_arith(p, - A0_DP4, - get_result_vector(p, inst), - A0_DEST_CHANNEL_X, 0, - swizzle(tmp, ONE, Z, Y, X), - i915_emit_const4fv(p, cos_constants), 0); - } - break; - - case OPCODE_SGE: - EMIT_2ARG_ARITH(A0_SGE); - break; - - case OPCODE_SIN: - src0 = src_vector(p, &inst->SrcReg[0], program); - tmp = i915_get_utemp(p); - - i915_emit_arith(p, - A0_MUL, - tmp, A0_DEST_CHANNEL_X, 0, - src0, i915_emit_const1f(p, 1.0 / (M_PI * 2)), 0); - - i915_emit_arith(p, A0_MOD, tmp, A0_DEST_CHANNEL_X, 0, tmp, 0, 0); - - /* By choosing different taylor constants, could get rid of this mul: - */ - i915_emit_arith(p, - A0_MUL, - tmp, A0_DEST_CHANNEL_X, 0, - tmp, i915_emit_const1f(p, (M_PI * 2)), 0); - - /* - * t0.xy = MUL x.xx11, x.x1111 ; x^2, x, 1, 1 - * t0 = MUL t0.xyxy t0.xx11 ; x^4, x^3, x^2, x - * t1 = MUL t0.xyyw t0.yz11 ; x^7 x^5 x^3 x - * result = DP4 t1.wzyx, sin_constants - */ - i915_emit_arith(p, - A0_MUL, - tmp, A0_DEST_CHANNEL_XY, 0, - swizzle(tmp, X, X, ONE, ONE), - swizzle(tmp, X, ONE, ONE, ONE), 0); - - i915_emit_arith(p, - A0_MUL, - tmp, A0_DEST_CHANNEL_ALL, 0, - swizzle(tmp, X, Y, X, Y), - swizzle(tmp, X, X, ONE, ONE), 0); - - i915_emit_arith(p, - A0_MUL, - tmp, A0_DEST_CHANNEL_ALL, 0, - swizzle(tmp, X, Y, Y, W), - swizzle(tmp, X, Z, ONE, ONE), 0); - - i915_emit_arith(p, - A0_DP4, - get_result_vector(p, inst), - get_result_flags(inst), 0, - swizzle(tmp, W, Z, Y, X), - i915_emit_const4fv(p, sin_constants), 0); - break; - - case OPCODE_SLT: - EMIT_2ARG_ARITH(A0_SLT); - break; - - case OPCODE_SUB: - src0 = src_vector(p, &inst->SrcReg[0], program); - src1 = src_vector(p, &inst->SrcReg[1], program); - - i915_emit_arith(p, - A0_ADD, - get_result_vector(p, inst), - get_result_flags(inst), 0, - src0, negate(src1, 1, 1, 1, 1), 0); - break; - - case OPCODE_SWZ: - EMIT_1ARG_ARITH(A0_MOV); /* extended swizzle handled natively */ - break; - - case OPCODE_TEX: - EMIT_TEX(T0_TEXLD); - break; - - case OPCODE_TXB: - EMIT_TEX(T0_TEXLDB); - break; - - case OPCODE_TXP: - EMIT_TEX(T0_TEXLDP); - break; - - case OPCODE_XPD: - /* Cross product: - * result.x = src0.y * src1.z - src0.z * src1.y; - * result.y = src0.z * src1.x - src0.x * src1.z; - * result.z = src0.x * src1.y - src0.y * src1.x; - * result.w = undef; - */ - src0 = src_vector(p, &inst->SrcReg[0], program); - src1 = src_vector(p, &inst->SrcReg[1], program); - tmp = i915_get_utemp(p); - - i915_emit_arith(p, - A0_MUL, - tmp, A0_DEST_CHANNEL_ALL, 0, - swizzle(src0, Z, X, Y, ONE), - swizzle(src1, Y, Z, X, ONE), 0); - - i915_emit_arith(p, - A0_MAD, - get_result_vector(p, inst), - get_result_flags(inst), 0, - swizzle(src0, Y, Z, X, ONE), - swizzle(src1, Z, X, Y, ONE), - negate(tmp, 1, 1, 1, 0)); - break; - - case OPCODE_END: - return; - - default: - i915_program_error(p, "bad opcode"); - return; - } - - inst++; - i915_release_utemps(p); - } -} - -/* Rather than trying to intercept and jiggle depth writes during - * emit, just move the value into its correct position at the end of - * the program: - */ -static void -fixup_depth_write(struct i915_fragment_program *p) -{ - if (p->fp->Base.OutputsWritten & (1<<FRAG_RESULT_DEPR)) { - GLuint depth = UREG(REG_TYPE_OD, 0); - - i915_emit_arith(p, - A0_MOV, - depth, A0_DEST_CHANNEL_W, 0, - swizzle(depth, X, Y, Z, Z), 0, 0); - } -} - - -#define FRAG_BIT_TEX(n) (FRAG_BIT_TEX0 << (n)) - - - - -void -i915EmitFragmentProgram(struct i915_context *i915) -{ - GLcontext *ctx = &i915->intel.ctx; - struct intel_context *intel = intel_context(ctx); - struct i915_fragment_program *p = - (struct i915_fragment_program *) ctx->FragmentProgram._Current; - - if (!p->translated) { - i915_init_program(i915, p); - check_wpos(p); - upload_program(p); - fixup_depth_write(p); - i915_fini_program(p); - - p->translated = 1; - } -} - diff --git a/src/mesa/drivers/dri/i915tex/i915_metaops.c b/src/mesa/drivers/dri/i915tex/i915_metaops.c deleted file mode 100644 index 3ab62bc806..0000000000 --- a/src/mesa/drivers/dri/i915tex/i915_metaops.c +++ /dev/null @@ -1,509 +0,0 @@ -/************************************************************************** - * - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - **************************************************************************/ - -#include "glheader.h" -#include "enums.h" -#include "mtypes.h" -#include "macros.h" -#include "utils.h" - -#include "intel_screen.h" -#include "intel_batchbuffer.h" -#include "intel_ioctl.h" -#include "intel_regions.h" -#include "intel_rotate.h" - -#include "i915_context.h" -#include "i915_reg.h" - -/* We touch almost everything: - */ -#define ACTIVE (I915_UPLOAD_INVARIENT | \ - I915_UPLOAD_CTX | \ - I915_UPLOAD_BUFFERS | \ - I915_UPLOAD_STIPPLE | \ - I915_UPLOAD_PROGRAM | \ - I915_UPLOAD_FOG | \ - I915_UPLOAD_TEX(0)) - -#define SET_STATE( i915, STATE ) \ -do { \ - i915->current->emitted &= ~ACTIVE; \ - i915->current = &i915->STATE; \ - i915->current->emitted &= ~ACTIVE; \ -} while (0) - - -static void -meta_no_stencil_write(struct intel_context *intel) -{ - struct i915_context *i915 = i915_context(&intel->ctx); - - /* ctx->Driver.Enable( ctx, GL_STENCIL_TEST, GL_FALSE ) - */ - i915->meta.Ctx[I915_CTXREG_LIS5] &= ~(S5_STENCIL_TEST_ENABLE | - S5_STENCIL_WRITE_ENABLE); - - i915->meta.emitted &= ~I915_UPLOAD_CTX; -} - -static void -meta_no_depth_write(struct intel_context *intel) -{ - struct i915_context *i915 = i915_context(&intel->ctx); - - /* ctx->Driver.Enable( ctx, GL_DEPTH_TEST, GL_FALSE ) - */ - i915->meta.Ctx[I915_CTXREG_LIS6] &= ~(S6_DEPTH_TEST_ENABLE | - S6_DEPTH_WRITE_ENABLE); - - i915->meta.emitted &= ~I915_UPLOAD_CTX; -} - -static void -meta_depth_replace(struct intel_context *intel) -{ - struct i915_context *i915 = i915_context(&intel->ctx); - - /* ctx->Driver.Enable( ctx, GL_DEPTH_TEST, GL_TRUE ) - * ctx->Driver.DepthMask( ctx, GL_TRUE ) - */ - i915->meta.Ctx[I915_CTXREG_LIS6] |= (S6_DEPTH_TEST_ENABLE | - S6_DEPTH_WRITE_ENABLE); - - /* ctx->Driver.DepthFunc( ctx, GL_REPLACE ) - */ - i915->meta.Ctx[I915_CTXREG_LIS6] &= ~S6_DEPTH_TEST_FUNC_MASK; - i915->meta.Ctx[I915_CTXREG_LIS6] |= - COMPAREFUNC_ALWAYS << S6_DEPTH_TEST_FUNC_SHIFT; - - i915->meta.emitted &= ~I915_UPLOAD_CTX; -} - - -/* Set stencil unit to replace always with the reference value. - */ -static void -meta_stencil_replace(struct intel_context *intel, - GLuint s_mask, GLuint s_clear) -{ - struct i915_context *i915 = i915_context(&intel->ctx); - GLuint op = STENCILOP_REPLACE; - GLuint func = COMPAREFUNC_ALWAYS; - - /* ctx->Driver.Enable( ctx, GL_STENCIL_TEST, GL_TRUE ) - */ - i915->meta.Ctx[I915_CTXREG_LIS5] |= (S5_STENCIL_TEST_ENABLE | - S5_STENCIL_WRITE_ENABLE); - - /* ctx->Driver.StencilMask( ctx, s_mask ) - */ - i915->meta.Ctx[I915_CTXREG_STATE4] &= ~MODE4_ENABLE_STENCIL_WRITE_MASK; - - i915->meta.Ctx[I915_CTXREG_STATE4] |= (ENABLE_STENCIL_WRITE_MASK | - STENCIL_WRITE_MASK(s_mask)); - - /* ctx->Driver.StencilOp( ctx, GL_REPLACE, GL_REPLACE, GL_REPLACE ) - */ - i915->meta.Ctx[I915_CTXREG_LIS5] &= ~(S5_STENCIL_FAIL_MASK | - S5_STENCIL_PASS_Z_FAIL_MASK | - S5_STENCIL_PASS_Z_PASS_MASK); - - i915->meta.Ctx[I915_CTXREG_LIS5] |= ((op << S5_STENCIL_FAIL_SHIFT) | - (op << S5_STENCIL_PASS_Z_FAIL_SHIFT) | - (op << S5_STENCIL_PASS_Z_PASS_SHIFT)); - - - /* ctx->Driver.StencilFunc( ctx, GL_ALWAYS, s_ref, ~0 ) - */ - i915->meta.Ctx[I915_CTXREG_STATE4] &= ~MODE4_ENABLE_STENCIL_TEST_MASK; - i915->meta.Ctx[I915_CTXREG_STATE4] |= (ENABLE_STENCIL_TEST_MASK | - STENCIL_TEST_MASK(0xff)); - - i915->meta.Ctx[I915_CTXREG_LIS5] &= ~(S5_STENCIL_REF_MASK | - S5_STENCIL_TEST_FUNC_MASK); - - i915->meta.Ctx[I915_CTXREG_LIS5] |= ((s_clear << S5_STENCIL_REF_SHIFT) | - (func << S5_STENCIL_TEST_FUNC_SHIFT)); - - - i915->meta.emitted &= ~I915_UPLOAD_CTX; -} - - -static void -meta_color_mask(struct intel_context *intel, GLboolean state) -{ - struct i915_context *i915 = i915_context(&intel->ctx); - const GLuint mask = (S5_WRITEDISABLE_RED | - S5_WRITEDISABLE_GREEN | - S5_WRITEDISABLE_BLUE | S5_WRITEDISABLE_ALPHA); - - /* Copy colormask state from "regular" hw context. - */ - if (state) { - i915->meta.Ctx[I915_CTXREG_LIS5] &= ~mask; - i915->meta.Ctx[I915_CTXREG_LIS5] |= - (i915->state.Ctx[I915_CTXREG_LIS5] & mask); - } - else - i915->meta.Ctx[I915_CTXREG_LIS5] |= mask; - - i915->meta.emitted &= ~I915_UPLOAD_CTX; -} - - - -static void -meta_import_pixel_state(struct intel_context *intel) -{ - struct i915_context *i915 = i915_context(&intel->ctx); - memcpy(i915->meta.Fog, i915->state.Fog, I915_FOG_SETUP_SIZE * 4); - - i915->meta.Ctx[I915_CTXREG_LIS5] = i915->state.Ctx[I915_CTXREG_LIS5]; - i915->meta.Ctx[I915_CTXREG_LIS6] = i915->state.Ctx[I915_CTXREG_LIS6]; - i915->meta.Ctx[I915_CTXREG_STATE4] = i915->state.Ctx[I915_CTXREG_STATE4]; - i915->meta.Ctx[I915_CTXREG_BLENDCOLOR1] = - i915->state.Ctx[I915_CTXREG_BLENDCOLOR1]; - i915->meta.Ctx[I915_CTXREG_IAB] = i915->state.Ctx[I915_CTXREG_IAB]; - - i915->meta.Buffer[I915_DESTREG_SENABLE] = - i915->state.Buffer[I915_DESTREG_SENABLE]; - i915->meta.Buffer[I915_DESTREG_SR1] = i915->state.Buffer[I915_DESTREG_SR1]; - i915->meta.Buffer[I915_DESTREG_SR2] = i915->state.Buffer[I915_DESTREG_SR2]; - - i915->meta.emitted &= ~I915_UPLOAD_FOG; - i915->meta.emitted &= ~I915_UPLOAD_BUFFERS; - i915->meta.emitted &= ~I915_UPLOAD_CTX; -} - - - - -#define REG( type, nr ) (((type)<<5)|(nr)) - -#define REG_R(x) REG(REG_TYPE_R, x) -#define REG_T(x) REG(REG_TYPE_T, x) -#define REG_CONST(x) REG(REG_TYPE_CONST, x) -#define REG_S(x) REG(REG_TYPE_S, x) -#define REG_OC REG(REG_TYPE_OC, 0) -#define REG_OD REG(REG_TYPE_OD, 0) -#define REG_U(x) REG(REG_TYPE_U, x) - -#define REG_T_DIFFUSE REG(REG_TYPE_T, T_DIFFUSE) -#define REG_T_SPECULAR REG(REG_TYPE_T, T_SPECULAR) -#define REG_T_FOG_W REG(REG_TYPE_T, T_FOG_W) -#define REG_T_TEX(x) REG(REG_TYPE_T, x) - - -#define A0_DEST_REG( reg ) ( (reg) << A0_DEST_NR_SHIFT ) -#define A0_SRC0_REG( reg ) ( (reg) << A0_SRC0_NR_SHIFT ) -#define A1_SRC1_REG( reg ) ( (reg) << A1_SRC1_NR_SHIFT ) -#define A1_SRC2_REG( reg ) ( (reg) << A1_SRC2_NR_SHIFT ) -#define A2_SRC2_REG( reg ) ( (reg) << A2_SRC2_NR_SHIFT ) -#define D0_DECL_REG( reg ) ( (reg) << D0_NR_SHIFT ) -#define T0_DEST_REG( reg ) ( (reg) << T0_DEST_NR_SHIFT ) - -#define T0_SAMPLER( unit ) ((unit)<<T0_SAMPLER_NR_SHIFT) - -#define T1_ADDRESS_REG( type, nr ) (((type)<<T1_ADDRESS_REG_TYPE_SHIFT)| \ - ((nr)<<T1_ADDRESS_REG_NR_SHIFT)) - - -#define A1_SRC0_XYZW ((SRC_X << A1_SRC0_CHANNEL_X_SHIFT) | \ - (SRC_Y << A1_SRC0_CHANNEL_Y_SHIFT) | \ - (SRC_Z << A1_SRC0_CHANNEL_Z_SHIFT) | \ - (SRC_W << A1_SRC0_CHANNEL_W_SHIFT)) - -#define A1_SRC1_XY ((SRC_X << A1_SRC1_CHANNEL_X_SHIFT) | \ - (SRC_Y << A1_SRC1_CHANNEL_Y_SHIFT)) - -#define A2_SRC1_ZW ((SRC_Z << A2_SRC1_CHANNEL_Z_SHIFT) | \ - (SRC_W << A2_SRC1_CHANNEL_W_SHIFT)) - -#define A2_SRC2_XYZW ((SRC_X << A2_SRC2_CHANNEL_X_SHIFT) | \ - (SRC_Y << A2_SRC2_CHANNEL_Y_SHIFT) | \ - (SRC_Z << A2_SRC2_CHANNEL_Z_SHIFT) | \ - (SRC_W << A2_SRC2_CHANNEL_W_SHIFT)) - - - - - -static void -meta_no_texture(struct intel_context *intel) -{ - struct i915_context *i915 = i915_context(&intel->ctx); - - static const GLuint prog[] = { - _3DSTATE_PIXEL_SHADER_PROGRAM, - - /* Declare incoming diffuse color: - */ - (D0_DCL | D0_DECL_REG(REG_T_DIFFUSE) | D0_CHANNEL_ALL), - D1_MBZ, - D2_MBZ, - - /* output-color = mov(t_diffuse) - */ - (A0_MOV | - A0_DEST_REG(REG_OC) | - A0_DEST_CHANNEL_ALL | A0_SRC0_REG(REG_T_DIFFUSE)), - (A1_SRC0_XYZW), - 0, - }; - - - memcpy(i915->meta.Program, prog, sizeof(prog)); - i915->meta.ProgramSize = sizeof(prog) / sizeof(*prog); - i915->meta.Program[0] |= i915->meta.ProgramSize - 2; - i915->meta.emitted &= ~I915_UPLOAD_PROGRAM; -} - -static void -meta_texture_blend_replace(struct intel_context *intel) -{ - struct i915_context *i915 = i915_context(&intel->ctx); - - static const GLuint prog[] = { - _3DSTATE_PIXEL_SHADER_PROGRAM, - - /* Declare the sampler: - */ - (D0_DCL | D0_DECL_REG(REG_S(0)) | D0_SAMPLE_TYPE_2D | D0_CHANNEL_NONE), - D1_MBZ, - D2_MBZ, - - /* Declare the interpolated texture coordinate: - */ - (D0_DCL | D0_DECL_REG(REG_T_TEX(0)) | D0_CHANNEL_ALL), - D1_MBZ, - D2_MBZ, - - /* output-color = texld(sample0, texcoord0) - */ - (T0_TEXLD | T0_DEST_REG(REG_OC) | T0_SAMPLER(0)), - T1_ADDRESS_REG(REG_TYPE_T, 0), - T2_MBZ - }; - - memcpy(i915->meta.Program, prog, sizeof(prog)); - i915->meta.ProgramSize = sizeof(prog) / sizeof(*prog); - i915->meta.Program[0] |= i915->meta.ProgramSize - 2; - i915->meta.emitted &= ~I915_UPLOAD_PROGRAM; -} - - - - - -/* Set up an arbitary piece of memory as a rectangular texture - * (including the front or back buffer). - */ -static GLboolean -meta_tex_rect_source(struct intel_context *intel, - struct _DriBufferObject *buffer, - GLuint offset, - GLuint pitch, GLuint height, GLenum format, GLenum type) -{ - struct i915_context *i915 = i915_context(&intel->ctx); - GLuint unit = 0; - GLint numLevels = 1; - GLuint *state = i915->meta.Tex[0]; - GLuint textureFormat; - GLuint cpp; - - /* A full implementation of this would do the upload through - * glTexImage2d, and get all the conversion operations at that - * point. We are restricted, but still at least have access to the - * fragment program swizzle. - */ - switch (format) { - case GL_BGRA: - switch (type) { - case GL_UNSIGNED_INT_8_8_8_8_REV: - case GL_UNSIGNED_BYTE: - textureFormat = (MAPSURF_32BIT | MT_32BIT_ARGB8888); - cpp = 4; - break; - default: - return GL_FALSE; - } - break; - case GL_RGBA: - switch (type) { - case GL_UNSIGNED_INT_8_8_8_8_REV: - case GL_UNSIGNED_BYTE: - textureFormat = (MAPSURF_32BIT | MT_32BIT_ABGR8888); - cpp = 4; - break; - default: - return GL_FALSE; - } - break; - case GL_BGR: - switch (type) { - case GL_UNSIGNED_SHORT_5_6_5_REV: - textureFormat = (MAPSURF_16BIT | MT_16BIT_RGB565); - cpp = 2; - break; - default: - return GL_FALSE; - } - break; - case GL_RGB: - switch (type) { - case GL_UNSIGNED_SHORT_5_6_5: - textureFormat = (MAPSURF_16BIT | MT_16BIT_RGB565); - cpp = 2; - break; - default: - return GL_FALSE; - } - break; - - default: - return GL_FALSE; - } - - - if ((pitch * cpp) & 3) { - _mesa_printf("%s: texture is not dword pitch\n", __FUNCTION__); - return GL_FALSE; - } - -/* intel_region_release(&i915->meta.tex_region[0]); */ -/* intel_region_reference(&i915->meta.tex_region[0], region); */ - i915->meta.tex_buffer[0] = buffer; - i915->meta.tex_offset[0] = offset; - - state[I915_TEXREG_MS3] = (((height - 1) << MS3_HEIGHT_SHIFT) | - ((pitch - 1) << MS3_WIDTH_SHIFT) | - textureFormat | MS3_USE_FENCE_REGS); - - state[I915_TEXREG_MS4] = (((((pitch * cpp) / 4) - 1) << MS4_PITCH_SHIFT) | - MS4_CUBE_FACE_ENA_MASK | - ((((numLevels - 1) * 4)) << MS4_MAX_LOD_SHIFT)); - - state[I915_TEXREG_SS2] = ((FILTER_NEAREST << SS2_MIN_FILTER_SHIFT) | - (MIPFILTER_NONE << SS2_MIP_FILTER_SHIFT) | - (FILTER_NEAREST << SS2_MAG_FILTER_SHIFT)); - - state[I915_TEXREG_SS3] = ((TEXCOORDMODE_WRAP << SS3_TCX_ADDR_MODE_SHIFT) | - (TEXCOORDMODE_WRAP << SS3_TCY_ADDR_MODE_SHIFT) | - (TEXCOORDMODE_WRAP << SS3_TCZ_ADDR_MODE_SHIFT) | - (unit << SS3_TEXTUREMAP_INDEX_SHIFT)); - - state[I915_TEXREG_SS4] = 0; - - i915->meta.emitted &= ~I915_UPLOAD_TEX(0); - return GL_TRUE; -} - - -/** - * Set the color and depth drawing region for meta ops. - */ -static void -meta_draw_region(struct intel_context *intel, - struct intel_region *color_region, - struct intel_region *depth_region) -{ - struct i915_context *i915 = i915_context(&intel->ctx); - i915_state_draw_region(intel, &i915->meta, color_region, depth_region); -} - - -static void -set_vertex_format(struct intel_context *intel) -{ - struct i915_context *i915 = i915_context(&intel->ctx); - - i915->meta.Ctx[I915_CTXREG_LIS2] = - (S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D) | - S2_TEXCOORD_FMT(1, TEXCOORDFMT_NOT_PRESENT) | - S2_TEXCOORD_FMT(2, TEXCOORDFMT_NOT_PRESENT) | - S2_TEXCOORD_FMT(3, TEXCOORDFMT_NOT_PRESENT) | - S2_TEXCOORD_FMT(4, TEXCOORDFMT_NOT_PRESENT) | - S2_TEXCOORD_FMT(5, TEXCOORDFMT_NOT_PRESENT) | - S2_TEXCOORD_FMT(6, TEXCOORDFMT_NOT_PRESENT) | - S2_TEXCOORD_FMT(7, TEXCOORDFMT_NOT_PRESENT)); - - i915->meta.Ctx[I915_CTXREG_LIS4] &= ~S4_VFMT_MASK; - - i915->meta.Ctx[I915_CTXREG_LIS4] |= (S4_VFMT_COLOR | S4_VFMT_XYZ); - - i915->meta.emitted &= ~I915_UPLOAD_CTX; -} - - - -/* Operations where the 3D engine is decoupled temporarily from the - * current GL state and used for other purposes than simply rendering - * incoming triangles. - */ -static void -install_meta_state(struct intel_context *intel) -{ - struct i915_context *i915 = i915_context(&intel->ctx); - memcpy(&i915->meta, &i915->initial, sizeof(i915->meta)); - i915->meta.active = ACTIVE; - i915->meta.emitted = 0; - - SET_STATE(i915, meta); - set_vertex_format(intel); - meta_no_texture(intel); -} - -static void -leave_meta_state(struct intel_context *intel) -{ - struct i915_context *i915 = i915_context(&intel->ctx); - intel_region_release(&i915->meta.draw_region); - intel_region_release(&i915->meta.depth_region); -/* intel_region_release(&i915->meta.tex_region[0]); */ - SET_STATE(i915, state); -} - - - -void -i915InitMetaFuncs(struct i915_context *i915) -{ - i915->intel.vtbl.install_meta_state = install_meta_state; - i915->intel.vtbl.leave_meta_state = leave_meta_state; - i915->intel.vtbl.meta_no_depth_write = meta_no_depth_write; - i915->intel.vtbl.meta_no_stencil_write = meta_no_stencil_write; - i915->intel.vtbl.meta_stencil_replace = meta_stencil_replace; - i915->intel.vtbl.meta_depth_replace = meta_depth_replace; - i915->intel.vtbl.meta_color_mask = meta_color_mask; - i915->intel.vtbl.meta_no_texture = meta_no_texture; - i915->intel.vtbl.meta_texture_blend_replace = meta_texture_blend_replace; - i915->intel.vtbl.meta_tex_rect_source = meta_tex_rect_source; - i915->intel.vtbl.meta_draw_region = meta_draw_region; - i915->intel.vtbl.meta_import_pixel_state = meta_import_pixel_state; -} diff --git a/src/mesa/drivers/dri/i915tex/i915_program.c b/src/mesa/drivers/dri/i915tex/i915_program.c index 1ae065b10d..fdfe39abea 100644 --- a/src/mesa/drivers/dri/i915tex/i915_program.c +++ b/src/mesa/drivers/dri/i915tex/i915_program.c @@ -1,85 +1,79 @@ -/* - Copyright (C) Intel Corp. 2006. All Rights Reserved. - Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to - develop this 3D driver. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice (including the - next paragraph) shall be included in all copies or substantial - portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - - **********************************************************************/ - /* - * Authors: - * Keith Whitwell <keith@tungstengraphics.com> - */ - - -#include "brw_context.h" -#include "brw_aub.h" -#include "brw_util.h" -#include "program.h" -#include "imports.h" +/************************************************************************** + * + * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ + +#include "glheader.h" +#include "macros.h" #include "enums.h" + #include "tnl/tnl.h" +#include "tnl/t_context.h" +#include "intel_batchbuffer.h" + +#include "i915_reg.h" +#include "i915_context.h" + +#include "program_instruction.h" +#include "program.h" +#include "programopt.h" -static void brwBindProgram( GLcontext *ctx, +static void i915BindProgram( GLcontext *ctx, GLenum target, struct gl_program *prog ) { - struct brw_context *brw = brw_context(ctx); + struct intel_context *intel = intel_context(ctx); switch (target) { case GL_VERTEX_PROGRAM_ARB: - brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM; +/* intel->state.dirty.intel |= INTEL_NEW_VERTEX_PROGRAM; */ break; case GL_FRAGMENT_PROGRAM_ARB: - brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM; + intel->state.dirty.intel |= INTEL_NEW_FRAGMENT_PROGRAM; break; } } -static struct gl_program *brwNewProgram( GLcontext *ctx, - GLenum target, - GLuint id ) +static struct gl_program *i915NewProgram( GLcontext *ctx, + GLenum target, + GLuint id ) { - struct brw_context *brw = brw_context(ctx); + struct i915_context *i915 = i915_context(ctx); switch (target) { - case GL_VERTEX_PROGRAM_ARB: { - struct brw_vertex_program *prog = CALLOC_STRUCT(brw_vertex_program); - if (prog) { - prog->id = brw->program_id++; - - return _mesa_init_vertex_program( ctx, &prog->program, - target, id ); - } - else - return NULL; - } + case GL_VERTEX_PROGRAM_ARB: + return _mesa_init_vertex_program(ctx, CALLOC_STRUCT(gl_vertex_program), + target, id); case GL_FRAGMENT_PROGRAM_ARB: { - struct brw_fragment_program *prog = CALLOC_STRUCT(brw_fragment_program); + struct i915_fragment_program *prog = CALLOC_STRUCT(i915_fragment_program); if (prog) { - prog->id = brw->program_id++; + prog->id = i915->program_id++; - return _mesa_init_fragment_program( ctx, &prog->program, + return _mesa_init_fragment_program( ctx, &prog->Base, target, id ); } else @@ -91,7 +85,7 @@ static struct gl_program *brwNewProgram( GLcontext *ctx, } } -static void brwDeleteProgram( GLcontext *ctx, +static void i915DeleteProgram( GLcontext *ctx, struct gl_program *prog ) { @@ -99,34 +93,27 @@ static void brwDeleteProgram( GLcontext *ctx, } -static GLboolean brwIsProgramNative( GLcontext *ctx, +static GLboolean i915IsProgramNative( GLcontext *ctx, GLenum target, struct gl_program *prog ) { return GL_TRUE; } -static void brwProgramStringNotify( GLcontext *ctx, +static void i915ProgramStringNotify( GLcontext *ctx, GLenum target, struct gl_program *prog ) { if (target == GL_FRAGMENT_PROGRAM_ARB) { - struct brw_context *brw = brw_context(ctx); - struct brw_fragment_program *p = (struct brw_fragment_program *)prog; - struct brw_fragment_program *fp = (struct brw_fragment_program *)brw->fragment_program; + struct i915_context *i915 = i915_context(ctx); + struct i915_fragment_program *p = (struct i915_fragment_program *)prog; + struct i915_fragment_program *fp = (struct i915_fragment_program *)i915->fragment_program; if (p == fp) - brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM; - p->id = brw->program_id++; - p->param_state = brw_parameter_list_state_flags(p->program.Base.Parameters); + i915->intel.state.dirty.intel |= INTEL_NEW_FRAGMENT_PROGRAM; + p->id = i915->program_id++; + p->param_state = p->Base.Base.Parameters->StateFlags; } else if (target == GL_VERTEX_PROGRAM_ARB) { - struct brw_context *brw = brw_context(ctx); - struct brw_vertex_program *p = (struct brw_vertex_program *)prog; - struct brw_vertex_program *vp = (struct brw_vertex_program *)brw->vertex_program; - if (p == vp) - brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM; - p->id = brw->program_id++; - p->param_state = brw_parameter_list_state_flags(p->program.Base.Parameters); /* Also tell tnl about it: */ @@ -134,14 +121,17 @@ static void brwProgramStringNotify( GLcontext *ctx, } } -void brwInitFragProgFuncs( struct dd_function_table *functions ) +void i915InitFragProgFuncs( struct dd_function_table *functions ) { assert(functions->ProgramStringNotify == _tnl_program_string); - functions->BindProgram = brwBindProgram; - functions->NewProgram = brwNewProgram; - functions->DeleteProgram = brwDeleteProgram; - functions->IsProgramNative = brwIsProgramNative; - functions->ProgramStringNotify = brwProgramStringNotify; + functions->BindProgram = i915BindProgram; + functions->NewProgram = i915NewProgram; + functions->DeleteProgram = i915DeleteProgram; + functions->IsProgramNative = i915IsProgramNative; + functions->ProgramStringNotify = i915ProgramStringNotify; } + + + diff --git a/src/mesa/drivers/dri/i915tex/i915_reg.h b/src/mesa/drivers/dri/i915tex/i915_reg.h index 04b199905c..02d2972db2 100644 --- a/src/mesa/drivers/dri/i915tex/i915_reg.h +++ b/src/mesa/drivers/dri/i915tex/i915_reg.h @@ -424,6 +424,16 @@ #define S7_DEPTH_OFFSET_CONST_MASK ~0 + + +#define DST_BLND_FACT(f) ((f)<<S6_CBUF_DST_BLEND_FACT_SHIFT) +#define SRC_BLND_FACT(f) ((f)<<S6_CBUF_SRC_BLEND_FACT_SHIFT) +#define DST_ABLND_FACT(f) ((f)<<IAB_DST_FACTOR_SHIFT) +#define SRC_ABLND_FACT(f) ((f)<<IAB_SRC_FACTOR_SHIFT) + + + + /* 3DSTATE_MAP_DEINTERLACER_PARAMETERS */ /* 3DSTATE_MAP_PALETTE_LOAD_32, p206 */ diff --git a/src/mesa/drivers/dri/i915tex/i915_state.c b/src/mesa/drivers/dri/i915tex/i915_state.c index 93e41245b3..4c02ec2858 100644 --- a/src/mesa/drivers/dri/i915tex/i915_state.c +++ b/src/mesa/drivers/dri/i915tex/i915_state.c @@ -77,32 +77,27 @@ * Keith Whitwell <keith@tungstengraphics.com> */ +#include "intel_context.h" +#include "i915_state.h" - -#include "brw_context.h" -#include "brw_state.h" -#include "bufmgr.h" -#include "intel_batchbuffer.h" - -/* This is used to initialize brw->state.atoms[]. We could use this - * list directly except for a single atom, brw_constant_buffer, which +/* This is used to initialize intel->state.atoms[]. We could use this + * list directly except for a single atom, i915_constants, which * has a .dirty value which changes according to the parameters of the * current fragment and vertex programs, and so cannot be a static * value. */ -const struct brw_tracked_state *atoms[] = +const struct intel_tracked_state *atoms[] = { &i915_check_fallback, - &i915_invarient_state, - + &i915_invarient_state, /* */ - &i915_fp_choose_prog_get_inputs, +/* &i915_fp_choose_prog, */ - /* Scan VB: + /* Scan VB: Or scan VP ?? */ - &i915_fp_input_sizes, +/* &i915_vb_output_sizes, */ /* Get compiled version of the fragment program which is mildly * optimized according to input sizes. This will be cached, but @@ -111,17 +106,17 @@ const struct brw_tracked_state *atoms[] = * Also calculate vertex layout, immediate (S2,S4) state, vertex * size. */ - &i915_fp_compile, - - /* Emit compiled version of the fragment program. + &i915_fp_compile_and_upload, + + /* Calculate vertex format, program t_vertex.c, etc: */ - &i915_upload_fp, + &i915_fp_inputs, + /* Immediate state. Don't make any effort to combine packets yet. */ &i915_upload_S0S1, - &i915_upload_S2, - &i915_upload_S4, + &i915_upload_S2S4, &i915_upload_S5, &i915_upload_S6, @@ -138,181 +133,46 @@ const struct brw_tracked_state *atoms[] = &i915_upload_BLENDCOLOR, &i915_upload_IAB, - &i915_upload_colorbuffer, - &i915_upload_depthbuffer, + &i915_upload_buffers, /* Note this packet has a dependency on the current primitive: */ - &i915_upload_polygon_stipple, + &i915_upload_stipple, &i915_upload_scissor, - NULL, /* i915_constant_buffer */ + NULL, /* i915_constants */ }; void i915_init_state( struct i915_context *i915 ) { + struct intel_context *intel = &i915->intel; GLuint i; - i915_init_pools(i915); - i915_init_caches(i915); - - i915->state.atoms = _mesa_malloc(sizeof(atoms)); - i915->state.nr_atoms = sizeof(atoms)/sizeof(*atoms); - _mesa_memcpy(i915->state.atoms, atoms, sizeof(atoms)); + intel->driver_state.atoms = _mesa_malloc(sizeof(atoms)); + intel->driver_state.nr_atoms = sizeof(atoms)/sizeof(*atoms); + _mesa_memcpy(intel->driver_state.atoms, atoms, sizeof(atoms)); /* Patch in a pointer to the dynamic state atom: */ - for (i = 0; i < i915->state.nr_atoms; i++) - if (i915->state.atoms[i] == NULL) - i915->state.atoms[i] = &i915->curbe.tracked_state; + for (i = 0; i < intel->driver_state.nr_atoms; i++) + if (intel->driver_state.atoms[i] == NULL) + intel->driver_state.atoms[i] = &i915->constants.tracked_state; - _mesa_memcpy(&i915->curbe.tracked_state, - &i915_constant_buffer, - sizeof(i915_constant_buffer)); + _mesa_memcpy(&i915->constants.tracked_state, + &i915_fp_upload_constants, + sizeof(i915_fp_upload_constants)); } void i915_destroy_state( struct i915_context *i915 ) { - if (i915->state.atoms) { - _mesa_free(i915->state.atoms); - i915->state.atoms = NULL; - } - - i915_destroy_caches(i915); - i915_destroy_batch_cache(i915); - i915_destroy_pools(i915); -} - -/*********************************************************************** - */ - -static GLboolean check_state( const struct i915_state_flags *a, - const struct i915_state_flags *b ) -{ - return ((a->mesa & b->mesa) || - (a->i915 & b->i915) || - (a->cache & b->cache)); -} - -static void accumulate_state( struct i915_state_flags *a, - const struct i915_state_flags *b ) -{ - a->mesa |= b->mesa; - a->i915 |= b->i915; - a->cache |= b->cache; -} - - -static void xor_states( struct i915_state_flags *result, - const struct i915_state_flags *a, - const struct i915_state_flags *b ) -{ - result->mesa = a->mesa ^ b->mesa; - result->i915 = a->i915 ^ b->i915; - result->cache = a->cache ^ b->cache; -} - - -/*********************************************************************** - * Emit all state: - */ -void i915_validate_state( struct i915_context *i915 ) -{ - struct i915_state_flags *state = &i915->state.dirty; - GLuint i; + struct intel_context *intel = &i915->intel; - state->mesa |= i915->intel.NewGLState; - i915->intel.NewGLState = 0; - - if (i915->wrap) - state->i915 |= I915_NEW_CONTEXT; - - if (i915->emit_state_always) { - state->mesa |= ~0; - state->i915 |= ~0; + if (intel->driver_state.atoms) { + _mesa_free(intel->driver_state.atoms); + intel->driver_state.atoms = NULL; } - - /* texenv program needs to notify us somehow when this happens: - * Some confusion about which state flag should represent this change. - */ - if (i915->fragment_program != i915->attribs.FragmentProgram->_Current) { - i915->fragment_program = i915->attribs.FragmentProgram->_Current; - i915->state.dirty.mesa |= _NEW_PROGRAM; - i915->state.dirty.i915 |= I915_NEW_FRAGMENT_PROGRAM; - } - - - if (state->mesa == 0 && - state->cache == 0 && - state->i915 == 0) - return; - - if (i915->state.dirty.i915 & I915_NEW_CONTEXT) - i915_clear_batch_cache_flush(i915); - - - - if (INTEL_DEBUG) { - /* Debug version which enforces various sanity checks on the - * state flags which are generated and checked to help ensure - * state atoms are ordered correctly in the list. - */ - struct i915_state_flags examined, prev; - _mesa_memset(&examined, 0, sizeof(examined)); - prev = *state; - - for (i = 0; i < i915->state.nr_atoms; i++) { - const struct i915_tracked_state *atom = i915->state.atoms[i]; - struct i915_state_flags generated; - - assert(atom->dirty.mesa || - atom->dirty.i915 || - atom->dirty.cache); - assert(atom->update); - - if (check_state(state, &atom->dirty)) { - i915->state.atoms[i]->update( i915 ); - -/* emit_foo(i915); */ - } - - accumulate_state(&examined, &atom->dirty); - - /* generated = (prev ^ state) - * if (examined & generated) - * fail; - */ - xor_states(&generated, &prev, state); - assert(!check_state(&examined, &generated)); - prev = *state; - } - } - else { - for (i = 0; i < Elements(atoms); i++) { - if (check_state(state, &i915->state.atoms[i]->dirty)) - i915->state.atoms[i]->update( i915 ); - } - } - - memset(state, 0, sizeof(*state)); } -/* - */ - - -void -i915InitState(struct i915_context *i915) -{ - GLcontext *ctx = &i915->intel.ctx; - - i915_init_packets(i915); - - intelInitState(ctx); - - memcpy(&i915->initial, &i915->state, sizeof(i915->state)); - i915->current = &i915->state; -} diff --git a/src/mesa/drivers/dri/i915tex/i915_state.h b/src/mesa/drivers/dri/i915tex/i915_state.h index 80e692f915..e4f26674a8 100644 --- a/src/mesa/drivers/dri/i915tex/i915_state.h +++ b/src/mesa/drivers/dri/i915tex/i915_state.h @@ -1,25 +1,62 @@ -#define DST_BLND_FACT(f) ((f)<<S6_CBUF_DST_BLEND_FACT_SHIFT) -#define SRC_BLND_FACT(f) ((f)<<S6_CBUF_SRC_BLEND_FACT_SHIFT) -#define DST_ABLND_FACT(f) ((f)<<IAB_DST_FACTOR_SHIFT) -#define SRC_ABLND_FACT(f) ((f)<<IAB_SRC_FACTOR_SHIFT) +/* + Copyright (C) Intel Corp. 2006. All Rights Reserved. + Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to + develop this 3D driver. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice (including the + next paragraph) shall be included in all copies or substantial + portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + **********************************************************************/ + /* + * Authors: + * Keith Whitwell <keith@tungstengraphics.com> + */ + +#ifndef I915_STATE_H +#define I915_STATE_H +#include "i915_context.h" -static GLuint -translate_blend_equation(GLenum mode) -{ - switch (mode) { - case GL_FUNC_ADD: - return BLENDFUNC_ADD; - case GL_MIN: - return BLENDFUNC_MIN; - case GL_MAX: - return BLENDFUNC_MAX; - case GL_FUNC_SUBTRACT: - return BLENDFUNC_SUBTRACT; - case GL_FUNC_REVERSE_SUBTRACT: - return BLENDFUNC_REVERSE_SUBTRACT; - default: - return 0; - } -} +void i915_init_state( struct i915_context *i915 ); +void i915_destroy_state( struct i915_context *i915 ); + + +const struct intel_tracked_state i915_check_fallback; +const struct intel_tracked_state i915_fp_upload_constants; +const struct intel_tracked_state i915_fp_compile_and_upload; +const struct intel_tracked_state i915_fp_inputs; +const struct intel_tracked_state i915_invarient_state; +const struct intel_tracked_state i915_upload_BFO; +const struct intel_tracked_state i915_upload_BLENDCOLOR; +const struct intel_tracked_state i915_upload_IAB; +const struct intel_tracked_state i915_upload_MODES4; +const struct intel_tracked_state i915_upload_S0S1; +const struct intel_tracked_state i915_upload_S2S4; +const struct intel_tracked_state i915_upload_S5; +const struct intel_tracked_state i915_upload_S6; +const struct intel_tracked_state i915_upload_buffers; +const struct intel_tracked_state i915_upload_maps; +const struct intel_tracked_state i915_upload_samplers; +const struct intel_tracked_state i915_upload_scissor; +const struct intel_tracked_state i915_upload_stipple; + + +#endif diff --git a/src/mesa/drivers/dri/i915tex/i915_state_constants.c b/src/mesa/drivers/dri/i915tex/i915_state_constants.c deleted file mode 100644 index 8faac6b891..0000000000 --- a/src/mesa/drivers/dri/i915tex/i915_state_constants.c +++ /dev/null @@ -1,136 +0,0 @@ -/************************************************************************** - * - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - **************************************************************************/ - -#include "glheader.h" -#include "macros.h" -#include "enums.h" - -#include "tnl/tnl.h" -#include "tnl/t_context.h" -#include "intel_batchbuffer.h" - -#include "i915_reg.h" -#include "i915_context.h" -#include "i915_program.h" - -#include "program_instruction.h" -#include "program.h" -#include "programopt.h" - - - -static void -upload_params(struct i915_fragment_program *p) -{ - GLint i; - - - /* Always seemed to get a failure if I used memcmp() to - * shortcircuit this state upload. Needs further investigation? - */ - if (p->nr_constants) { - GLuint nr = p->nr_constants; - - I915_ACTIVESTATE(i915, I915_UPLOAD_CONSTANTS, 1); - I915_STATECHANGE(i915, I915_UPLOAD_CONSTANTS); - - i915->state.Constant[0] = _3DSTATE_PIXEL_SHADER_CONSTANTS | ((nr) * 4); - i915->state.Constant[1] = (1 << (nr - 1)) | ((1 << (nr - 1)) - 1); - - memcpy(&i915->state.Constant[2], p->constant, 4 * sizeof(int) * (nr)); - i915->state.ConstantSize = 2 + (nr) * 4; - - if (0) { - GLuint i; - for (i = 0; i < nr; i++) { - fprintf(stderr, "const[%d]: %f %f %f %f\n", i, - p->constant[i][0], - p->constant[i][1], p->constant[i][2], p->constant[i][3]); - } - } - } - else { - I915_ACTIVESTATE(i915, I915_UPLOAD_CONSTANTS, 0); - } - - -/////////////////////// - if (p->nr_params) - _mesa_load_state_parameters(p->ctx, p->FragProg.Base.Parameters); - - for (i = 0; i < p->nr_params; i++) { - GLint reg = p->param[i].reg; - COPY_4V(p->constant[reg], p->param[i].values); - } - - p->params_uptodate = 1; - - -///////////////// - - /* Allocate state in the indirect buffer and upload constants: - */ - - -} - - - - - -static void -track_params(struct i915_fragment_program *p) -{ - GLint i; - - if (p->nr_params) - _mesa_load_state_parameters(p->ctx, p->FragProg.Base.Parameters); - - for (i = 0; i < p->nr_params; i++) { - GLint reg = p->param[i].reg; - COPY_4V(p->constant[reg], p->param[i].values); - } - - p->params_uptodate = 1; -} - - -/* This tracked state is unique in that the state it monitors varies - * dynamically depending on the parameters tracked by the fragment and - * vertex programs. This is the template used as a starting point, - * each context will maintain a copy of this internally and update as - * required. - */ -const struct i915_tracked_state i915_constant_buffer = { - .dirty = { - .mesa = 0, /* plus fp flags */ - .intel = (I915_NEW_FRAGMENT_PROGRAM), - .cache = (CACHE_NEW_PROGRAM) /* ?? */ - }, - .update = upload_params -}; - diff --git a/src/mesa/drivers/dri/i915tex/i915_state_fp.c b/src/mesa/drivers/dri/i915tex/i915_state_fp.c index 6711bf2fcc..2b9b2e0b9d 100644 --- a/src/mesa/drivers/dri/i915tex/i915_state_fp.c +++ b/src/mesa/drivers/dri/i915tex/i915_state_fp.c @@ -28,65 +28,110 @@ #include "glheader.h" #include "macros.h" #include "enums.h" +#include "program.h" -#include "tnl/tnl.h" -#include "tnl/t_context.h" #include "intel_batchbuffer.h" - -#include "i915_reg.h" #include "i915_context.h" -#include "i915_program.h" +#include "i915_fpc.h" -#include "program_instruction.h" -#include "program.h" -#include "programopt.h" -void -i915_upload_program() -{ - if (dirty & I915_UPLOAD_PROGRAM) { - if (INTEL_DEBUG & DEBUG_STATE) - fprintf(stderr, "I915_UPLOAD_PROGRAM:\n"); - assert((state->Program[0] & 0x1ff) + 2 == state->ProgramSize); +/********************************************************************************* + * Program instructions (and decls) + */ + - emit(intel, state->Program, state->ProgramSize * sizeof(GLuint)); - if (INTEL_DEBUG & DEBUG_STATE) - i915_disassemble_program(state->Program, state->ProgramSize); +static void i915_upload_fp( struct intel_context *intel ) +{ + struct i915_context *i915 = i915_context( &intel->ctx ); + struct i915_fragment_program *fp = i915->fragment_program; + GLuint i; + + assert (&i915->fragment_program->Base == intel->state.FragmentProgram->_Current); + + /* As the compiled program depends only on the original program + * text (??? for now at least ???), there is no need for a compiled + * program cache, just store the compiled version with the original + * text. + */ + if (!fp->translated) { + i915_compile_fragment_program(i915, fp); } -} + BEGIN_BATCH( fp->program_size, 0 ); + for (i = 0; i < fp->program_size; i++) + OUT_BATCH( fp->program[i] ); + ADVANCE_BATCH(); +} -void -i915ValidateFragmentProgram(struct i915_context *i915) -{ - GLcontext *ctx = &i915->intel.ctx; - struct intel_context *intel = intel_context(ctx); - struct i915_fragment_program *p = - (struct i915_fragment_program *) ctx->FragmentProgram._Current; +/* See i915_wm.c: + */ +const struct intel_tracked_state i915_fp_compile_and_upload = { + .dirty = { + .mesa = (0), + .intel = (INTEL_NEW_FRAGMENT_PROGRAM), /* ?? Is this all ?? */ + .extra = 0 + }, + .update = i915_upload_fp +}; - int i, offset = 0; - if (i915->current_program != p) { +/********************************************************************************* + * Program constants and state parameters + */ +static void +upload_constants(struct intel_context *intel) +{ + struct i915_context *i915 = i915_context( &intel->ctx ); + struct i915_fragment_program *p = i915->fragment_program; + GLint i; + /* XXX: Pull from state, not ctx!!! + */ + if (p->nr_params) + _mesa_load_state_parameters(&intel->ctx, p->Base.Base.Parameters); - i915->current_program = p; + for (i = 0; i < p->nr_params; i++) { + GLint reg = p->param[i].reg; + COPY_4V(p->constant[reg], p->param[i].values); } - - /* Important: + /* Always seemed to get a failure if I used memcmp() to + * shortcircuit this state upload. Needs further investigation? */ - VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr; - - if (!p->translated) - translate_program(p); - - - i915_upload_program(i915, p); + if (p->nr_constants) { + GLuint nr = p->nr_constants; + + BEGIN_BATCH( nr * 4 + 2, 0 ); + OUT_BATCH( _3DSTATE_PIXEL_SHADER_CONSTANTS | (nr * 4) ); + OUT_BATCH( (1 << (nr - 1)) | ((1 << (nr - 1)) - 1) ); + + for (i = 0; i < nr; i++) { + OUT_BATCH(p->constant[i][0]); + OUT_BATCH(p->constant[i][1]); + OUT_BATCH(p->constant[i][2]); + OUT_BATCH(p->constant[i][3]); + } + } } + +/* This tracked state is unique in that the state it monitors varies + * dynamically depending on the parameters tracked by the fragment and + * vertex programs. This is the template used as a starting point, + * each context will maintain a copy of this internally and update as + * required. + */ +const struct intel_tracked_state intel_constants = { + .dirty = { + .mesa = 0, /* plus fp state flags */ + .intel = INTEL_NEW_FRAGMENT_PROGRAM, + .extra = 0 + }, + .update = upload_constants +}; diff --git a/src/mesa/drivers/dri/i915tex/i915_state_fp_inputs.c b/src/mesa/drivers/dri/i915tex/i915_state_fp_inputs.c index d7ec11500a..65dc10ec28 100644 --- a/src/mesa/drivers/dri/i915tex/i915_state_fp_inputs.c +++ b/src/mesa/drivers/dri/i915tex/i915_state_fp_inputs.c @@ -1,68 +1,113 @@ - -static void -check_wpos(struct i915_fragment_program *p) +/************************************************************************** + * + * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ + +#include "glheader.h" +#include "macros.h" +#include "enums.h" +#include "program.h" + +#include "intel_batchbuffer.h" +#include "i915_context.h" +#include "i915_reg.h" +#include "tnl/t_context.h" +#include "tnl/t_vertex.h" + + +#if 0 +/* Scan the TNL VB struct and look at the size of each attribute + * coming out. + * + * The fragment program has been determined by this point, so it is ok + * to restrict the list to the inputs referenced by the fragprog. + * + * This is not a + */ +void check_input_sizes( struct intel_context *intel ) { - GLuint inputs = p->FragProg.Base.InputsRead; - GLint i; - - p->wpos_tex = -1; - - for (i = 0; i < p->ctx->Const.MaxTextureCoordUnits; i++) { - if (inputs & FRAG_BIT_TEX(i)) - continue; - else if (inputs & FRAG_BIT_WPOS) { - p->wpos_tex = i; - inputs &= ~FRAG_BIT_WPOS; - } - } - - if (inputs & FRAG_BIT_WPOS) { - i915_program_error(p, "No free texcoord for wpos value"); - } -} - - -static void brw_merge_inputs( struct brw_context *brw, - const struct gl_client_array *arrays[]) -{ - struct brw_vertex_element *inputs = brw->vb.inputs; - struct brw_vertex_info old = brw->vb.info; + struct i915_context *i915 = i915_context( &intel->ctx ); + GLcontext *ctx = &intel->ctx; + struct vertex_buffer *VB = &TNL_CONTEXT(ctx)->vb; + GLubyte old_sizes[8]; GLuint i; - memset(inputs, 0, sizeof(*inputs)); - memset(&brw->vb.info, 0, sizeof(brw->vb.info)); - - for (i = 0; i < VERT_ATTRIB_MAX; i++) { - brw->vb.inputs[i].glarray = arrays[i]; - - /* XXX: metaops passes null arrays */ - if (arrays[i]) { - if (arrays[i]->StrideB != 0) - brw->vb.info.varying |= 1 << i; + memcpy(old_sizes, i915->fragprog.input_sizes, sizeof(old_sizes)); - brw->vb.info.sizes[i/16] |= (inputs[i].glarray->Size - 1) << ((i%16) * 2); - } + for (i = 0; i < FRAG_ATTRIB_MAX; i++) { + GLvector4f *attrib = VB->AttribPtr[i]; + i915->fragprog.input_sizes[i] = attrib->size; } /* Raise statechanges if input sizes and varying have changed: */ - if (memcmp(brw->vb.info.sizes, old.sizes, sizeof(old.sizes)) != 0) - brw->state.dirty.brw |= BRW_NEW_INPUT_DIMENSIONS; - - if (brw->vb.info.varying != old.varying) - brw->state.dirty.brw |= BRW_NEW_INPUT_VARYING; + if (memcmp(i915->fragprog.input_sizes, old_sizes, sizeof(old_sizes)) != 0) + intel->state.dirty.intel |= I915_NEW_INPUT_SIZES; } +#endif +/*********************************************************************** + * + */ +#define SZ_TO_HW(sz) ((sz-2)&0x3) +#define EMIT_SZ(sz) (EMIT_1F + (sz) - 1) +#define EMIT_ATTR( ATTR, STYLE, S4, SZ ) \ +do { \ + intel->vertex_attrs[intel->vertex_attr_count].attrib = (ATTR); \ + intel->vertex_attrs[intel->vertex_attr_count].format = (STYLE); \ + s4 |= S4; \ + intel->vertex_attr_count++; \ + offset += (SZ); \ +} while (0) +#define EMIT_PAD( N ) \ +do { \ + intel->vertex_attrs[intel->vertex_attr_count].attrib = 0; \ + intel->vertex_attrs[intel->vertex_attr_count].format = EMIT_PAD; \ + intel->vertex_attrs[intel->vertex_attr_count].offset = (N); \ + intel->vertex_attr_count++; \ + offset += (N); \ +} while (0) - TNLcontext *tnl = TNL_CONTEXT(ctx); - struct vertex_buffer *VB = &tnl->vb; - const GLuint inputsRead = p->FragProg.Base.InputsRead; +/*********************************************************************** + * + */ +static void i915_calculate_vertex_format( struct intel_context *intel ) +{ + struct i915_context *i915 = i915_context( &intel->ctx ); + struct i915_fragment_program *fp = i915->fragment_program; + const GLuint inputsRead = fp->Base.Base.InputsRead; + GLuint s2 = S2_TEXCOORD_NONE; + GLuint s4 = 0; + GLuint offset = 0; + GLuint i; intel->vertex_attr_count = 0; intel->wpos_offset = 0; @@ -83,7 +128,6 @@ static void brw_merge_inputs( struct brw_context *brw, } if (inputsRead & (FRAG_BIT_COL1 | FRAG_BIT_FOGC)) { - if (inputsRead & FRAG_BIT_COL1) { intel->specoffset = offset / 4; EMIT_ATTR(_TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR, S4_VFMT_SPEC_FOG, 3); @@ -101,16 +145,20 @@ static void brw_merge_inputs( struct brw_context *brw, EMIT_ATTR(_TNL_ATTRIB_FOG, EMIT_1F, S4_VFMT_FOG_PARAM, 4); } - for (i = 0; i < p->ctx->Const.MaxTextureCoordUnits; i++) { - if (inputsRead & FRAG_BIT_TEX(i)) { - int sz = VB->TexCoordPtr[i]->size; + for (i = 0; i < I915_TEX_UNITS; i++) { + if (inputsRead & (FRAG_BIT_TEX0 << i)) { + + /* _NEW_VB_OUTPUT_SIZES + */ +/* int sz = VB->TexCoordPtr[i]->size; */ + int sz = 2; s2 &= ~S2_TEXCOORD_FMT(i, S2_TEXCOORD_FMT0_MASK); s2 |= S2_TEXCOORD_FMT(i, SZ_TO_HW(sz)); EMIT_ATTR(_TNL_ATTRIB_TEX0 + i, EMIT_SZ(sz), 0, sz * 4); } - else if (i == p->wpos_tex) { + else if (i == fp->wpos_tex) { /* If WPOS is required, duplicate the XYZ position data in an * unused texture coordinate: @@ -125,26 +173,33 @@ static void brw_merge_inputs( struct brw_context *brw, } } + if (s2 != i915->fragprog.LIS2 || + s4 != i915->fragprog.LIS4) { + GLuint vs = _tnl_install_attrs(&intel->ctx, + intel->vertex_attrs, + intel->vertex_attr_count, + intel->ViewportMatrix.m, 0); - GLuint s4 = i915->state.Ctx[I915_CTXREG_LIS4] & ~S4_VFMT_MASK; - GLuint s2 = S2_TEXCOORD_NONE; - if (s2 != i915->state.Ctx[I915_CTXREG_LIS2] || - s4 != i915->state.Ctx[I915_CTXREG_LIS4]) { - int k; - - I915_STATECHANGE(i915, I915_UPLOAD_CTX); + intel->vertex_size = vs >> 2; + i915->fragprog.LIS2 = s2; + i915->fragprog.LIS4 = s4; + intel->state.dirty.intel |= I915_NEW_VERTEX_FORMAT; + } +} - /* Must do this *after* statechange, so as not to affect - * buffered vertices reliant on the old state: - */ - intel->vertex_size = _tnl_install_attrs(&intel->ctx, - intel->vertex_attrs, - intel->vertex_attr_count, - intel->ViewportMatrix.m, 0); - intel->vertex_size >>= 2; +/* Could use the information calculated here to optimize the fragment + * program. + */ +const struct intel_tracked_state i915_vertex_format = { + .dirty = { + .mesa = 0, + .intel = (I915_NEW_FRAGMENT_PROGRAM +/* | INTEL_NEW_VB_OUTPUT_SIZES */ + ), + .extra = 0 + }, + .update = i915_calculate_vertex_format +}; - i915->state.Ctx[I915_CTXREG_LIS2] = s2; - i915->state.Ctx[I915_CTXREG_LIS4] = s4; - } diff --git a/src/mesa/drivers/dri/i915tex/i915_state_immediate.c b/src/mesa/drivers/dri/i915tex/i915_state_immediate.c index e3090eb743..56e4ea4ce8 100644 --- a/src/mesa/drivers/dri/i915tex/i915_state_immediate.c +++ b/src/mesa/drivers/dri/i915tex/i915_state_immediate.c @@ -1,52 +1,60 @@ -/* - Copyright (C) Intel Corp. 2006. All Rights Reserved. - Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to - develop this 3D driver. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice (including the - next paragraph) shall be included in all copies or substantial - portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - - **********************************************************************/ +/************************************************************************** + * + * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ /* * Authors: * Keith Whitwell <keith@tungstengraphics.com> */ - #include "intel_batchbuffer.h" #include "intel_regions.h" +#include "intel_state_inlines.h" + +#include "macros.h" + +#include "i915_context.h" +#include "i915_state.h" +#include "i915_state_inlines.h" +#include "i915_reg.h" + + +#define STATE_LOGICOP_ENABLED(state) \ + ((state)->Color->ColorLogicOpEnabled || \ + ((state)->Color->BlendEnabled && (state)->Color->BlendEquationRGB == GL_LOGIC_OP)) -#include "brw_context.h" -#include "brw_state.h" -#include "brw_defines.h" /*********************************************************************** * S0,S1: Vertex buffer state. */ -static void upload_S0S1( struct i915_context *i915 ) +static void upload_S0S1( struct intel_context *intel ) { - struct intel_context *intel = &i915->intel; /* INTEL_NEW_VBO */ - if (intel->vb->state.current_vbo) { + if (intel->state.vbo) { BEGIN_BATCH(3, 0); @@ -56,10 +64,10 @@ static void upload_S0S1( struct i915_context *i915 ) 2); /* INTEL_NEW_VBO, INTEL_NEW_RELOC */ - OUT_RELOC(intel->vb->state.current_vbo->buffer, + OUT_RELOC(intel->state.vbo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, DRM_BO_MASK_MEM | DRM_BO_FLAG_READ, - intel->vb->state.hw_vbo_offset); + intel->state.vbo_offset); /* INTEL_NEW_VERTEX_SIZE */ OUT_BATCH((intel->vertex_size << 24) | @@ -69,102 +77,97 @@ static void upload_S0S1( struct i915_context *i915 ) } } -const struct i915_tracked_state i915_upload_S0S1 = { +const struct intel_tracked_state i915_upload_S0S1 = { .dirty = { .mesa = 0, - .intel = INTEL_NEW_VBO | INTEL_NEW_VERTEX_SIZE | INTEL_NEW_RELOC, - .indirect = 0 + .intel = INTEL_NEW_VBO | INTEL_NEW_VERTEX_SIZE | INTEL_NEW_FENCE, + .extra = 0 }, .update = upload_S0S1 }; -/*********************************************************************** - * S2: Vertex format - */ -static void upload_S2( struct i915_context *i915 ) -{ - /* I915_NEW_FRAGPROG */ - i915->state.Ctx[I915_CTXREG_LIS2] = i915->state.fragprog.LIS2; -} - -const struct i915_tracked_state i915_upload_S2 = { - .dirty = { - .mesa = 0, - .intel = I915_NEW_FRAGPROG, - .indirect = 0 - }, - .update = upload_S2 -}; /*********************************************************************** * S4: Vertex format, rasterization state */ -static void upload_S4(struct brw_context *brw) +static void upload_S2S4(struct intel_context *intel) { - - /* I915_NEW_FRAGPROG */ - i915->state.Ctx[I915_CTXREG_LIS4] |= i915->state.fragprog.LIS4; + struct i915_context *i915 = i915_context( &intel->ctx ); + GLuint LIS2, LIS4; + + /* I915_NEW_VERTEX_FORMAT */ + LIS2 = i915->fragprog.LIS2; + LIS4 = i915->fragprog.LIS4; /* _NEW_POLYGON, _NEW_BUFFERS */ { GLuint mode; - if (!ctx->Polygon.CullFlag) { + if (!intel->state.Polygon->CullFlag) { mode = S4_CULLMODE_NONE; } - else if (ctx->Polygon.CullFaceMode != GL_FRONT_AND_BACK) { + else if (intel->state.Polygon->CullFaceMode != GL_FRONT_AND_BACK) { mode = S4_CULLMODE_CW; - if (ctx->DrawBuffer && ctx->DrawBuffer->Name != 0) + if (intel->state.DrawBuffer && intel->state.DrawBuffer->Name != 0) mode ^= (S4_CULLMODE_CW ^ S4_CULLMODE_CCW); - if (ctx->Polygon.CullFaceMode == GL_FRONT) + if (intel->state.Polygon->CullFaceMode == GL_FRONT) mode ^= (S4_CULLMODE_CW ^ S4_CULLMODE_CCW); - if (ctx->Polygon.FrontFace != GL_CCW) + if (intel->state.Polygon->FrontFace != GL_CCW) mode ^= (S4_CULLMODE_CW ^ S4_CULLMODE_CCW); } else { mode = S4_CULLMODE_BOTH; } - i915->state.Ctx[I915_CTXREG_LIS4] |= mode; + + LIS4 |= mode; } /* _NEW_LINE */ { - GLint width = (GLint) (ctx->Line.Width * 2); + GLint width = (GLint) (intel->state.Line->Width * 2); CLAMP_SELF(width, 1, 0xf); - i915->state.Ctx[I915_CTXREG_LIS4] |= width << S4_LINE_WIDTH_SHIFT; + LIS4 |= width << S4_LINE_WIDTH_SHIFT; - if (ctx->Line.Smooth) - i915->state.Ctx[I915_CTXREG_LIS4] |= S4_LINE_ANTIALIAS_ENABLE; + if (intel->state.Line->SmoothFlag) + LIS4 |= S4_LINE_ANTIALIAS_ENABLE; } /* _NEW_POINT */ { - GLint point_size = (int) ctx->Point._Size; + GLint point_size = (int) intel->state.Point->_Size; CLAMP_SELF(point_size, 1, 255); - i915->state.Ctx[I915_CTXREG_LIS4] |= point_size << S4_POINT_WIDTH_SHIFT; + LIS4 |= point_size << S4_POINT_WIDTH_SHIFT; } /* _NEW_LIGHT */ - if (ctx->Light.ShadeModel == GL_FLAT) { - i915->state.Ctx[I915_CTXREG_LIS4] |= (S4_FLATSHADE_ALPHA | - S4_FLATSHADE_COLOR | - S4_FLATSHADE_SPECULAR); + if (intel->state.Light->ShadeModel == GL_FLAT) { + LIS4 |= (S4_FLATSHADE_ALPHA | + S4_FLATSHADE_COLOR | + S4_FLATSHADE_SPECULAR); } - - I915_SET_STATE_IMMEDIATE(i915, , &bcc); + + BEGIN_BATCH(3, 0); + + OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | + I1_LOAD_S(2) | + I1_LOAD_S(4) | + 2); + OUT_BATCH(LIS2); + OUT_BATCH(LIS4); + ADVANCE_BATCH(); } -const struct i915_tracked_state i915_upload_S4 = { +const struct intel_tracked_state i915_upload_S2S4 = { .dirty = { .mesa = (_NEW_POLYGON | _NEW_BUFFERS | @@ -172,10 +175,10 @@ const struct i915_tracked_state i915_upload_S4 = { _NEW_POINT | _NEW_LIGHT), - .intel = I915_NEW_FRAGPROG, - .indirect = 0 + .intel = I915_NEW_VERTEX_FORMAT, + .extra = 0 }, - .update = upload_S4 + .update = upload_S2S4 }; @@ -183,63 +186,66 @@ const struct i915_tracked_state i915_upload_S4 = { /*********************************************************************** * */ -static void upload_S5( struct i915_context *i915 ) +static void upload_S5( struct intel_context *intel ) { + GLuint LIS5 = 0; + /* _NEW_STENCIL */ - if (ctx->Stencil.Enabled) { - GLint test = intel_translate_compare_func(ctx->Stencil.Function[0]); - GLint fop = intel_translate_stencil_op(fail); - GLint dfop = intel_translate_stencil_op(zfail); - GLint dpop = intel_translate_stencil_op(zpass); + if (intel->state.Stencil->Enabled) { + GLint test = intel_translate_compare_func(intel->state.Stencil->Function[0]); + GLint fop = intel_translate_stencil_op(intel->state.Stencil->FailFunc[0]); + GLint dfop = intel_translate_stencil_op(intel->state.Stencil->ZFailFunc[0]); + GLint dpop = intel_translate_stencil_op(intel->state.Stencil->ZPassFunc[0]); + GLint ref = intel->state.Stencil->Ref[0] & 0xff; - i915->state.Ctx[I915_CTXREG_LIS5] |= (S5_STENCIL_TEST_ENABLE | - S5_STENCIL_WRITE_ENABLE); - - i915->state.Ctx[I915_CTXREG_LIS5] |= ((ref << S5_STENCIL_REF_SHIFT) | - (test << - S5_STENCIL_TEST_FUNC_SHIFT)); - - - - i915->state.Ctx[I915_CTXREG_LIS5] |= ((fop << S5_STENCIL_FAIL_SHIFT) | - (dfop << - S5_STENCIL_PASS_Z_FAIL_SHIFT) | - (dpop << - S5_STENCIL_PASS_Z_PASS_SHIFT)); - + LIS5 |= (S5_STENCIL_TEST_ENABLE | + S5_STENCIL_WRITE_ENABLE | + (ref << S5_STENCIL_REF_SHIFT) | + (test << S5_STENCIL_TEST_FUNC_SHIFT) | + (fop << S5_STENCIL_FAIL_SHIFT) | + (dfop << S5_STENCIL_PASS_Z_FAIL_SHIFT) | + (dpop << S5_STENCIL_PASS_Z_PASS_SHIFT)); } /* _NEW_COLOR */ - if (RGBA_LOGICOP_ENABLED(ctx)) { - i915->state.Ctx[I915_CTXREG_LIS5] |= S5_LOGICOP_ENABLE; + if (STATE_LOGICOP_ENABLED(&intel->state)) { + LIS5 |= S5_LOGICOP_ENABLE; } - if (ctx->Color.DitherFlag) { - i915->state.Ctx[I915_CTXREG_LIS5] |= S5_COLOR_DITHER_ENABLE; + if (intel->state.Color->DitherFlag) { + LIS5 |= S5_COLOR_DITHER_ENABLE; } { - const GLubyte *mask = ctx->Color.ColorMask; + const GLubyte *mask = intel->state.Color->ColorMask; if (!mask[0]) - i915->state.Ctx[I915_CTXREG_LIS5] |= S5_WRITEDISABLE_RED; + LIS5 |= S5_WRITEDISABLE_RED; if (!mask[1]) - i915->state.Ctx[I915_CTXREG_LIS5] |= S5_WRITEDISABLE_GREEN; + LIS5 |= S5_WRITEDISABLE_GREEN; if (!mask[2]) - i915->state.Ctx[I915_CTXREG_LIS5] |= S5_WRITEDISABLE_BLUE; + LIS5 |= S5_WRITEDISABLE_BLUE; if (!mask[3]) - i915->state.Ctx[I915_CTXREG_LIS5] |= S5_WRITEDISABLE_ALPHA; + LIS5 |= S5_WRITEDISABLE_ALPHA; } + + BEGIN_BATCH(2, 0); + OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | + I1_LOAD_S(5) | + 1); + OUT_BATCH(LIS5); + ADVANCE_BATCH(); + } -const struct i915_tracked_state i915_upload_S5 = { +const struct intel_tracked_state i915_upload_S5 = { .dirty = { .mesa = (_NEW_STENCIL | _NEW_COLOR), .intel = 0, - .indirect = 0 + .extra = 0 }, .update = upload_S5 }; @@ -247,68 +253,70 @@ const struct i915_tracked_state i915_upload_S5 = { /*********************************************************************** */ -static void upload_S6( struct i915_context *i915 ) +static void upload_S6( struct intel_context *intel ) { - struct i915_context *i915 = I915_CONTEXT(ctx); - - - i915->state.Ctx[I915_CTXREG_LIS6] = (S6_COLOR_WRITE_ENABLE | - (2 << S6_TRISTRIP_PV_SHIFT)); + GLuint LIS6 = (S6_COLOR_WRITE_ENABLE | + (2 << S6_TRISTRIP_PV_SHIFT)); /* _NEW_COLOR */ - if (ctx->Color.AlphaTest) { - int test = intel_translate_compare_func(ctx->Color.AlphaFunc); + if (intel->state.Color->AlphaEnabled) { + int test = intel_translate_compare_func(intel->state.Color->AlphaFunc); GLubyte refByte; - CLAMPED_FLOAT_TO_UBYTE(refByte, ctx->Color.AlphaRef); + CLAMPED_FLOAT_TO_UBYTE(refByte, intel->state.Color->AlphaRef); - i915->state.Ctx[I915_CTXREG_LIS6] |= S6_ALPHA_TEST_ENABLE; + LIS6 |= S6_ALPHA_TEST_ENABLE; - i915->state.Ctx[I915_CTXREG_LIS6] |= ((test << S6_ALPHA_TEST_FUNC_SHIFT) | - (((GLuint) refByte) << S6_ALPHA_REF_SHIFT)); + LIS6 |= ((test << S6_ALPHA_TEST_FUNC_SHIFT) | + (((GLuint) refByte) << S6_ALPHA_REF_SHIFT)); } /* _NEW_COLOR */ - if (ctx->Color.BlendEnabled && !RGBA_LOGICOP_ENABLED(ctx)) { - - GLuint eqRGB = ctx->Color.BlendEquationRGB; - GLuint eqA = ctx->Color.BlendEquationA; - GLuint srcRGB = ctx->Color.BlendSrcRGB; - GLuint dstRGB = ctx->Color.BlendDstRGB; - GLuint srcA = ctx->Color.BlendSrcA; - GLuint dstA = ctx->Color.BlendDstA; + if (intel->state.Color->BlendEnabled && + !STATE_LOGICOP_ENABLED(&intel->state)) { + + GLuint eqRGB = intel->state.Color->BlendEquationRGB; + GLuint srcRGB = intel->state.Color->BlendSrcRGB; + GLuint dstRGB = intel->state.Color->BlendDstRGB; if (eqRGB == GL_MIN || eqRGB == GL_MAX) { srcRGB = dstRGB = GL_ONE; } - i915->state.Ctx[I915_CTXREG_LIS6] |= S6_CBUF_BLEND_ENABLE; - - lis6 |= SRC_BLND_FACT(intel_translate_blend_factor(srcRGB)); - lis6 |= DST_BLND_FACT(intel_translate_blend_factor(dstRGB)); - lis6 |= translate_blend_equation(eqRGB) << S6_CBUF_BLEND_FUNC_SHIFT; + LIS6 |= (S6_CBUF_BLEND_ENABLE | + SRC_BLND_FACT(intel_translate_blend_factor(srcRGB)) | + DST_BLND_FACT(intel_translate_blend_factor(dstRGB)) | + (i915_translate_blend_equation(eqRGB) << S6_CBUF_BLEND_FUNC_SHIFT)); } /* _NEW_DEPTH */ - if (ctx->Depth.Test) { - GLint func = intel_translate_compare_func(ctx->Depth.Func); + if (intel->state.Depth->Test) { + GLint func = intel_translate_compare_func(intel->state.Depth->Func); - i915->state.Ctx[I915_CTXREG_LIS6] |= S6_DEPTH_TEST_ENABLE; - i915->state.Ctx[I915_CTXREG_LIS6] |= func << S6_DEPTH_TEST_FUNC_SHIFT; + LIS6 |= S6_DEPTH_TEST_ENABLE; + LIS6 |= func << S6_DEPTH_TEST_FUNC_SHIFT; - if (ctx->Depth.Mask) - i915->state.Ctx[I915_CTXREG_LIS6] |= S6_DEPTH_WRITE_ENABLE; + if (intel->state.Depth->Mask) + LIS6 |= S6_DEPTH_WRITE_ENABLE; } + + BEGIN_BATCH(2, 0); + OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | + I1_LOAD_S(6) | + 1); + OUT_BATCH(LIS6); + ADVANCE_BATCH(); + } -const struct i915_tracked_state i915_upload_S6 = { +const struct intel_tracked_state i915_upload_S6 = { .dirty = { .mesa = (_NEW_COLOR | _NEW_DEPTH), .intel = 0, - .indirect = 0 + .extra = 0 }, .update = upload_S6 }; diff --git a/src/mesa/drivers/dri/i915tex/i915_state_map.c b/src/mesa/drivers/dri/i915tex/i915_state_map.c index df85a8c344..fee52d5dbd 100644 --- a/src/mesa/drivers/dri/i915tex/i915_state_map.c +++ b/src/mesa/drivers/dri/i915tex/i915_state_map.c @@ -32,6 +32,7 @@ #include "intel_mipmap_tree.h" #include "intel_tex.h" +#include "intel_batchbuffer.h" #include "i915_context.h" #include "i915_reg.h" @@ -86,116 +87,97 @@ translate_texture_format(GLuint mesa_format) static void -upload_maps( struct i915_context *i915 ) +upload_maps( struct intel_context *intel ) { - GLcontext *ctx = &i915->intel.ctx; + struct i915_context *i915 = i915_context( &intel->ctx ); + GLuint state[I915_TEX_UNITS][2]; + GLuint i, dirty = 0, nr = 0; - for (unit = 0; unit < I915_TEX_UNITS; unit++) { - switch (ctx.Texture.Unit[unit]._ReallyEnabled) { + for (i = 0; i < I915_TEX_UNITS; i++) { + /* Decrement refcounts on old buffers + */ + if (i915->state.tex_buffer[i] != NULL) { + driBOUnReference(i915->state.tex_buffer[i]); + i915->state.tex_buffer[i] = NULL; + } - struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current; + if (intel->state.Texture->Unit[i]._ReallyEnabled) { + struct gl_texture_object *tObj = intel->state.Texture->Unit[i]._Current; struct intel_texture_object *intelObj = intel_texture_object(tObj); struct gl_texture_image *firstImage; - GLuint *state = i915->state.Tex[unit]; - - memset(state, 0, sizeof(state)); - /*We need to refcount these. */ - - if (i915->state.tex_buffer[unit] != NULL) { - driBOUnReference(i915->state.tex_buffer[unit]); - i915->state.tex_buffer[unit] = NULL; + if (!intel_finalize_mipmap_tree(intel, i)) { + /* XXX: TODO */ +/* return GL_FALSE; */ + assert(0); } - - if (!intel_finalize_mipmap_tree(intel, unit)) - return GL_FALSE; + + /* Reference new buffers + */ + i915->state.tex_buffer[i] = driBOReference(intelObj->mt->region->buffer); + i915->state.tex_offset[i] = intel_miptree_image_offset(intelObj->mt, 0, + intelObj-> firstLevel); /* Get first image here, since intelObj->firstLevel will get set in * the intel_finalize_mipmap_tree() call above. */ firstImage = tObj->Image[0][intelObj->firstLevel]; - i915->state.tex_buffer[unit] = driBOReference(intelObj->mt->region->buffer); - i915->state.tex_offset[unit] = intel_miptree_image_offset(intelObj->mt, 0, - intelObj-> - firstLevel); - - state[I915_TEXREG_MS3] = + state[i][0] = (((firstImage->Height - 1) << MS3_HEIGHT_SHIFT) | ((firstImage->Width - 1) << MS3_WIDTH_SHIFT) | translate_texture_format(firstImage->TexFormat->MesaFormat) | MS3_USE_FENCE_REGS); - state[I915_TEXREG_MS4] = + state[i][1] = (((((intelObj->mt->pitch * intelObj->mt->cpp) / 4) - 1) << MS4_PITCH_SHIFT) | MS4_CUBE_FACE_ENA_MASK | ((((intelObj->lastLevel - intelObj->firstLevel) * 4)) << MS4_MAX_LOD_SHIFT) | ((firstImage->Depth - 1) << MS4_VOLUME_DEPTH_SHIFT)); - - DBG(TEXTURE, "state[I915_TEXREG_MS2] = 0x%x\n", state[I915_TEXREG_MS2]); - DBG(TEXTURE, "state[I915_TEXREG_MS3] = 0x%x\n", state[I915_TEXREG_MS3]); - DBG(TEXTURE, "state[I915_TEXREG_MS4] = 0x%x\n", state[I915_TEXREG_MS4]); - + dirty |= (1<<i); + nr++; } } - else { - if (i915->state.active & I915_UPLOAD_TEX(i)) - I915_ACTIVESTATE(i915, I915_UPLOAD_TEX(i), GL_FALSE); - - if (i915->state.tex_buffer[i] != NULL) { - driBOUnReference(i915->state.tex_buffer[i]); - i915->state.tex_buffer[i] = NULL; - } - break; - } + BEGIN_BATCH(2 + nr * 3, 0); + OUT_BATCH(_3DSTATE_MAP_STATE | (3 * nr)); + OUT_BATCH(dirty); - { - int nr = 0; - - for (i = 0; i < I915_TEX_UNITS; i++) - if (dirty & I915_UPLOAD_TEX(i)) - nr++; - - BEGIN_BATCH(2 + nr * 3, 0); - OUT_BATCH(_3DSTATE_MAP_STATE | (3 * nr)); - OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT); - for (i = 0; i < I915_TEX_UNITS; i++) { - if (dirty & I915_UPLOAD_TEX(i)) { - - if (state->tex_buffer[i]) { - OUT_RELOC(state->tex_buffer[i], - DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, - DRM_BO_MASK_MEM | DRM_BO_FLAG_READ, - state->tex_offset[i]); - } - else { - assert(i == 0); - assert(state == &i915->meta); - OUT_BATCH(0); - } - - OUT_BATCH(state->Tex[i][I915_TEXREG_MS3]); - OUT_BATCH(state->Tex[i][I915_TEXREG_MS4]); + for (i = 0; i < I915_TEX_UNITS; i++) { + if (dirty & (1<<i)) { + + if (i915->state.tex_buffer[i]) { + OUT_RELOC(i915->state.tex_buffer[i], + DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, + DRM_BO_MASK_MEM | DRM_BO_FLAG_READ, + i915->state.tex_offset[i]); } + else { + assert(i == 0); + assert(intel->metaops.active); /* when does this happen? */ + OUT_BATCH(0); + } + + OUT_BATCH(state[i][3]); + OUT_BATCH(state[i][4]); } - ADVANCE_BATCH(); } + ADVANCE_BATCH(); - return GL_TRUE; +/* return GL_TRUE; */ } -const struct i915_tracked_state i915_upload_maps = { +const struct intel_tracked_state i915_upload_maps = { .dirty = { .mesa = (_NEW_TEXTURE), .intel = 0, - .indirect = 0 + .extra = 0 }, .update = upload_maps }; diff --git a/src/mesa/drivers/dri/i915tex/i915_state_misc.c b/src/mesa/drivers/dri/i915tex/i915_state_misc.c index 8dbed0092f..07cf8afa65 100644 --- a/src/mesa/drivers/dri/i915tex/i915_state_misc.c +++ b/src/mesa/drivers/dri/i915tex/i915_state_misc.c @@ -25,67 +25,70 @@ * **************************************************************************/ - #include "glheader.h" #include "context.h" #include "macros.h" #include "enums.h" -#include "dd.h" -#include "tnl/tnl.h" -#include "tnl/t_context.h" - -#include "texmem.h" #include "intel_fbo.h" -#include "intel_screen.h" #include "intel_batchbuffer.h" +#include "intel_regions.h" +#include "intel_state_inlines.h" #include "i915_context.h" #include "i915_reg.h" +#include "i915_state.h" +#include "i915_state_inlines.h" #define FILE_DEBUG_FLAG DEBUG_STATE /*********************************************************************** * Modes4: stencil masks and logicop */ -static void upload_MODES4( struct i915_context *i915 ) +static void upload_MODES4( struct intel_context *intel ) { - i915->state.Ctx[I915_CTXREG_MODES4] = _3DSTATE_MODES_4_CMD; + GLuint modes4 = _3DSTATE_MODES_4_CMD; /* _NEW_STENCIL */ - if (ctx->Stencil.Enabled) { - GLint testmask = ctx->Stencil.ValueMask[0] & 0xff; - GLint writemask = ctx->Stencil.WriteMask[0] & 0xff; - - i915->state.Ctx[I915_CTXREG_MODES4] |= (ENABLE_STENCIL_TEST_MASK | - STENCIL_TEST_MASK(mask) | - ENABLE_STENCIL_WRITE_MASK | - STENCIL_WRITE_MASK(writemask)); + if (intel->state.Stencil->Enabled) { + GLint testmask = intel->state.Stencil->ValueMask[0] & 0xff; + GLint writemask = intel->state.Stencil->WriteMask[0] & 0xff; + + modes4 |= (ENABLE_STENCIL_TEST_MASK | + STENCIL_TEST_MASK(testmask) | + ENABLE_STENCIL_WRITE_MASK | + STENCIL_WRITE_MASK(writemask)); } /* _NEW_COLOR */ - if (ctx->Color._LogicOpEnabled) + if (intel->state.Color->_LogicOpEnabled) { - int tmp = intel_translate_logic_op(ctx->Color.LogicOp); - - i915->state.Ctx[I915_CTXREG_MODES4] |= (ENABLE_LOGIC_OP_FUNC | - LOGIC_OP_FUNC(tmp)); + modes4 |= (ENABLE_LOGIC_OP_FUNC | + LOGIC_OP_FUNC(intel_translate_logic_op(intel->state.Color->LogicOp))); } else { /* This seems to be the only way to turn off logicop. The * ENABLE_LOGIC_OP_FUNC is just a modify-enable bit to say this * field is present in the instruction. */ - i915->state.Ctx[I915_CTXREG_MODES4] |= (ENABLE_LOGIC_OP_FUNC | - LOGICOP_COPY); + modes4 |= (ENABLE_LOGIC_OP_FUNC | + LOGICOP_COPY); } + + /* This needs to be sent in all states (subject eventually to + * caching to avoid duplicate emits, and later to indirect state + * management) + */ + BEGIN_BATCH(1,0); + OUT_BATCH(modes4); + ADVANCE_BATCH(); } -const struct i915_tracked_state i915_upload_MODES4 = { +const struct intel_tracked_state i915_upload_MODES4 = { .dirty = { .mesa = _NEW_STENCIL | _NEW_COLOR, .intel = 0, - .indirect = 0 + .extra = 0 }, .update = upload_MODES4 }; @@ -95,28 +98,29 @@ const struct i915_tracked_state i915_upload_MODES4 = { * BFO: Backface stencil */ -static void upload_BFO( struct i915_context *i915 ) +static void upload_BFO( struct intel_context *intel ) { - i915->state.Ctx[I915_CTXREG_BFO] = _3DSTATE_BACKFACE_STENCIL_OPS; + GLuint bfo; /* _NEW_STENCIL */ - if (ctx->Stencil.Enabled) { - GLint test = intel_translate_compare_func(ctx->Stencil.Function[1]); - GLint fop = intel_translate_stencil_op(fail); - GLint dfop = intel_translate_stencil_op(zfail); - GLint dpop = intel_translate_stencil_op(zpass); + if (intel->state.Stencil->Enabled) { + GLint test = intel_translate_compare_func(intel->state.Stencil->Function[1]); + GLint fop = intel_translate_stencil_op(intel->state.Stencil->FailFunc[1]); + GLint dfop = intel_translate_stencil_op(intel->state.Stencil->ZFailFunc[1]); + GLint dpop = intel_translate_stencil_op(intel->state.Stencil->ZPassFunc[1]); + GLint ref = intel->state.Stencil->Ref[1] & 0xff; - i915->state.Ctx[I915_CTXREG_BFO] |= - (BFO_ENABLE_STENCIL_FUNCS | - BFO_ENABLE_STENCIL_TWO_SIDE | - BFO_ENABLE_STENCIL_REF | - BFO_STENCIL_TWO_SIDE | - (ref << BFO_STENCIL_REF_SHIFT) | - (test << BFO_STENCIL_TEST_FUNC_SHIFT) | - (fop << BFO_STENCIL_FAIL_SHIFT) | - (dfop << BFO_STENCIL_PASS_Z_FAIL_SHIFT) | - (dpop << BFO_STENCIL_PASS_Z_PASS_SHIFT)); + bfo = (_3DSTATE_BACKFACE_STENCIL_OPS | + BFO_ENABLE_STENCIL_FUNCS | + BFO_ENABLE_STENCIL_TWO_SIDE | + BFO_ENABLE_STENCIL_REF | + BFO_STENCIL_TWO_SIDE | + (ref << BFO_STENCIL_REF_SHIFT) | + (test << BFO_STENCIL_TEST_SHIFT) | + (fop << BFO_STENCIL_FAIL_SHIFT) | + (dfop << BFO_STENCIL_PASS_Z_FAIL_SHIFT) | + (dpop << BFO_STENCIL_PASS_Z_PASS_SHIFT)); } else { /* This actually disables two-side stencil: The bit set is a @@ -124,32 +128,35 @@ static void upload_BFO( struct i915_context *i915 ) * setting. Then there is a symbolic zero to show that we are * setting the flag to zero/off. */ - i915->state.Ctx[I915_CTXREG_BFO] |= (BFO_ENABLE_STENCIL_TWO_SIDE | - 0); + bfo = (_3DSTATE_BACKFACE_STENCIL_OPS | + BFO_ENABLE_STENCIL_TWO_SIDE | + 0); } + + BEGIN_BATCH(1,0); + OUT_BATCH(bfo); + ADVANCE_BATCH(); } -const struct i915_tracked_state i915_upload_BFO = { +const struct intel_tracked_state i915_upload_BFO = { .dirty = { .mesa = _NEW_STENCIL, .intel = 0, - .indirect = 0 + .extra = 0 }, - .update = upload_MODES4 + .update = upload_BFO }; /*********************************************************************** * BLENDCOLOR */ -static void upload_BLENDCOLOR( struct i915_context *i915 ) +static void upload_BLENDCOLOR( struct intel_context *intel ) { - struct i915_context *i915 = I915_CONTEXT(ctx); - /* _NEW_COLOR */ - if (ctx->Color.BlendEnabled) { - const GLfloat *color = ctx->Color.BlendColor; + if (intel->state.Color->BlendEnabled) { + const GLfloat *color = intel->state.Color->BlendColor; GLubyte r, g, b, a; UNCLAMPED_FLOAT_TO_UBYTE(r, color[RCOMP]); @@ -157,6 +164,8 @@ static void upload_BLENDCOLOR( struct i915_context *i915 ) UNCLAMPED_FLOAT_TO_UBYTE(b, color[BCOMP]); UNCLAMPED_FLOAT_TO_UBYTE(a, color[ACOMP]); + /* Only needs to be sent when blend is enabled + */ BEGIN_BATCH(2, 0); OUT_BATCH(_3DSTATE_CONST_BLEND_COLOR_CMD); OUT_BATCH( (a << 24) | (r << 16) | (g << 8) | b ); @@ -164,11 +173,11 @@ static void upload_BLENDCOLOR( struct i915_context *i915 ) } } -const struct i915_tracked_state i915_upload_BLENDCOLOR = { +const struct intel_tracked_state i915_upload_BLENDCOLOR = { .dirty = { .mesa = _NEW_COLOR, - .i915 = 0, - .cache = 0 + .intel = 0, + .extra = 0 }, .update = upload_BLENDCOLOR }; @@ -177,22 +186,19 @@ const struct i915_tracked_state i915_upload_BLENDCOLOR = { /*********************************************************************** * IAB: Independent Alpha Blend */ -static void upload_IAB( struct i915_context *i915 ) +static void upload_IAB( struct intel_context *intel ) { - struct i915_context *i915 = I915_CONTEXT(ctx); - - - i915->state.Ctx[I915_CTXREG_IAB] = - - - if (ctx->Color.BlendEnabled) { - - GLuint eqRGB = ctx->Color.BlendEquationRGB; - GLuint eqA = ctx->Color.BlendEquationA; - GLuint srcRGB = ctx->Color.BlendSrcRGB; - GLuint dstRGB = ctx->Color.BlendDstRGB; - GLuint srcA = ctx->Color.BlendSrcA; - GLuint dstA = ctx->Color.BlendDstA; + if (intel->state.Color->BlendEnabled) { + GLuint iab = (_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD | + IAB_MODIFY_ENABLE | + 0); + + GLuint eqRGB = intel->state.Color->BlendEquationRGB; + GLuint eqA = intel->state.Color->BlendEquationA; + GLuint srcRGB = intel->state.Color->BlendSrcRGB; + GLuint dstRGB = intel->state.Color->BlendDstRGB; + GLuint srcA = intel->state.Color->BlendSrcA; + GLuint dstA = intel->state.Color->BlendDstA; if (srcA != srcRGB || dstA != dstRGB || @@ -202,28 +208,26 @@ static void upload_IAB( struct i915_context *i915 ) srcA = dstA = GL_ONE; } - BEGIN_BATCH(1, 0); - - OUT_BATCH( _3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD | - IAB_MODIFY_ENABLE | - IAB_MODIFY_FUNC | - IAB_MODIFY_SRC_FACTOR | - IAB_MODIFY_DST_FACTOR | - SRC_ABLND_FACT(intel_translate_blend_factor(srcA)) | - DST_ABLND_FACT(intel_translate_blend_factor(dstA)) | - (translate_blend_equation(eqA) << IAB_FUNC_SHIFT) | - IAB_ENABLE ); - - ADVANCE_BATCH(); + iab |= (IAB_MODIFY_FUNC | + IAB_MODIFY_SRC_FACTOR | + IAB_MODIFY_DST_FACTOR | + SRC_ABLND_FACT(intel_translate_blend_factor(srcA)) | + DST_ABLND_FACT(intel_translate_blend_factor(dstA)) | + (i915_translate_blend_equation(eqA) << IAB_FUNC_SHIFT) | + IAB_ENABLE ); } + + BEGIN_BATCH(1, 0); + OUT_BATCH( iab ); + ADVANCE_BATCH(); } } -const struct i915_tracked_state i915_upload_IAB = { +const struct intel_tracked_state i915_upload_IAB = { .dirty = { .mesa = _NEW_COLOR, - .i915 = 0, - .cache = 0 + .intel = 0, + .extra = 0 }, .update = upload_IAB }; @@ -233,32 +237,11 @@ const struct i915_tracked_state i915_upload_IAB = { * Depthbuffer - currently constant, but rotation would change that. */ -static void emit_buffers( struct i915_context *i915 ) -{ - if (INTEL_DEBUG & DEBUG_STATE) - fprintf(stderr, "I915_UPLOAD_BUFFERS:\n"); - BEGIN_BATCH(I915_DEST_SETUP_SIZE + 2, 0); - OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]); - OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]); - OUT_RELOC(state->draw_region->buffer, - DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE, - DRM_BO_MASK_MEM | DRM_BO_FLAG_WRITE, - state->draw_region->draw_offset); - - if (state->depth_region) { - OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR0]); - OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR1]); - } - OUT_BATCH(state->Buffer[I915_DESTREG_DV1]); - ADVANCE_BATCH(); -} - -static void upload_buffers(struct i915_context *i915) +static void upload_buffers(struct intel_context *intel) { - struct intel_region *color_region = state->draw_region; - struct intel_region *depth_region = state->depth_region; - GLuint value; + struct intel_region *color_region = intel->state.draw_region; + struct intel_region *depth_region = intel->state.depth_region; if (color_region) { BEGIN_BATCH(4, 0); @@ -266,10 +249,10 @@ static void upload_buffers(struct i915_context *i915) OUT_BATCH( BUF_3D_ID_COLOR_BACK | BUF_3D_PITCH(color_region->pitch * color_region->cpp) | BUF_3D_USE_FENCE); - OUT_RELOC(state->draw_region->buffer, + OUT_RELOC(intel->state.draw_region->buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE, DRM_BO_MASK_MEM | DRM_BO_FLAG_WRITE, - state->draw_region->draw_offset); + intel->state.draw_region->draw_offset); ADVANCE_BATCH(); } @@ -279,10 +262,10 @@ static void upload_buffers(struct i915_context *i915) OUT_BATCH( BUF_3D_ID_DEPTH | BUF_3D_PITCH(depth_region->pitch * depth_region->cpp) | BUF_3D_USE_FENCE ); - OUT_RELOC(state->depth_region->buffer, + OUT_RELOC(intel->state.depth_region->buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE, DRM_BO_MASK_MEM | DRM_BO_FLAG_WRITE, - state->depth_region->draw_offset); + intel->state.depth_region->draw_offset); ADVANCE_BATCH(); } @@ -307,11 +290,11 @@ static void upload_buffers(struct i915_context *i915) ADVANCE_BATCH(); } -const struct i915_tracked_state i915_upload_buffers = { +const struct intel_tracked_state i915_upload_buffers = { .dirty = { .mesa = 0, - .i915 = I915_NEW_CBUF | I915_NEW_ZBUF, - .cache = 0 + .intel = INTEL_NEW_CBUF | INTEL_NEW_ZBUF | INTEL_NEW_FENCE, + .extra = 0 }, .update = upload_buffers }; @@ -323,205 +306,102 @@ const struct i915_tracked_state i915_upload_buffers = { * * The i915 supports a 4x4 stipple natively, GL wants 32x32. * Fortunately stipple is usually a repeating pattern. + * + * XXX: does stipple pattern need to be adjusted according to + * the window position? + * + * XXX: possibly need workaround for conform paths test. */ -static void upload_stipple( struct i915_context *i915 ) -{ - struct i915_context *i915 = I915_CONTEXT(ctx); - const GLubyte *m = mask; - GLubyte p[4]; - int i, j, k; - i915->state.Stipple[I915_STPREG_ST1] = 0; +static void upload_stipple( struct intel_context *intel ) +{ + GLuint st0 = _3DSTATE_STIPPLE; + GLuint st1 = 0; - if (ctx->Polygon.StippleFlag && - i915->intel.reduced_primitive == GL_TRIANGLES) - { + GLboolean hw_stipple_fallback = 0; - GLuint newMask; - - p[0] = mask[12] & 0xf; - p[0] |= p[0] << 4; - p[1] = mask[8] & 0xf; - p[1] |= p[1] << 4; - p[2] = mask[4] & 0xf; - p[2] |= p[2] << 4; - p[3] = mask[0] & 0xf; - p[3] |= p[3] << 4; - - for (k = 0; k < 8; k++) - for (j = 3; j >= 0; j--) - for (i = 0; i < 4; i++, m++) - if (*m != p[j]) { - i915->intel.hw_stipple = 0; - return; - } - - newMask = (((p[0] & 0xf) << 0) | - ((p[1] & 0xf) << 4) | - ((p[2] & 0xf) << 8) | ((p[3] & 0xf) << 12)); - - - if (newMask == 0xffff || newMask == 0x0) { - /* this is needed to make conform pass */ - i915->intel.hw_stipple = 0; - return; - } + /* _NEW_POLYGON, INTEL_NEW_REDUCED_PRIMITIVE + */ + if (intel->state.Polygon->StippleFlag && + intel->reduced_primitive == GL_TRIANGLES) { - i915->state.Stipple[I915_STPREG_ST0] = _3DSTATE_STIPPLE; if (active) { - I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE); - i915->state.Stipple[I915_STPREG_ST1] &= ~ST1_ENABLE; - } + /* _NEW_POLYGONSTIPPLE + */ + const GLubyte *mask = (const GLubyte *)intel->state.PolygonStipple; + GLubyte p[4]; + GLint i, j, k; + + p[0] = mask[12] & 0xf; + p[0] |= p[0] << 4; + p[1] = mask[8] & 0xf; + p[1] |= p[1] << 4; + p[2] = mask[4] & 0xf; + p[2] |= p[2] << 4; + p[3] = mask[0] & 0xf; + p[3] |= p[3] << 4; + + st1 |= ST1_ENABLE; + + for (k = 0; k < 8; k++) { + for (j = 3; j >= 0; j--) { + for (i = 0; i < 4; i++, mask++) { + if (*mask != p[j]) { + hw_stipple_fallback = 1; + st1 &= ~ST1_ENABLE; + } + } + } + } + st1 |= (((p[0] & 0xf) << 0) | + ((p[1] & 0xf) << 4) | + ((p[2] & 0xf) << 8) | + ((p[3] & 0xf) << 12)); + } - i915->state.Stipple[I915_STPREG_ST1] &= ~0xffff; - i915->state.Stipple[I915_STPREG_ST1] |= newMask; - i915->intel.hw_stipple = 1; + assert(!hw_stipple_fallback); /* TODO */ - if (active) - i915->state.Stipple[I915_STPREG_ST1] |= ST1_ENABLE; + BEGIN_BATCH(2, 0); + OUT_BATCH(st0); + OUT_BATCH(st1); + ADVANCE_BATCH(); } -const struct i915_tracked_state i915_polygon_stipple = { +const struct intel_tracked_state i915_upload_stipple = { .dirty = { - .mesa = _NEW_POLYGONSTIPPLE, - .i915 = 0, - .cache = 0 + .mesa = _NEW_POLYGONSTIPPLE, _NEW_POLYGON, + .intel = INTEL_NEW_REDUCED_PRIMITIVE, + .extra = 0 }, - .update = upload_polygon_stipple + .update = upload_stipple }; /*********************************************************************** - * Misc invarient state packets + * Scissor. */ -static void upload_invarient_state( struct i915_context *i915 ) +static void upload_scissor( struct intel_context *intel ) { - static GLuint invarient_state[] = { - - (_3DSTATE_AA_CMD | - AA_LINE_ECAAR_WIDTH_ENABLE | - AA_LINE_ECAAR_WIDTH_1_0 | - AA_LINE_REGION_WIDTH_ENABLE | - AA_LINE_REGION_WIDTH_1_0), - - /* Could use these to reduce the size of vertices when the incoming - * array is constant. - */ - (_3DSTATE_DFLT_DIFFUSE_CMD), - (0), - - (_3DSTATE_DFLT_SPEC_CMD), - (0), - - (_3DSTATE_DFLT_Z_CMD), - (0), - - /* We support texture crossbar via the fragment shader, rather than - * with this mechanism. - */ - (_3DSTATE_COORD_SET_BINDINGS | - CSB_TCB(0, 0) | - CSB_TCB(1, 1) | - CSB_TCB(2, 2) | - CSB_TCB(3, 3) | - CSB_TCB(4, 4) | - CSB_TCB(5, 5) | - CSB_TCB(6, 6) | - CSB_TCB(7, 7)), - - /* Setup OpenGL rasterization state: - */ - (_3DSTATE_RASTER_RULES_CMD | - ENABLE_POINT_RASTER_RULE | - OGL_POINT_RASTER_RULE | - ENABLE_LINE_STRIP_PROVOKE_VRTX | - ENABLE_TRI_FAN_PROVOKE_VRTX | - LINE_STRIP_PROVOKE_VRTX(1) | - TRI_FAN_PROVOKE_VRTX(2) | - ENABLE_TEXKILL_3D_4D | - TEXKILL_4D), - - /* Need to initialize this to zero. - */ - (_3DSTATE_LOAD_STATE_IMMEDIATE_1 | - I1_LOAD_S(3) | - (1)), - (0), - - /* For private depth buffers but shared color buffers, eg - * front-buffer rendering with a private depthbuffer. We don't do - * this. - */ - (_3DSTATE_DEPTH_SUBRECT_DISABLE), - - /* Disable indirect state for now. - */ - (_3DSTATE_LOAD_INDIRECT | 0), - (0), - }; - - - BATCH_LOCALS; - - BEGIN_BATCH(sizeof(invarient_state)/4, 0); - - for (i = 0; i < sizeof(invarient_state)/4; i++) - OUT_BATCH( invarient_state[i] ); - - ADVANCE_BATCH(); -} - -const struct i915_tracked_state i915_invarient_state = { - .dirty = { - .mesa = 0, - .i915 = I915_NEW_CONTEXT, - .cache = 0 - }, - .update = upload_invarient_state -}; - - - - - -static void check_fallback() -{ - if (ctx->Color._LogicOpEnabled && i915->intel.intelScreen->cpp == 2) /* XXX FBO fix */ - fallback = 1; - - if (ctx->Stencil.Enabled) { - if (!ctx->DrawBuffer) - return GL_TRUE; - - struct intel_renderbuffer *irbStencil - = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL); - - if (!irbStencil || !irbStencil->region) - return GL_TRUE; - } - - -} - - -static void update_scissor() -{ - struct i915_context *i915 = I915_CONTEXT(ctx); - - if (ctx->Scissor.Enabled && ctx->DrawBuffer) { - int x1, y1, x2, y2; - - DBG("%s %d,%d %dx%d\n", __FUNCTION__, x, y, w, h); + /* _NEW_SCISSOR, _NEW_BUFFERS + */ + if (intel->state.Scissor->Enabled && + intel->state.DrawBuffer) { + + GLint x = intel->state.Scissor->X; + GLint y = intel->state.Scissor->Y; + GLint w = intel->state.Scissor->Width; + GLint h = intel->state.Scissor->Height; + + GLint x1, y1, x2, y2; - if (ctx->DrawBuffer->Name == 0) { + if (intel->state.DrawBuffer->Name == 0) { x1 = x; - y1 = ctx->DrawBuffer->Height - (y + h); + y1 = intel->state.DrawBuffer->Height - (y + h); x2 = x + w - 1; y2 = y1 + h - 1; - DBG("%s %d..%d,%d..%d (inverted)\n", __FUNCTION__, x1, x2, y1, y2); } else { /* FBO - not inverted @@ -530,31 +410,33 @@ static void update_scissor() y1 = y; x2 = x + w - 1; y2 = y + h - 1; - DBG("%s %d..%d,%d..%d (not inverted)\n", __FUNCTION__, x1, x2, y1, y2); } - x1 = CLAMP(x1, 0, ctx->DrawBuffer->Width - 1); - y1 = CLAMP(y1, 0, ctx->DrawBuffer->Height - 1); - x2 = CLAMP(x2, 0, ctx->DrawBuffer->Width - 1); - y2 = CLAMP(y2, 0, ctx->DrawBuffer->Height - 1); - - DBG("%s %d..%d,%d..%d (clamped)\n", __FUNCTION__, x1, x2, y1, y2); - - I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS); - i915->state.Buffer[I915_DESTREG_SR0] = _3DSTATE_SCISSOR_RECT_0_CMD; - i915->state.Buffer[I915_DESTREG_SR1] = (y1 << 16) | (x1 & 0xffff); - i915->state.Buffer[I915_DESTREG_SR2] = (y2 << 16) | (x2 & 0xffff); - + x1 = CLAMP(x1, 0, intel->state.DrawBuffer->Width - 1); + y1 = CLAMP(y1, 0, intel->state.DrawBuffer->Height - 1); + x2 = CLAMP(x2, 0, intel->state.DrawBuffer->Width - 1); + y2 = CLAMP(y2, 0, intel->state.DrawBuffer->Height - 1); - i915->state.Buffer[I915_DESTREG_SENABLE] = - (_3DSTATE_SCISSOR_ENABLE_CMD | ENABLE_SCISSOR_RECT); + BEGIN_BATCH(4, 0); + OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | ENABLE_SCISSOR_RECT); + OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD); + OUT_BATCH((y1 << 16) | (x1 & 0xffff)); + OUT_BATCH((y2 << 16) | (x2 & 0xffff)); + ADVANCE_BATCH(); + } + else { + BEGIN_BATCH(1, 0); + OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT); + ADVANCE_BATCH(); } - else - i915->state.Buffer[I915_DESTREG_SENABLE] = - (_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT); - } - - +const struct intel_tracked_state i915_upload_scissor = { + .dirty = { + .mesa = _NEW_SCISSOR | _NEW_BUFFERS, + .intel = 0, + .extra = 0 + }, + .update = upload_scissor +}; diff --git a/src/mesa/drivers/dri/i915tex/i915_state_sampler.c b/src/mesa/drivers/dri/i915tex/i915_state_sampler.c index 09d28a6bc1..4ddb534b01 100644 --- a/src/mesa/drivers/dri/i915tex/i915_state_sampler.c +++ b/src/mesa/drivers/dri/i915tex/i915_state_sampler.c @@ -28,59 +28,18 @@ #include "mtypes.h" #include "enums.h" #include "texformat.h" +#include "macros.h" #include "dri_bufmgr.h" #include "intel_mipmap_tree.h" #include "intel_tex.h" +#include "intel_batchbuffer.h" +#include "intel_state_inlines.h" #include "i915_context.h" #include "i915_reg.h" -static GLuint -translate_texture_format(GLuint mesa_format) -{ - switch (mesa_format) { - case MESA_FORMAT_L8: - return MAPSURF_8BIT | MT_8BIT_L8; - case MESA_FORMAT_I8: - return MAPSURF_8BIT | MT_8BIT_I8; - case MESA_FORMAT_A8: - return MAPSURF_8BIT | MT_8BIT_A8; - case MESA_FORMAT_AL88: - return MAPSURF_16BIT | MT_16BIT_AY88; - case MESA_FORMAT_RGB565: - return MAPSURF_16BIT | MT_16BIT_RGB565; - case MESA_FORMAT_ARGB1555: - return MAPSURF_16BIT | MT_16BIT_ARGB1555; - case MESA_FORMAT_ARGB4444: - return MAPSURF_16BIT | MT_16BIT_ARGB4444; - case MESA_FORMAT_ARGB8888: - return MAPSURF_32BIT | MT_32BIT_ARGB8888; - case MESA_FORMAT_YCBCR_REV: - return (MAPSURF_422 | MT_422_YCRCB_NORMAL); - case MESA_FORMAT_YCBCR: - return (MAPSURF_422 | MT_422_YCRCB_SWAPY); - case MESA_FORMAT_RGB_FXT1: - case MESA_FORMAT_RGBA_FXT1: - return (MAPSURF_COMPRESSED | MT_COMPRESS_FXT1); - case MESA_FORMAT_Z16: - return (MAPSURF_16BIT | MT_16BIT_L16); - case MESA_FORMAT_RGBA_DXT1: - case MESA_FORMAT_RGB_DXT1: - return (MAPSURF_COMPRESSED | MT_COMPRESS_DXT1); - case MESA_FORMAT_RGBA_DXT3: - return (MAPSURF_COMPRESSED | MT_COMPRESS_DXT2_3); - case MESA_FORMAT_RGBA_DXT5: - return (MAPSURF_COMPRESSED | MT_COMPRESS_DXT4_5); - case MESA_FORMAT_Z24_S8: - return (MAPSURF_32BIT | MT_32BIT_xL824); - default: - fprintf(stderr, "%s: bad image format %x\n", __FUNCTION__, mesa_format); - abort(); - return 0; - } -} @@ -114,24 +73,18 @@ translate_wrap_mode(GLenum wrap) * efficient, but this has gotten complex enough that we need * something which is understandable and reliable. */ -static GLboolean -i915_update_sampler(struct intel_context *intel, GLuint unit) +static void update_sampler(struct intel_context *intel, + GLuint unit, + GLuint *state ) { - GLcontext *ctx = &intel->ctx; - struct i915_context *i915 = i915_context(ctx); - struct gl_texture_unit *tUnit = &ctx->Texture.Unit[unit]; + struct gl_texture_unit *tUnit = &intel->state.Texture->Unit[unit]; struct gl_texture_object *tObj = tUnit->_Current; struct intel_texture_object *intelObj = intel_texture_object(tObj); - struct gl_texture_image *firstImage; - GLuint *state = i915->state.Tex[unit]; - - memset(state, 0, sizeof(state)); - - /* Get first image here, since intelObj->firstLevel will get set in - * the intel_finalize_mipmap_tree() call above. + /* Need to do this after updating the maps, which call the + * intel_finalize_mipmap_tree and hence can update firstLevel: */ - firstImage = tObj->Image[0][intelObj->firstLevel]; + struct gl_texture_image *firstImage = tObj->Image[0][intelObj->firstLevel]; { @@ -189,7 +142,7 @@ i915_update_sampler(struct intel_context *intel, GLuint unit) GLint b = (int) ((tObj->LodBias + tUnit->LodBias) * 16.0); b = CLAMP(b, -256, 255); - state[I915_TEXREG_SS2] |= ((b << SS2_LOD_BIAS_SHIFT) & SS2_LOD_BIAS_MASK); + state[0] |= ((b << SS2_LOD_BIAS_SHIFT) & SS2_LOD_BIAS_MASK); } @@ -197,24 +150,23 @@ i915_update_sampler(struct intel_context *intel, GLuint unit) */ if (firstImage->TexFormat->MesaFormat == MESA_FORMAT_YCBCR || firstImage->TexFormat->MesaFormat == MESA_FORMAT_YCBCR_REV) - state[I915_TEXREG_SS2] |= SS2_COLORSPACE_CONVERSION; + state[0] |= SS2_COLORSPACE_CONVERSION; /* Shadow: */ if (tObj->CompareMode == GL_COMPARE_R_TO_TEXTURE_ARB && tObj->Target != GL_TEXTURE_3D) { - state[I915_TEXREG_SS2] |= - (SS2_SHADOW_ENABLE | - intel_translate_compare_func(tObj->CompareFunc)); + state[0] |= (SS2_SHADOW_ENABLE | + intel_translate_compare_func(tObj->CompareFunc)); minFilt = FILTER_4X4_FLAT; magFilt = FILTER_4X4_FLAT; } - state[I915_TEXREG_SS2] |= ((minFilt << SS2_MIN_FILTER_SHIFT) | - (mipFilt << SS2_MIP_FILTER_SHIFT) | - (magFilt << SS2_MAG_FILTER_SHIFT)); + state[0] |= ((minFilt << SS2_MIN_FILTER_SHIFT) | + (mipFilt << SS2_MIP_FILTER_SHIFT) | + (magFilt << SS2_MAG_FILTER_SHIFT)); } { @@ -240,85 +192,63 @@ i915_update_sampler(struct intel_context *intel, GLuint unit) wt == GL_CLAMP_TO_BORDER || wr == GL_CLAMP_TO_BORDER)) { -/* return GL_FALSE; */ - sampler->fallback = true; + if (intel->strict_conformance) { + assert(0); +/* sampler->fallback = true; */ + /* TODO */ + } } - - /* Or some field in tObj? */ - if (ctx->Texture.Unit[i]._ReallyEnabled == TEXTURE_RECT_BIT) - ss3 = SS3_NORMALIZED_COORDS; - else - ss3 = 0; - - - state[I915_TEXREG_SS3] = ss3; /* SS3_NORMALIZED_COORDS */ - - state[I915_TEXREG_SS3] |= + state[1] = ((translate_wrap_mode(ws) << SS3_TCX_ADDR_MODE_SHIFT) | (translate_wrap_mode(wt) << SS3_TCY_ADDR_MODE_SHIFT) | - (translate_wrap_mode(wr) << SS3_TCZ_ADDR_MODE_SHIFT)); + (translate_wrap_mode(wr) << SS3_TCZ_ADDR_MODE_SHIFT) | + (unit << SS3_TEXTUREMAP_INDEX_SHIFT)); - state[I915_TEXREG_SS3] |= (unit << SS3_TEXTUREMAP_INDEX_SHIFT); + /* Or some field in tObj? */ + if (intel->state.Texture->Unit[unit]._ReallyEnabled == TEXTURE_RECT_BIT) + state[1] |= SS3_NORMALIZED_COORDS; } - - state[I915_TEXREG_SS4] = INTEL_PACKCOLOR8888(tObj->_BorderChan[0], - tObj->_BorderChan[1], - tObj->_BorderChan[2], - tObj->_BorderChan[3]); - - - - I915_ACTIVESTATE(i915, I915_UPLOAD_TEX(unit), GL_TRUE); - /* memcmp was already disabled, but definitely won't work as the - * region might now change and that wouldn't be detected: - */ - I915_STATECHANGE(i915, I915_UPLOAD_TEX(unit)); - - - DBG(TEXTURE, "state[I915_TEXREG_SS2] = 0x%x\n", state[I915_TEXREG_SS2]); - DBG(TEXTURE, "state[I915_TEXREG_SS3] = 0x%x\n", state[I915_TEXREG_SS3]); - DBG(TEXTURE, "state[I915_TEXREG_SS4] = 0x%x\n", state[I915_TEXREG_SS4]); - - return GL_TRUE; + state[2] = INTEL_PACKCOLOR8888(tObj->_BorderChan[0], + tObj->_BorderChan[1], + tObj->_BorderChan[2], + tObj->_BorderChan[3]); } - - - -void -i915_tex_state_emit() +static void upload_samplers( struct intel_context *intel ) { - int nr = 0; - - for (i = 0; i < I915_TEX_UNITS; i++) - if (dirty & I915_UPLOAD_TEX(i)) - nr++; - - for (i = 0; i < I915_TEX_UNITS; i++) - update_sampler( i915, i ); - + GLint i, dirty = 0, nr = 0; + GLuint state[I915_TEX_UNITS][3]; + + for (i = 0; i < I915_TEX_UNITS; i++) { + if (intel->state.Texture->Unit[i]._ReallyEnabled) { + update_sampler( intel, i, state[i] ); + nr++; + dirty |= (1<<i); + } + } - BEGIN_BATCH(2 + nr * 3, 0); - OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * nr)); - OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT); - for (i = 0; i < I915_TEX_UNITS; i++) - if (dirty & I915_UPLOAD_TEX(i)) { - OUT_BATCH(state->Tex[i][I915_TEXREG_SS2]); - OUT_BATCH(state->Tex[i][I915_TEXREG_SS3]); - OUT_BATCH(state->Tex[i][I915_TEXREG_SS4]); - } - ADVANCE_BATCH(); + BEGIN_BATCH(2 + nr * 3, 0); + OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * nr)); + OUT_BATCH(dirty); + for (i = 0; i < I915_TEX_UNITS; i++) { + if (intel->state.Texture->Unit[i]._ReallyEnabled) { + OUT_BATCH(state[i][0]); + OUT_BATCH(state[i][1]); + OUT_BATCH(state[i][2]); + } + } + ADVANCE_BATCH(); } -const struct i915_tracked_state i915_upload_samplers = { +const struct intel_tracked_state i915_upload_samplers = { .dirty = { - .mesa = (_NEW_TEXTURE), + .mesa = _NEW_TEXTURE, .intel = 0, - .indirect = 0 + .extra = 0 }, .update = upload_samplers }; diff --git a/src/mesa/drivers/dri/i915tex/i915_tex_layout.c b/src/mesa/drivers/dri/i915tex/i915_tex_layout.c index 333fefef85..c83bc73b12 100644 --- a/src/mesa/drivers/dri/i915tex/i915_tex_layout.c +++ b/src/mesa/drivers/dri/i915tex/i915_tex_layout.c @@ -36,21 +36,23 @@ #define FILE_DEBUG_FLAG DEBUG_TEXTURE -static GLint initial_offsets[6][2] = { {0, 0}, -{0, 2}, -{1, 0}, -{1, 2}, -{1, 1}, -{1, 3} +static GLint initial_offsets[6][2] = { + {0, 0}, + {0, 2}, + {1, 0}, + {1, 2}, + {1, 1}, + {1, 3} }; -static GLint step_offsets[6][2] = { {0, 2}, -{0, 2}, -{-1, 2}, -{-1, 2}, -{-1, 1}, -{-1, 1} +static GLint step_offsets[6][2] = { + {0, 2}, + {0, 2}, + {-1, 2}, + {-1, 2}, + {-1, 1}, + {-1, 1} }; GLboolean diff --git a/src/mesa/drivers/dri/i915tex/i915_vtbl.c b/src/mesa/drivers/dri/i915tex/i915_vtbl.c index 2703ca8d9f..35f8a80fb6 100644 --- a/src/mesa/drivers/dri/i915tex/i915_vtbl.c +++ b/src/mesa/drivers/dri/i915tex/i915_vtbl.c @@ -43,95 +43,17 @@ #include "i915_reg.h" #include "i915_context.h" -static void -i915_render_start(struct intel_context *intel) -{ - struct i915_context *i915 = i915_context(&intel->ctx); - - i915ValidateFragmentProgram(i915); -} - - -static void -i915_reduced_primitive_state(struct intel_context *intel, GLenum rprim) -{ -} - static void -i915_emit_invarient_state(struct intel_context *intel) -{ -} - - - - -/* Push the state into the sarea and/or texture memory. - */ -static void -i915_emit_state(struct intel_context *intel) -{ -} - -static void i915_destroy_context(struct intel_context *intel) { _tnl_free_vertices(&intel->ctx); } -/** - * Set the drawing regions for the color and depth/stencil buffers. - * This involves setting the pitch, cpp and buffer ID/location. - * Also set pixel format for color and Z rendering - * Used for setting both regular and meta state. - */ -void -i915_state_draw_region(struct intel_context *intel, - struct i915_hw_state *state, - struct intel_region *color_region, - struct intel_region *depth_region) -{ - struct i915_context *i915 = i915_context(&intel->ctx); - GLuint value; - - ASSERT(state == &i915->state || state == &i915->meta); - - if (state->draw_region != color_region) { - intel_region_release(&state->draw_region); - intel_region_reference(&state->draw_region, color_region); - } - if (state->depth_region != depth_region) { - intel_region_release(&state->depth_region); - intel_region_reference(&state->depth_region, depth_region); - } - - /* Everything else will get done later: - */ - I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS); -} - - -static void -i915_set_draw_region(struct intel_context *intel, - struct intel_region *color_region, - struct intel_region *depth_region) -{ - struct i915_context *i915 = i915_context(&intel->ctx); - i915_state_draw_region(intel, &i915->state, color_region, depth_region); -} - - - -static void -i915_lost_hardware(struct intel_context *intel) -{ - struct i915_context *i915 = i915_context(&intel->ctx); - i915->state.emitted = 0; -} static GLuint i915_flush_cmd(void) @@ -139,26 +61,10 @@ i915_flush_cmd(void) return MI_FLUSH | FLUSH_MAP_CACHE; } -static void -i915_assert_not_dirty( struct intel_context *intel ) -{ - struct i915_context *i915 = i915_context(&intel->ctx); - struct i915_hw_state *state = i915->current; - GLuint dirty = get_dirty(state); - assert(!dirty); -} - void i915InitVtbl(struct i915_context *i915) { i915->intel.vtbl.destroy = i915_destroy_context; - i915->intel.vtbl.emit_state = i915_emit_state; - i915->intel.vtbl.lost_hardware = i915_lost_hardware; - i915->intel.vtbl.reduced_primitive_state = i915_reduced_primitive_state; - i915->intel.vtbl.render_start = i915_render_start; - i915->intel.vtbl.set_draw_region = i915_set_draw_region; - i915->intel.vtbl.update_texture_state = i915UpdateTextureState; i915->intel.vtbl.flush_cmd = i915_flush_cmd; - i915->intel.vtbl.assert_not_dirty = i915_assert_not_dirty; } diff --git a/src/mesa/drivers/dri/i915tex/intel_batchbuffer.c b/src/mesa/drivers/dri/i915tex/intel_batchbuffer.c index 309ecf926d..9f6d82eef4 100644 --- a/src/mesa/drivers/dri/i915tex/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/i915tex/intel_batchbuffer.c @@ -28,6 +28,7 @@ #include "intel_batchbuffer.h" #include "intel_ioctl.h" #include "intel_idx_render.h" +#include "intel_reg.h" /* Relocations in kernel space: * - pass dma buffer seperately @@ -243,7 +244,10 @@ do_flush_locked(struct intel_batchbuffer *batch, sched_yield(); LOCK_HARDWARE(intel); } - intel->vtbl.lost_hardware(intel); + /* This sucks: + */ + intel->state.dirty.intel |= ~0; + intel->state.dirty.mesa |= ~0; } } diff --git a/src/mesa/drivers/dri/i915tex/intel_batchbuffer.h b/src/mesa/drivers/dri/i915tex/intel_batchbuffer.h index 916bcaed5e..84c3e83ba9 100644 --- a/src/mesa/drivers/dri/i915tex/intel_batchbuffer.h +++ b/src/mesa/drivers/dri/i915tex/intel_batchbuffer.h @@ -116,6 +116,12 @@ intel_batchbuffer_require_space(struct intel_batchbuffer *batch, #define OUT_BATCH(d) intel_batchbuffer_emit_dword(intel->batch, d) +#define OUT_BATCH_F(fl) do { \ + fi_type fi; \ + fi.f = fl; \ + intel_batchbuffer_emit_dword(intel->batch, fi.i); \ +} while (0) + #define OUT_RELOC(buf,flags,mask,delta) do { \ assert((delta) >= 0); \ intel_batchbuffer_emit_reloc(intel->batch, buf, flags, mask, delta); \ diff --git a/src/mesa/drivers/dri/i915tex/intel_buffers.c b/src/mesa/drivers/dri/i915tex/intel_buffers.c index 1ded0b5417..039632fcce 100644 --- a/src/mesa/drivers/dri/i915tex/intel_buffers.c +++ b/src/mesa/drivers/dri/i915tex/intel_buffers.c @@ -34,6 +34,7 @@ #include "intel_tris.h" #include "intel_regions.h" #include "intel_batchbuffer.h" +#include "intel_metaops.h" #include "context.h" #include "utils.h" #include "drirenderbuffer.h" @@ -242,12 +243,8 @@ intelWindowMoved(struct intel_context *intel) intel->vblank_flags &= ~VBLANK_FLAG_SECONDARY; } - /* Update hardware scissor */ - ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y, - ctx->Scissor.Width, ctx->Scissor.Height); - - /* Re-calculate viewport related state */ - ctx->Driver.DepthRange( ctx, ctx->Viewport.Near, ctx->Viewport.Far ); + /* Raise a state flag */ + intel->state.dirty.intel |= INTEL_NEW_WINDOW_DIMENSIONS; } @@ -271,7 +268,7 @@ intelClearWithTris(struct intel_context *intel, GLbitfield mask) GLint cx, cy, cw, ch; GLuint buf; - intel->vtbl.install_meta_state(intel); + intel_install_meta_state(intel); /* Get clear bounds after locking */ cx = ctx->DrawBuffer->_Xmin; @@ -297,29 +294,33 @@ intelClearWithTris(struct intel_context *intel, GLbitfield mask) const GLuint clearColor = (backRegion && backRegion->cpp == 4) ? intel->ClearColor8888 : intel->ClearColor565; - intel->vtbl.meta_draw_region(intel, backRegion, depthRegion); + intel_meta_draw_region(intel, backRegion, depthRegion); if (mask & BUFFER_BIT_BACK_LEFT) - intel->vtbl.meta_color_mask(intel, GL_TRUE); + intel_meta_color_mask(intel, GL_TRUE); else - intel->vtbl.meta_color_mask(intel, GL_FALSE); + intel_meta_color_mask(intel, GL_FALSE); if (mask & BUFFER_BIT_STENCIL) - intel->vtbl.meta_stencil_replace(intel, + intel_meta_stencil_replace(intel, intel->ctx.Stencil.WriteMask[0], intel->ctx.Stencil.Clear); else - intel->vtbl.meta_no_stencil_write(intel); + intel_meta_no_stencil_write(intel); if (mask & BUFFER_BIT_DEPTH) - intel->vtbl.meta_depth_replace(intel); + intel_meta_depth_replace(intel); else - intel->vtbl.meta_no_depth_write(intel); + intel_meta_no_depth_write(intel); /* XXX: Using INTEL_BATCH_NO_CLIPRECTS here is dangerous as the * drawing origin may not be correctly emitted. */ - intel_meta_draw_quad(intel, clear.x1, clear.x2, clear.y1, clear.y2, intel->ctx.Depth.Clear, clearColor, 0, 0, 0, 0); /* texcoords */ + intel_meta_draw_quad(intel, + clear.x1, clear.x2, + clear.y1, clear.y2, + intel->ctx.Depth.Clear, + clearColor, 0, 0, 0, 0); /* texcoords */ mask &= ~(BUFFER_BIT_BACK_LEFT | BUFFER_BIT_STENCIL | BUFFER_BIT_DEPTH); @@ -337,10 +338,10 @@ intelClearWithTris(struct intel_context *intel, GLbitfield mask) ASSERT(irbColor); - intel->vtbl.meta_no_depth_write(intel); - intel->vtbl.meta_no_stencil_write(intel); - intel->vtbl.meta_color_mask(intel, GL_TRUE); - intel->vtbl.meta_draw_region(intel, irbColor->region, NULL); + intel_meta_no_depth_write(intel); + intel_meta_no_stencil_write(intel); + intel_meta_color_mask(intel, GL_TRUE); + intel_meta_draw_region(intel, irbColor->region, NULL); /* XXX: Using INTEL_BATCH_NO_CLIPRECTS here is dangerous as the * drawing origin may not be correctly emitted. @@ -352,7 +353,7 @@ intelClearWithTris(struct intel_context *intel, GLbitfield mask) } } - intel->vtbl.leave_meta_state(intel); + intel_leave_meta_state(intel); intel_batchbuffer_flush(intel->batch); } UNLOCK_HARDWARE(intel); @@ -394,11 +395,11 @@ intelRotateWindow(struct intel_context *intel, return; } - intel->vtbl.install_meta_state(intel); + intel_install_meta_state(intel); - intel->vtbl.meta_no_depth_write(intel); - intel->vtbl.meta_no_stencil_write(intel); - intel->vtbl.meta_color_mask(intel, GL_FALSE); + intel_meta_no_depth_write(intel); + intel_meta_no_stencil_write(intel); + intel_meta_color_mask(intel, GL_FALSE); /* save current drawing origin and cliprects (restored at end) */ @@ -419,7 +420,7 @@ intelRotateWindow(struct intel_context *intel, intel->numClipRects = 1; intel->pClipRects = &fullRect; - intel->vtbl.meta_draw_region(intel, screen->rotated_region, NULL); /* ? */ + intel_meta_draw_region(intel, screen->rotated_region, NULL); /* ? */ if (srcBuf == BUFFER_BIT_FRONT_LEFT) { src = intel->intelScreen->front_region; @@ -442,12 +443,12 @@ intelRotateWindow(struct intel_context *intel, } /* set the whole screen up as a texture to avoid alignment issues */ - intel->vtbl.meta_tex_rect_source(intel, + intel_meta_tex_rect_source(intel, src->buffer, screen->width, screen->height, src->pitch, format, type); - intel->vtbl.meta_texture_blend_replace(intel); + intel_meta_texture_blend_replace(intel); /* * loop over the source window's cliprects @@ -492,7 +493,7 @@ intelRotateWindow(struct intel_context *intel, } /* cliprect loop */ - intel->vtbl.leave_meta_state(intel); + intel_leave_meta_state(intel); intel_batchbuffer_flush(intel->batch); /* restore original drawing origin and cliprects */ @@ -724,6 +725,8 @@ intelCopySubBuffer(__DRIdrawablePrivate * dPriv, int x, int y, int w, int h) * Basically, this needs to be called any time the current framebuffer * changes, the renderbuffers change, or we need to draw into different * color buffers. + * + * XXX: Make this into a tracked state atom... */ void intel_draw_buffer(GLcontext * ctx, struct gl_framebuffer *fb) @@ -762,12 +765,7 @@ intel_draw_buffer(GLcontext * ctx, struct gl_framebuffer *fb) /* * How many color buffers are we drawing into? */ - if (fb->_NumColorDrawBuffers[0] != 1 -#if 0 - /* XXX FBO temporary - always use software rendering */ - || 1 -#endif - ) { + if (fb->_NumColorDrawBuffers[0] != 1) { /* writing to 0 or 2 or 4 color buffers */ /*_mesa_debug(ctx, "Software rendering\n");*/ FALLBACK(intel, INTEL_FALLBACK_DRAW_BUFFER, GL_TRUE); @@ -809,20 +807,6 @@ intel_draw_buffer(GLcontext * ctx, struct gl_framebuffer *fb) colorRegion = (irb && irb->region) ? irb->region : NULL; } - /* Update culling direction which changes depending on the - * orientation of the buffer: - */ - if (ctx->Driver.FrontFace) - ctx->Driver.FrontFace(ctx, ctx->Polygon.FrontFace); - else - ctx->NewState |= _NEW_POLYGON; - - if (!colorRegion) { - FALLBACK(intel, INTEL_FALLBACK_DRAW_BUFFER, GL_TRUE); - } - else { - FALLBACK(intel, INTEL_FALLBACK_DRAW_BUFFER, GL_FALSE); - } /*** *** Get depth buffer region and check if we need a software fallback. @@ -855,8 +839,7 @@ intel_draw_buffer(GLcontext * ctx, struct gl_framebuffer *fb) if (irbStencil && irbStencil->region) { ASSERT(irbStencil->Base._ActualFormat == GL_DEPTH24_STENCIL8_EXT); FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, GL_FALSE); - /* need to re-compute stencil hw state */ - ctx->Driver.Enable(ctx, GL_STENCIL_TEST, ctx->Stencil.Enabled); + if (!depthRegion) depthRegion = irbStencil->region; } @@ -867,34 +850,27 @@ intel_draw_buffer(GLcontext * ctx, struct gl_framebuffer *fb) else { /* XXX FBO: instead of FALSE, pass ctx->Stencil.Enabled ??? */ FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, GL_FALSE); - /* need to re-compute stencil hw state */ - ctx->Driver.Enable(ctx, GL_STENCIL_TEST, ctx->Stencil.Enabled); } - /** - ** Release old regions, reference new regions - **/ -#if 0 /* XXX FBO: this seems to be redundant with i915_state_draw_region() */ - if (intel->draw_region != colorRegion) { - intel_region_release(&intel->draw_region); - intel_region_reference(&intel->draw_region, colorRegion); - } - if (intel->intelScreen->depth_region != depthRegion) { - intel_region_release(&intel->intelScreen->depth_region); - intel_region_reference(&intel->intelScreen->depth_region, depthRegion); + if (intel->state.draw_region != colorRegion) { + intel_region_release(&intel->state.draw_region); + intel_region_reference(&intel->state.draw_region, colorRegion); + + /* Raise a state flag to ensure viewport, scissor get recalculated. + */ + intel->state.dirty.intel |= INTEL_NEW_CBUF; } -#endif - intel->vtbl.set_draw_region(intel, colorRegion, depthRegion); + if (intel->state.depth_region != depthRegion) { + intel_region_release(&intel->state.depth_region); + intel_region_reference(&intel->state.depth_region, depthRegion); - /* update viewport since it depends on window size */ - ctx->Driver.Viewport(ctx, ctx->Viewport.X, ctx->Viewport.Y, - ctx->Viewport.Width, ctx->Viewport.Height); + /* Raise a state flag to ensure viewport, scissor get recalculated. + */ + intel->state.dirty.intel |= INTEL_NEW_ZBUF; + } - /* Update hardware scissor */ - ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y, - ctx->Scissor.Width, ctx->Scissor.Height); } diff --git a/src/mesa/drivers/dri/i915tex/intel_context.c b/src/mesa/drivers/dri/i915tex/intel_context.c index 6786c5c1c6..2ae59083ca 100644 --- a/src/mesa/drivers/dri/i915tex/intel_context.c +++ b/src/mesa/drivers/dri/i915tex/intel_context.c @@ -59,6 +59,7 @@ #include "intel_regions.h" #include "intel_buffer_objects.h" #include "intel_fbo.h" +#include "intel_metaops.h" #include "vblank.h" #include "utils.h" @@ -244,12 +245,24 @@ static const struct dri_debug_control debug_control[] = { static void intelInvalidateState(GLcontext * ctx, GLuint new_state) { + struct intel_context *intel = intel_context(ctx); + _swrast_InvalidateState(ctx, new_state); _swsetup_InvalidateState(ctx, new_state); _vbo_InvalidateState(ctx, new_state); _tnl_InvalidateState(ctx, new_state); _tnl_invalidate_vertex_state(ctx, new_state); - intel_context(ctx)->NewGLState |= new_state; + + assert(!intel->metaops.active); + + intel->state.dirty.mesa |= new_state; + intel->state.dirty.intel |= INTEL_NEW_MESA; +} + +void intel_lost_hardware( struct intel_context *intel ) +{ + intel->state.dirty.intel |= ~0; + intel->state.dirty.mesa |= ~0; } @@ -332,11 +345,33 @@ intelInitDriverFunctions(struct dd_function_table *functions) intelInitTextureFuncs(functions); intelInitPixelFuncs(functions); - intelInitStateFuncs(functions); intelInitBufferFuncs(functions); } +static void intel_attribs_init( struct intel_context *intel ) +{ + GLcontext *ctx = &intel->ctx; + + intel->state.Color = &ctx->Color; + intel->state.Depth = &ctx->Depth; + intel->state.Fog = &ctx->Fog; + intel->state.Hint = &ctx->Hint; + intel->state.Light = &ctx->Light; + intel->state.Line = &ctx->Line; + intel->state.Point = &ctx->Point; + intel->state.Polygon = &ctx->Polygon; + intel->state.Scissor = &ctx->Scissor; + intel->state.Stencil = &ctx->Stencil; + intel->state.Texture = &ctx->Texture; + intel->state.Transform = &ctx->Transform; + intel->state.Viewport = &ctx->Viewport; + intel->state.VertexProgram = &ctx->VertexProgram; + intel->state.FragmentProgram = &ctx->FragmentProgram; + intel->state.PolygonStipple = &ctx->PolygonStipple[0]; +} + + GLboolean intelInitContext(struct intel_context *intel, const __GLcontextModes * mesaVis, @@ -418,7 +453,7 @@ intelInitContext(struct intel_context *intel, intel->hw_stipple = 1; - /* XXX FBO: this doesn't seem to be used anywhere */ + /* XXX FBO: recalculate on bind */ switch (mesaVis->depthBits) { case 0: /* what to do in this case? */ case 16: @@ -446,8 +481,6 @@ intelInitContext(struct intel_context *intel, intel->do_irqs = (intel->intelScreen->irq_active && fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS); - intel->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS); - intel->vblank_flags = (intel->intelScreen->irq_active != 0) ? driGetDefaultVBlankFlags(&intel->optionCache) : VBLANK_FLAG_NO_IRQ; @@ -469,8 +502,14 @@ intelInitContext(struct intel_context *intel, intel_bufferobj_init(intel); intel_fbo_init(intel); + intel_attribs_init(intel); + intel_metaops_init(intel); intel_idx_init(intel); + intel->state.dirty.mesa = ~0; + intel->state.dirty.intel = ~0; + + if (intel->ctx.Mesa_DXTn) { _mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc"); _mesa_enable_extension(ctx, "GL_S3_s3tc"); @@ -672,7 +711,7 @@ intelContendedLock(struct intel_context *intel, GLuint flags) intel->prim.flush = 0; /* re-emit all state */ - intel->vtbl.lost_hardware(intel); + intel_lost_hardware(intel); /* force window update */ intel->lastStamp = 0; diff --git a/src/mesa/drivers/dri/i915tex/intel_context.h b/src/mesa/drivers/dri/i915tex/intel_context.h index 20c95a88cb..4d85606763 100644 --- a/src/mesa/drivers/dri/i915tex/intel_context.h +++ b/src/mesa/drivers/dri/i915tex/intel_context.h @@ -52,6 +52,11 @@ struct intel_region; struct intel_context; struct _DriBufferObject; + +struct intel_texture_object; +struct intel_texture_image; + + typedef void (*intel_tri_func) (struct intel_context *, intelVertex *, intelVertex *, intelVertex *); typedef void (*intel_line_func) (struct intel_context *, intelVertex *, @@ -64,55 +69,94 @@ typedef void (*intel_point_func) (struct intel_context *, intelVertex *); #define INTEL_FALLBACK_STENCIL_BUFFER 0x8 #define INTEL_FALLBACK_USER 0x10 #define INTEL_FALLBACK_RENDERMODE 0x20 +#define INTEL_FALLBACK_OTHER 0x40 extern void intelFallback(struct intel_context *intel, GLuint bit, GLboolean mode); #define FALLBACK( intel, bit, mode ) intelFallback( intel, bit, mode ) - #define INTEL_WRITE_PART 0x1 #define INTEL_WRITE_FULL 0x2 #define INTEL_READ 0x4 -struct intel_texture_object -{ - struct gl_texture_object base; /* The "parent" object */ - /* The mipmap tree must include at least these levels once - * validated: - */ - GLuint firstLevel; - GLuint lastLevel; - /* Offset for firstLevel image: - */ - GLuint textureOffset; +#define INTEL_NEW_MESA 0x1 /* Mesa state has changed */ +#define INTEL_NEW_FRAGMENT_PROGRAM 0x2 +#define INTEL_NEW_VERTEX_SIZE 0x4 +#define INTEL_NEW_INPUT_SIZES 0x8 +#define INTEL_NEW_CONTEXT 0x10 /* Lost hardware? */ +#define INTEL_NEW_REDUCED_PRIMITIVE 0x20 +#define INTEL_NEW_FALLBACK 0x40 +#define INTEL_NEW_METAOPS 0x80 /* not needed? */ +#define INTEL_NEW_VBO 0x100 +#define INTEL_NEW_FENCE 0x200 /* whatever invalidates RELOC's */ +#define INTEL_NEW_CBUF 0x400 +#define INTEL_NEW_ZBUF 0x800 +#define INTEL_NEW_WINDOW_DIMENSIONS 0x1000 - /* On validation any active images held in main memory or in other - * regions will be copied to this region and the old storage freed. - */ - struct intel_mipmap_tree *mt; +#define INTEL_NEW_DRIVER0 0x10000 + +struct intel_state_flags { + GLuint mesa; + GLuint intel; + GLuint extra; }; +struct intel_context_state { + struct gl_colorbuffer_attrib *Color; + struct gl_depthbuffer_attrib *Depth; + struct gl_fog_attrib *Fog; + struct gl_hint_attrib *Hint; + struct gl_light_attrib *Light; + struct gl_line_attrib *Line; + struct gl_point_attrib *Point; + struct gl_polygon_attrib *Polygon; + GLuint *PolygonStipple; + struct gl_scissor_attrib *Scissor; + struct gl_stencil_attrib *Stencil; + struct gl_texture_attrib *Texture; + struct gl_transform_attrib *Transform; + struct gl_viewport_attrib *Viewport; + struct gl_vertex_program_state *VertexProgram; + struct gl_fragment_program_state *FragmentProgram; -struct intel_texture_image -{ - struct gl_texture_image base; + GLframebuffer *DrawBuffer; + GLframebuffer *ReadBuffer; + GLenum RenderMode; - /* These aren't stored in gl_texture_image - */ - GLuint level; - GLuint face; + GLuint _ColorDrawBufferMask0; /* ??? */ + + struct intel_region *draw_region; /* INTEL_NEW_CBUF */ + struct intel_region *depth_region; /* INTEL_NEW_ZBUF */ + + + struct gl_fragment_program *fp; - /* If intelImage->mt != NULL, image data is stored here. - * Else if intelImage->base.Data != NULL, image is stored there. - * Else there is no image data. + /* Indexed rendering support. GEN3 specific. */ - struct intel_mipmap_tree *mt; + struct _DriBufferObject *vbo; + GLuint vbo_offset; + + + struct intel_state_flags dirty; +}; + +/* A single atom of derived state + */ +struct intel_tracked_state { + struct intel_state_flags dirty; + void (*update)( struct intel_context *intel ); +}; + +struct intel_driver_state { + struct intel_tracked_state **atoms; + GLuint nr_atoms; }; + #define INTEL_MAX_FIXUP 64 struct intel_context @@ -122,9 +166,7 @@ struct intel_context struct { void (*destroy) (struct intel_context * intel); - void (*emit_state) (struct intel_context * intel); void (*lost_hardware) (struct intel_context * intel); - void (*update_texture_state) (struct intel_context * intel); void (*render_start) (struct intel_context * intel); void (*set_draw_region) (struct intel_context * intel, @@ -133,40 +175,7 @@ struct intel_context GLuint (*flush_cmd) (void); - void (*reduced_primitive_state) (struct intel_context * intel, - GLenum rprim); - - - /* Metaops: - */ - void (*install_meta_state) (struct intel_context * intel); - void (*leave_meta_state) (struct intel_context * intel); - - void (*meta_draw_region) (struct intel_context * intel, - struct intel_region * draw_region, - struct intel_region * depth_region); - - void (*meta_color_mask) (struct intel_context * intel, GLboolean); - - void (*meta_stencil_replace) (struct intel_context * intel, - GLuint mask, GLuint clear); - - void (*meta_depth_replace) (struct intel_context * intel); - - void (*meta_texture_blend_replace) (struct intel_context * intel); - - void (*meta_no_stencil_write) (struct intel_context * intel); - void (*meta_no_depth_write) (struct intel_context * intel); - void (*meta_no_texture) (struct intel_context * intel); - - void (*meta_import_pixel_state) (struct intel_context * intel); - - GLboolean(*meta_tex_rect_source) (struct intel_context * intel, - struct _DriBufferObject * buffer, - GLuint offset, - GLuint pitch, - GLuint height, - GLenum format, GLenum type); + /* Do with metaops: */ void (*rotate_window) (struct intel_context * intel, __DRIdrawablePrivate * dPriv, GLuint srcBuf); @@ -175,8 +184,21 @@ struct intel_context } vtbl; GLint refcount; + + struct intel_context_state state; + + struct intel_driver_state driver_state; + + struct { + /* Will be allocated on demand if needed. + */ + struct intel_context_state state; + struct gl_buffer_object *vbo; + GLboolean active; + } metaops; + + GLuint Fallback; - GLuint NewGLState; struct _DriFenceObject *last_swap_fence; struct _DriFenceObject *first_swap_fence; @@ -193,18 +215,10 @@ struct intel_context } prim; GLboolean locked; - char *prevLockFile; - int prevLockLine; GLuint ClearColor565; GLuint ClearColor8888; - /* Offsets of fields within the current vertex: - */ - GLuint coloroffset; - GLuint specoffset; - GLuint wpos_offset; - GLuint wpos_size; struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX]; GLuint vertex_attr_count; @@ -212,6 +226,8 @@ struct intel_context GLfloat polygon_offset_scale; /* dependent on depth_scale, bpp */ GLboolean hw_stipple; + GLboolean hw_stencil; + GLboolean strict_conformance; /* AGP memory buffer manager: @@ -221,6 +237,10 @@ struct intel_context /* State for intelvb.c and inteltris.c. */ + GLuint coloroffset; + GLuint specoffset; + GLuint wpos_offset; + GLuint wpos_size; GLuint RenderIndex; GLmatrix ViewportMatrix; GLenum render_primitive; @@ -228,13 +248,6 @@ struct intel_context GLuint vertex_size; GLubyte *verts; /* points to tnl->clipspace.vertex_buf */ -#if 0 - struct intel_region *front_region; /* XXX FBO: obsolete */ - struct intel_region *rotated_region; /* XXX FBO: obsolete */ - struct intel_region *back_region; /* XXX FBO: obsolete */ - struct intel_region *draw_region; /* XXX FBO: rename to color_region */ - struct intel_region *depth_region; /**< currently bound depth/Z region */ -#endif /* Fallback rasterization functions */ @@ -249,9 +262,6 @@ struct intel_context drm_clip_rect_t *pClipRects; drm_clip_rect_t fboRect; /**< cliprect for FBO rendering */ - int perf_boxes; - - GLuint do_usleeps; int do_irqs; GLuint irqsEmitted; drm_i915_irq_wait_t iw; @@ -276,22 +286,19 @@ struct intel_context */ GLuint vbl_seq; GLuint vblank_flags; - int64_t swap_ust; int64_t swap_missed_ust; - GLuint swap_count; GLuint swap_missed_count; - GLuint swap_scheduled; - /* Rotation. Need to match that of the - * current screen. - */ + /* Rotation. Need to match that of the + * current screen. + */ - int width; - int height; - int current_rotation; + int width; + int height; + int current_rotation; }; /* These are functions now: @@ -408,78 +415,17 @@ extern GLboolean intelInitContext(struct intel_context *intel, extern void intelGetLock(struct intel_context *intel, GLuint flags); -extern void intelInitState(GLcontext * ctx); extern void intelFinish(GLcontext * ctx); extern void intelFlush(GLcontext * ctx); extern void intelInitDriverFunctions(struct dd_function_table *functions); +void intel_lost_hardware( struct intel_context *intel ); /* ================================================================ * intel_state.c: */ -extern void intelInitStateFuncs(struct dd_function_table *functions); - -#define COMPAREFUNC_ALWAYS 0 -#define COMPAREFUNC_NEVER 0x1 -#define COMPAREFUNC_LESS 0x2 -#define COMPAREFUNC_EQUAL 0x3 -#define COMPAREFUNC_LEQUAL 0x4 -#define COMPAREFUNC_GREATER 0x5 -#define COMPAREFUNC_NOTEQUAL 0x6 -#define COMPAREFUNC_GEQUAL 0x7 - -#define STENCILOP_KEEP 0 -#define STENCILOP_ZERO 0x1 -#define STENCILOP_REPLACE 0x2 -#define STENCILOP_INCRSAT 0x3 -#define STENCILOP_DECRSAT 0x4 -#define STENCILOP_INCR 0x5 -#define STENCILOP_DECR 0x6 -#define STENCILOP_INVERT 0x7 - -#define LOGICOP_CLEAR 0 -#define LOGICOP_NOR 0x1 -#define LOGICOP_AND_INV 0x2 -#define LOGICOP_COPY_INV 0x3 -#define LOGICOP_AND_RVRSE 0x4 -#define LOGICOP_INV 0x5 -#define LOGICOP_XOR 0x6 -#define LOGICOP_NAND 0x7 -#define LOGICOP_AND 0x8 -#define LOGICOP_EQUIV 0x9 -#define LOGICOP_NOOP 0xa -#define LOGICOP_OR_INV 0xb -#define LOGICOP_COPY 0xc -#define LOGICOP_OR_RVRSE 0xd -#define LOGICOP_OR 0xe -#define LOGICOP_SET 0xf - -#define BLENDFACT_ZERO 0x01 -#define BLENDFACT_ONE 0x02 -#define BLENDFACT_SRC_COLR 0x03 -#define BLENDFACT_INV_SRC_COLR 0x04 -#define BLENDFACT_SRC_ALPHA 0x05 -#define BLENDFACT_INV_SRC_ALPHA 0x06 -#define BLENDFACT_DST_ALPHA 0x07 -#define BLENDFACT_INV_DST_ALPHA 0x08 -#define BLENDFACT_DST_COLR 0x09 -#define BLENDFACT_INV_DST_COLR 0x0a -#define BLENDFACT_SRC_ALPHA_SATURATE 0x0b -#define BLENDFACT_CONST_COLOR 0x0c -#define BLENDFACT_INV_CONST_COLOR 0x0d -#define BLENDFACT_CONST_ALPHA 0x0e -#define BLENDFACT_INV_CONST_ALPHA 0x0f -#define BLENDFACT_MASK 0x0f - -#define MI_BATCH_BUFFER_END (0xA<<23) - - -extern int intel_translate_compare_func(GLenum func); -extern int intel_translate_stencil_op(GLenum op); -extern int intel_translate_blend_factor(GLenum factor); -extern int intel_translate_logic_op(GLenum opcode); - +extern void intel_emit_state( struct intel_context *intel ); /*====================================================================== * Inline conversion functions. diff --git a/src/mesa/drivers/dri/i915tex/intel_fbo.c b/src/mesa/drivers/dri/i915tex/intel_fbo.c index ab0e569bd9..9cac2ef9f8 100644 --- a/src/mesa/drivers/dri/i915tex/intel_fbo.c +++ b/src/mesa/drivers/dri/i915tex/intel_fbo.c @@ -42,6 +42,7 @@ #include "intel_mipmap_tree.h" #include "intel_regions.h" #include "intel_span.h" +#include "intel_tex.h" #define FILE_DEBUG_FLAG DEBUG_FBO @@ -380,12 +381,6 @@ intel_create_renderbuffer(GLenum intFormat, GLsizei width, GLsizei height, irb->pfMap = map; irb->pfPitch = pitch / cpp; /* in pixels */ -#if 00 - irb->region = intel_region_create_static(intel, - DRM_MM_TT, - offset, map, cpp, width, height); -#endif - return irb; } diff --git a/src/mesa/drivers/dri/i915tex/intel_idx_render.c b/src/mesa/drivers/dri/i915tex/intel_idx_render.c index fa16d670a3..8cf0adbce6 100644 --- a/src/mesa/drivers/dri/i915tex/intel_idx_render.c +++ b/src/mesa/drivers/dri/i915tex/intel_idx_render.c @@ -70,18 +70,17 @@ struct intel_vb { struct intel_buffer_object *vbo[MAX_VBO]; GLuint nr_vbo; + struct intel_buffer_object *current_vbo; GLuint current_vbo_size; GLuint current_vbo_used; void *current_vbo_ptr; + GLuint hw_vbo_offset; GLuint hw_vbo_delta; GLuint vertex_size; - struct { - struct intel_buffer_object *current_vbo; - GLuint hw_vbo_offset; - } state; + GLuint dirty; }; @@ -130,6 +129,19 @@ static GLboolean check_idx_render(GLcontext *ctx, return GL_TRUE; } +static void +emit_vb_state( struct intel_vb *vb ) +{ + struct intel_context *intel = vb->intel; + + DBG("%s\n", __FUNCTION__); + + intel->state.vbo = vb->current_vbo->buffer; + intel->state.vbo_offset = vb->hw_vbo_offset; + intel->state.dirty.intel |= INTEL_NEW_VBO; + + vb->dirty = 0; +} static void release_current_vbo( struct intel_vb *vb ) @@ -143,12 +155,11 @@ release_current_vbo( struct intel_vb *vb ) GL_ARRAY_BUFFER_ARB, &vb->current_vbo->Base ); - vb->state.current_vbo = NULL; - vb->intel->state.intel |= INTEL_NEW_VBO; - + vb->current_vbo = NULL; vb->current_vbo_ptr = NULL; vb->current_vbo_size = 0; vb->current_vbo_used = 0; + vb->dirty = 0; } static void @@ -189,13 +200,11 @@ get_next_vbo( struct intel_vb *vb, GLuint size ) if (size < VBO_SIZE) size = VBO_SIZE; - vb->state.current_vbo = vb->vbo[vb->nr_vbo++]; - vb->state.hw_vbo_offset = 0; - vb->intel->state.intel |= INTEL_NEW_VBO; - + vb->current_vbo = vb->vbo[vb->nr_vbo++]; vb->current_vbo_size = size; vb->current_vbo_used = 0; - + vb->hw_vbo_offset = 0; + vb->dirty = 1; /* Clear out buffer contents and break any hardware dependency on * the old memory: @@ -222,8 +231,8 @@ static void *get_space( struct intel_vb *vb, GLuint nr, GLuint vertex_size ) if (vb->vertex_size != vertex_size) { vb->vertex_size = vertex_size; - vb->state.hw_vbo_offset = vb->current_vbo_used; - vb->intel->state.intel |= INTEL_NEW_VBO; + vb->hw_vbo_offset = vb->current_vbo_used; + vb->dirty = 1; } if (!vb->current_vbo_ptr) { @@ -319,10 +328,22 @@ static void emit_prims( GLcontext *ctx, if (nr == 0) continue; - + + /* XXX: Need to ensure that both the state and the primitive + * command below end up in the same batchbuffer, otherwise there + * is a risk that another context might interpose a batchbuffer + * containing different statesetting commands. Using logical + * contexts would fix this, as would the BRW scheme of only + * emitting batch commands while holding the lock. + */ + if (vb->dirty) + emit_vb_state( vb ); + + intel_emit_state(intel); + /* XXX: Can emit upto 64k indices, need to split larger prims */ - EMIT_STATE_BEGIN_BATCH(2 + (nr+1)/2, INTEL_BATCH_CLIPRECTS); + BEGIN_BATCH(2 + (nr+1)/2, INTEL_BATCH_CLIPRECTS); OUT_BATCH(0); OUT_BATCH( _3DPRIMITIVE | diff --git a/src/mesa/drivers/dri/i915tex/intel_ioctl.c b/src/mesa/drivers/dri/i915tex/intel_ioctl.c index 3250c6b3a9..8d38e2925d 100644 --- a/src/mesa/drivers/dri/i915tex/intel_ioctl.c +++ b/src/mesa/drivers/dri/i915tex/intel_ioctl.c @@ -134,5 +134,5 @@ intel_batch_ioctl(struct intel_context *intel, /* FIXME: use hardware contexts to avoid 'losing' hardware after * each buffer flush. */ - intel->vtbl.lost_hardware(intel); + intel_lost_hardware(intel); } diff --git a/src/mesa/drivers/dri/i915tex/intel_pixel_copy.c b/src/mesa/drivers/dri/i915tex/intel_pixel_copy.c index 9d478283e4..87bc0fc354 100644 --- a/src/mesa/drivers/dri/i915tex/intel_pixel_copy.c +++ b/src/mesa/drivers/dri/i915tex/intel_pixel_copy.c @@ -42,6 +42,7 @@ #include "intel_regions.h" #include "intel_tris.h" #include "intel_pixel.h" +#include "intel_metaops.h" #define FILE_DEBUG_FLAG DEBUG_PIXEL @@ -154,19 +155,19 @@ do_texture_copypixels(GLcontext * ctx, intelFlush(&intel->ctx); - intel->vtbl.install_meta_state(intel); + intel_install_meta_state(intel); /* Is this true? Also will need to turn depth testing on according * to state: */ - intel->vtbl.meta_no_stencil_write(intel); - intel->vtbl.meta_no_depth_write(intel); + intel_meta_no_stencil_write(intel); + intel_meta_no_depth_write(intel); /* Set the 3d engine to draw into the destination region: */ - intel->vtbl.meta_draw_region(intel, dst, intel->intelScreen->depth_region); + intel_meta_draw_region(intel, dst, intel->intelScreen->depth_region); - intel->vtbl.meta_import_pixel_state(intel); + intel_meta_import_pixel_state(intel); if (src->cpp == 2) { src_format = GL_RGB; @@ -179,15 +180,15 @@ do_texture_copypixels(GLcontext * ctx, /* Set the frontbuffer up as a large rectangular texture. */ - if (!intel->vtbl.meta_tex_rect_source(intel, src->buffer, 0, + if (!intel_meta_tex_rect_source(intel, src->buffer, 0, src->pitch, src->height, src_format, src_type)) { - intel->vtbl.leave_meta_state(intel); + intel_leave_meta_state(intel); return GL_FALSE; } - intel->vtbl.meta_texture_blend_replace(intel); + intel_meta_texture_blend_replace(intel); LOCK_HARDWARE(intel); @@ -229,7 +230,7 @@ do_texture_copypixels(GLcontext * ctx, srcx, srcx + width, srcy, srcy + height); out: - intel->vtbl.leave_meta_state(intel); + intel_leave_meta_state(intel); intel_batchbuffer_flush(intel->batch); } UNLOCK_HARDWARE(intel); diff --git a/src/mesa/drivers/dri/i915tex/intel_pixel_draw.c b/src/mesa/drivers/dri/i915tex/intel_pixel_draw.c index 10a079896a..297e2222d9 100644 --- a/src/mesa/drivers/dri/i915tex/intel_pixel_draw.c +++ b/src/mesa/drivers/dri/i915tex/intel_pixel_draw.c @@ -43,6 +43,7 @@ #include "intel_pixel.h" #include "intel_buffer_objects.h" #include "intel_tris.h" +#include "intel_metaops.h" @@ -64,8 +65,7 @@ do_texture_drawpixels(GLcontext * ctx, fprintf(stderr, "%s\n", __FUNCTION__); intelFlush(&intel->ctx); - intel->vtbl.render_start(intel); - intel->vtbl.emit_state(intel); + intel_emit_state(intel); if (!dst) return GL_FALSE; @@ -101,20 +101,20 @@ do_texture_drawpixels(GLcontext * ctx, return GL_FALSE; } - intel->vtbl.install_meta_state(intel); + intel_install_meta_state(intel); /* Is this true? Also will need to turn depth testing on according * to state: */ - intel->vtbl.meta_no_stencil_write(intel); - intel->vtbl.meta_no_depth_write(intel); + intel_meta_no_stencil_write(intel); + intel_meta_no_depth_write(intel); /* Set the 3d engine to draw into the destination region: */ - intel->vtbl.meta_draw_region(intel, dst, intel->intelScreen->depth_region); + intel_meta_draw_region(intel, dst, intel->intelScreen->depth_region); - intel->vtbl.meta_import_pixel_state(intel); + intel_meta_import_pixel_state(intel); src_offset = (GLuint) _mesa_image_address(2, unpack, pixels, width, height, format, type, 0, 0, 0); @@ -127,13 +127,13 @@ do_texture_drawpixels(GLcontext * ctx, * The major exception is any 24bit texture, like RGB888, for which * there is no hardware support. */ - if (!intel->vtbl.meta_tex_rect_source(intel, src->buffer, src_offset, + if (!intel_meta_tex_rect_source(intel, src->buffer, src_offset, rowLength, height, format, type)) { - intel->vtbl.leave_meta_state(intel); + intel_leave_meta_state(intel); return GL_FALSE; } - intel->vtbl.meta_texture_blend_replace(intel); + intel_meta_texture_blend_replace(intel); LOCK_HARDWARE(intel); @@ -178,7 +178,7 @@ do_texture_drawpixels(GLcontext * ctx, 0x00ff00ff, srcx, srcx + width, srcy + height, srcy); out: - intel->vtbl.leave_meta_state(intel); + intel_leave_meta_state(intel); intel_batchbuffer_flush(intel->batch); } UNLOCK_HARDWARE(intel); diff --git a/src/mesa/drivers/dri/i915tex/intel_pixel_read.c b/src/mesa/drivers/dri/i915tex/intel_pixel_read.c index 24e49ae066..13b69dc776 100644 --- a/src/mesa/drivers/dri/i915tex/intel_pixel_read.c +++ b/src/mesa/drivers/dri/i915tex/intel_pixel_read.c @@ -94,9 +94,9 @@ do_texture_readpixels(GLcontext * ctx, return GL_FALSE; } - intel->vtbl.meta_texrect_source(intel, intel_readbuf_region(intel)); + intel_meta_texrect_source(intel, intel_readbuf_region(intel)); - if (!intel->vtbl.meta_render_dest(intel, dest_region, type, format)) { + if (!intel_meta_render_dest(intel, dest_region, type, format)) { if (INTEL_DEBUG & DEBUG_PIXEL) fprintf(stderr, "%s: couldn't set dest %s/%s\n", __FUNCTION__, @@ -108,9 +108,9 @@ do_texture_readpixels(GLcontext * ctx, LOCK_HARDWARE(intel); if (intel->driDrawable->numClipRects) { - intel->vtbl.install_meta_state(intel); - intel->vtbl.meta_no_depth_write(intel); - intel->vtbl.meta_no_stencil_write(intel); + intel_install_meta_state(intel); + intel_meta_no_depth_write(intel); + intel_meta_no_stencil_write(intel); if (!driClipRectToFramebuffer(ctx->ReadBuffer, &x, &y, &width, &height)) { UNLOCK_HARDWARE(intel); @@ -127,28 +127,28 @@ do_texture_readpixels(GLcontext * ctx, /* Set the frontbuffer up as a large rectangular texture. */ - intel->vtbl.meta_tex_rect_source(intel, src_region, textureFormat); + intel_meta_tex_rect_source(intel, src_region, textureFormat); - intel->vtbl.meta_texture_blend_replace(i830, glTextureFormat); + intel_meta_texture_blend_replace(i830, glTextureFormat); /* Set the 3d engine to draw into the destination region: */ - intel->vtbl.meta_draw_region(intel, dest_region); - intel->vtbl.meta_draw_format(intel, destFormat, depthFormat); /* ?? */ + intel_meta_draw_region(intel, dest_region); + intel_meta_draw_format(intel, destFormat, depthFormat); /* ?? */ /* Draw a single quad, no cliprects: */ - intel->vtbl.meta_disable_cliprects(intel); + intel_meta_disable_cliprects(intel); - intel->vtbl.draw_quad(intel, + intel_draw_quad(intel, 0, width, 0, height, 0x00ff00ff, x, x + width, y, y + height); - intel->vtbl.leave_meta_state(intel); + intel_leave_meta_state(intel); } UNLOCK_HARDWARE(intel); diff --git a/src/mesa/drivers/dri/i915tex/intel_reg.h b/src/mesa/drivers/dri/i915tex/intel_reg.h index 1ec153266c..b5a1a20eaf 100644 --- a/src/mesa/drivers/dri/i915tex/intel_reg.h +++ b/src/mesa/drivers/dri/i915tex/intel_reg.h @@ -81,4 +81,60 @@ #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) + +#define COMPAREFUNC_ALWAYS 0 +#define COMPAREFUNC_NEVER 0x1 +#define COMPAREFUNC_LESS 0x2 +#define COMPAREFUNC_EQUAL 0x3 +#define COMPAREFUNC_LEQUAL 0x4 +#define COMPAREFUNC_GREATER 0x5 +#define COMPAREFUNC_NOTEQUAL 0x6 +#define COMPAREFUNC_GEQUAL 0x7 + +#define STENCILOP_KEEP 0 +#define STENCILOP_ZERO 0x1 +#define STENCILOP_REPLACE 0x2 +#define STENCILOP_INCRSAT 0x3 +#define STENCILOP_DECRSAT 0x4 +#define STENCILOP_INCR 0x5 +#define STENCILOP_DECR 0x6 +#define STENCILOP_INVERT 0x7 + +#define LOGICOP_CLEAR 0 +#define LOGICOP_NOR 0x1 +#define LOGICOP_AND_INV 0x2 +#define LOGICOP_COPY_INV 0x3 +#define LOGICOP_AND_RVRSE 0x4 +#define LOGICOP_INV 0x5 +#define LOGICOP_XOR 0x6 +#define LOGICOP_NAND 0x7 +#define LOGICOP_AND 0x8 +#define LOGICOP_EQUIV 0x9 +#define LOGICOP_NOOP 0xa +#define LOGICOP_OR_INV 0xb +#define LOGICOP_COPY 0xc +#define LOGICOP_OR_RVRSE 0xd +#define LOGICOP_OR 0xe +#define LOGICOP_SET 0xf + +#define BLENDFACT_ZERO 0x01 +#define BLENDFACT_ONE 0x02 +#define BLENDFACT_SRC_COLR 0x03 +#define BLENDFACT_INV_SRC_COLR 0x04 +#define BLENDFACT_SRC_ALPHA 0x05 +#define BLENDFACT_INV_SRC_ALPHA 0x06 +#define BLENDFACT_DST_ALPHA 0x07 +#define BLENDFACT_INV_DST_ALPHA 0x08 +#define BLENDFACT_DST_COLR 0x09 +#define BLENDFACT_INV_DST_COLR 0x0a +#define BLENDFACT_SRC_ALPHA_SATURATE 0x0b +#define BLENDFACT_CONST_COLOR 0x0c +#define BLENDFACT_INV_CONST_COLOR 0x0d +#define BLENDFACT_CONST_ALPHA 0x0e +#define BLENDFACT_INV_CONST_ALPHA 0x0f +#define BLENDFACT_MASK 0x0f + +#define MI_BATCH_BUFFER_END (0xA<<23) + + #endif diff --git a/src/mesa/drivers/dri/i915tex/intel_render.c b/src/mesa/drivers/dri/i915tex/intel_render.c index f9fa55051e..148a486266 100644 --- a/src/mesa/drivers/dri/i915tex/intel_render.c +++ b/src/mesa/drivers/dri/i915tex/intel_render.c @@ -112,7 +112,7 @@ intelDmaPrimitive(struct intel_context *intel, GLenum prim) if (0) fprintf(stderr, "%s %s\n", __FUNCTION__, _mesa_lookup_enum_by_nr(prim)); INTEL_FIREVERTICES(intel); - intel->vtbl.reduced_primitive_state(intel, reduced_prim[prim]); +/* intel->vtbl.reduced_primitive_state(intel, reduced_prim[prim]); */ intelStartInlinePrimitive(intel, hw_prim[prim], INTEL_BATCH_CLIPRECTS); } diff --git a/src/mesa/drivers/dri/i915tex/intel_screen.c b/src/mesa/drivers/dri/i915tex/intel_screen.c index efa1b014a6..8a4c1194c0 100644 --- a/src/mesa/drivers/dri/i915tex/intel_screen.c +++ b/src/mesa/drivers/dri/i915tex/intel_screen.c @@ -108,21 +108,11 @@ intelMapScreenRegions(__DRIscreenPrivate * sPriv) return GL_FALSE; } -#if 0 - _mesa_printf("TEX 0x%08x ", intelScreen->tex.handle); - if (drmMap(sPriv->fd, - intelScreen->tex.handle, - intelScreen->tex.size, - (drmAddress *) & intelScreen->tex.map) != 0) { - intelUnmapScreenRegions(intelScreen); - return GL_FALSE; - } -#endif if (0) - printf("Mappings: front: %p back: %p depth: %p tex: %p\n", + printf("Mappings: front: %p back: %p depth: %p\n", intelScreen->front.map, intelScreen->back.map, - intelScreen->depth.map, intelScreen->tex.map); + intelScreen->depth.map); return GL_TRUE; } @@ -246,12 +236,6 @@ intelUnmapScreenRegions(intelScreenPrivate * intelScreen) intelScreen->depth.map = NULL; #endif } - if (intelScreen->tex.map) { -#if REALLY_UNMAP - drmUnmap(intelScreen->tex.map, intelScreen->tex.size); - intelScreen->tex.map = NULL; -#endif - } } @@ -271,8 +255,6 @@ intelPrintDRIInfo(intelScreenPrivate * intelScreen, fprintf(stderr, "*** Rotated size: 0x%x offset: 0x%x pitch: %d\n", intelScreen->rotated.size, intelScreen->rotated.offset, intelScreen->rotated.pitch); - fprintf(stderr, "*** Texture size: 0x%x offset: 0x%x\n", - intelScreen->tex.size, intelScreen->tex.offset); fprintf(stderr, "*** Memory : 0x%x\n", gDRIPriv->mem); } @@ -330,11 +312,6 @@ intelUpdateScreenFromSAREA(intelScreenPrivate * intelScreen, intelScreen->depth.handle = sarea->depth_handle; intelScreen->depth.size = sarea->depth_size; - intelScreen->tex.offset = sarea->tex_offset; - intelScreen->logTextureGranularity = sarea->log_tex_granularity; - intelScreen->tex.handle = sarea->tex_handle; - intelScreen->tex.size = sarea->tex_size; - intelScreen->rotated.offset = sarea->rotated_offset; intelScreen->rotated.pitch = sarea->rotated_pitch * intelScreen->cpp; intelScreen->rotated.size = sarea->rotated_size; @@ -401,7 +378,7 @@ intelInitDriver(__DRIscreenPrivate * sPriv) intelScreen->fbFormat = DV_PF_8888; break; default: - exit(1); + assert(0); break; } @@ -414,24 +391,6 @@ intelInitDriver(__DRIscreenPrivate * sPriv) return GL_FALSE; } -#if 0 - - /* - * FIXME: Remove this code and its references. - */ - - intelScreen->tex.offset = gDRIPriv->textureOffset; - intelScreen->logTextureGranularity = gDRIPriv->logTextureGranularity; - intelScreen->tex.handle = gDRIPriv->textures; - intelScreen->tex.size = gDRIPriv->textureSize; - -#else - intelScreen->tex.offset = 0; - intelScreen->logTextureGranularity = 0; - intelScreen->tex.handle = 0; - intelScreen->tex.size = 0; -#endif - intelScreen->sarea_priv_offset = gDRIPriv->sarea_priv_offset; if (0) @@ -455,22 +414,6 @@ intelInitDriver(__DRIscreenPrivate * sPriv) } } - /* Determine if batchbuffers are allowed */ - { - int ret; - drmI830GetParam gp; - - gp.param = I830_PARAM_ALLOW_BATCHBUFFER; - gp.value = &intelScreen->allow_batchbuffer; - - ret = drmCommandWriteRead(sPriv->fd, DRM_I830_GETPARAM, - &gp, sizeof(gp)); - if (ret) { - fprintf(stderr, "drmI830GetParam: (%d) %d\n", gp.param, ret); - return GL_FALSE; - } - } - if (glx_enable_extension != NULL) { (*glx_enable_extension) (psc, "GLX_SGI_swap_control"); (*glx_enable_extension) (psc, "GLX_SGI_video_sync"); @@ -670,7 +613,8 @@ intelCreateContext(const __GLcontextModes * mesaVis, case PCI_CHIP_I830_M: case PCI_CHIP_I855_GM: case PCI_CHIP_I865_G: - return i830CreateContext(mesaVis, driContextPriv, sharedContextPrivate); +/* return i830CreateContext(mesaVis, driContextPriv, sharedContextPrivate); */ + return GL_FALSE; case PCI_CHIP_I915_G: case PCI_CHIP_I915_GM: diff --git a/src/mesa/drivers/dri/i915tex/intel_screen.h b/src/mesa/drivers/dri/i915tex/intel_screen.h index 17698773f3..99b18ca578 100644 --- a/src/mesa/drivers/dri/i915tex/intel_screen.h +++ b/src/mesa/drivers/dri/i915tex/intel_screen.h @@ -53,7 +53,6 @@ typedef struct intelRegion back; intelRegion rotated; intelRegion depth; - intelRegion tex; struct intel_region *front_region; struct intel_region *back_region; @@ -66,18 +65,14 @@ typedef struct int mem; /* unused */ int cpp; /* for front and back buffers */ -/* int bitsPerPixel; */ int fbFormat; /* XXX FBO: this is obsolete - remove after i830 updates */ - int logTextureGranularity; - __DRIscreenPrivate *driScrnPriv; unsigned int sarea_priv_offset; int drmMinor; int irq_active; - int allow_batchbuffer; struct matrix23 rotMatrix; diff --git a/src/mesa/drivers/dri/i915tex/intel_state.c b/src/mesa/drivers/dri/i915tex/intel_state.c index f85d8ef835..176dc598c0 100644 --- a/src/mesa/drivers/dri/i915tex/intel_state.c +++ b/src/mesa/drivers/dri/i915tex/intel_state.c @@ -39,325 +39,91 @@ #include "intel_regions.h" #include "swrast/swrast.h" -int -intel_translate_compare_func(GLenum func) -{ - switch (func) { - case GL_NEVER: - return COMPAREFUNC_NEVER; - case GL_LESS: - return COMPAREFUNC_LESS; - case GL_LEQUAL: - return COMPAREFUNC_LEQUAL; - case GL_GREATER: - return COMPAREFUNC_GREATER; - case GL_GEQUAL: - return COMPAREFUNC_GEQUAL; - case GL_NOTEQUAL: - return COMPAREFUNC_NOTEQUAL; - case GL_EQUAL: - return COMPAREFUNC_EQUAL; - case GL_ALWAYS: - return COMPAREFUNC_ALWAYS; - } - - fprintf(stderr, "Unknown value in %s: %x\n", __FUNCTION__, func); - return COMPAREFUNC_ALWAYS; -} - -int -intel_translate_stencil_op(GLenum op) -{ - switch (op) { - case GL_KEEP: - return STENCILOP_KEEP; - case GL_ZERO: - return STENCILOP_ZERO; - case GL_REPLACE: - return STENCILOP_REPLACE; - case GL_INCR: - return STENCILOP_INCRSAT; - case GL_DECR: - return STENCILOP_DECRSAT; - case GL_INCR_WRAP: - return STENCILOP_INCR; - case GL_DECR_WRAP: - return STENCILOP_DECR; - case GL_INVERT: - return STENCILOP_INVERT; - default: - return STENCILOP_ZERO; - } -} +/*********************************************************************** + */ -int -intel_translate_blend_factor(GLenum factor) +static GLboolean check_state( const struct intel_state_flags *a, + const struct intel_state_flags *b ) { - switch (factor) { - case GL_ZERO: - return BLENDFACT_ZERO; - case GL_SRC_ALPHA: - return BLENDFACT_SRC_ALPHA; - case GL_ONE: - return BLENDFACT_ONE; - case GL_SRC_COLOR: - return BLENDFACT_SRC_COLR; - case GL_ONE_MINUS_SRC_COLOR: - return BLENDFACT_INV_SRC_COLR; - case GL_DST_COLOR: - return BLENDFACT_DST_COLR; - case GL_ONE_MINUS_DST_COLOR: - return BLENDFACT_INV_DST_COLR; - case GL_ONE_MINUS_SRC_ALPHA: - return BLENDFACT_INV_SRC_ALPHA; - case GL_DST_ALPHA: - return BLENDFACT_DST_ALPHA; - case GL_ONE_MINUS_DST_ALPHA: - return BLENDFACT_INV_DST_ALPHA; - case GL_SRC_ALPHA_SATURATE: - return BLENDFACT_SRC_ALPHA_SATURATE; - case GL_CONSTANT_COLOR: - return BLENDFACT_CONST_COLOR; - case GL_ONE_MINUS_CONSTANT_COLOR: - return BLENDFACT_INV_CONST_COLOR; - case GL_CONSTANT_ALPHA: - return BLENDFACT_CONST_ALPHA; - case GL_ONE_MINUS_CONSTANT_ALPHA: - return BLENDFACT_INV_CONST_ALPHA; - } - - fprintf(stderr, "Unknown value in %s: %x\n", __FUNCTION__, factor); - return BLENDFACT_ZERO; + return ((a->mesa & b->mesa) || + (a->intel & b->intel) || + (a->extra & b->extra)); } -int -intel_translate_logic_op(GLenum opcode) +static void accumulate_state( struct intel_state_flags *a, + const struct intel_state_flags *b ) { - switch (opcode) { - case GL_CLEAR: - return LOGICOP_CLEAR; - case GL_AND: - return LOGICOP_AND; - case GL_AND_REVERSE: - return LOGICOP_AND_RVRSE; - case GL_COPY: - return LOGICOP_COPY; - case GL_COPY_INVERTED: - return LOGICOP_COPY_INV; - case GL_AND_INVERTED: - return LOGICOP_AND_INV; - case GL_NOOP: - return LOGICOP_NOOP; - case GL_XOR: - return LOGICOP_XOR; - case GL_OR: - return LOGICOP_OR; - case GL_OR_INVERTED: - return LOGICOP_OR_INV; - case GL_NOR: - return LOGICOP_NOR; - case GL_EQUIV: - return LOGICOP_EQUIV; - case GL_INVERT: - return LOGICOP_INV; - case GL_OR_REVERSE: - return LOGICOP_OR_RVRSE; - case GL_NAND: - return LOGICOP_NAND; - case GL_SET: - return LOGICOP_SET; - default: - return LOGICOP_SET; - } + a->mesa |= b->mesa; + a->intel |= b->intel; + a->extra |= b->extra; } -static void -intelClearColor(GLcontext * ctx, const GLfloat color[4]) +static void xor_states( struct intel_state_flags *result, + const struct intel_state_flags *a, + const struct intel_state_flags *b ) { - struct intel_context *intel = intel_context(ctx); - GLubyte clear[4]; - - CLAMPED_FLOAT_TO_UBYTE(clear[0], color[0]); - CLAMPED_FLOAT_TO_UBYTE(clear[1], color[1]); - CLAMPED_FLOAT_TO_UBYTE(clear[2], color[2]); - CLAMPED_FLOAT_TO_UBYTE(clear[3], color[3]); - - /* compute both 32 and 16-bit clear values */ - intel->ClearColor8888 = INTEL_PACKCOLOR8888(clear[0], clear[1], - clear[2], clear[3]); - intel->ClearColor565 = INTEL_PACKCOLOR565(clear[0], clear[1], clear[2]); + result->mesa = a->mesa ^ b->mesa; + result->intel = a->intel ^ b->intel; + result->extra = a->extra ^ b->extra; } -/** - * Update the viewport transformation matrix. Depends on: - * - viewport pos/size - * - depthrange - * - window pos/size or FBO size +/*********************************************************************** + * Emit all state: */ -static void -intelCalcViewport(GLcontext * ctx) +void intel_emit_state( struct intel_context *intel ) { - struct intel_context *intel = intel_context(ctx); - const GLfloat *v = ctx->Viewport._WindowMap.m; - const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF; - GLfloat *m = intel->ViewportMatrix.m; - GLfloat yScale, yBias; - - if (ctx->DrawBuffer->Name) { - /* User created FBO */ - struct intel_renderbuffer *irb - = intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[0][0]); - if (irb && !irb->RenderToTexture) { - /* y=0=top */ - yScale = -1.0; - yBias = irb->Base.Height; - } - else { - /* y=0=bottom */ - yScale = 1.0; - yBias = 0.0; + struct intel_state_flags *state = &intel->state.dirty; + GLuint i; + + if (state->intel == 0) + return; + + + if (INTEL_DEBUG) { + /* Debug version which enforces various sanity checks on the + * state flags which are generated and checked to help ensure + * state atoms are ordered correctly in the list. + */ + struct intel_state_flags examined, prev; + _mesa_memset(&examined, 0, sizeof(examined)); + prev = *state; + + for (i = 0; i < intel->driver_state.nr_atoms; i++) { + const struct intel_tracked_state *atom = intel->driver_state.atoms[i]; + struct intel_state_flags generated; + + assert(atom->dirty.mesa || + atom->dirty.intel || + atom->dirty.extra); + assert(atom->update); + + if (check_state(state, &atom->dirty)) { + intel->driver_state.atoms[i]->update( intel ); + } + + accumulate_state(&examined, &atom->dirty); + + /* generated = (prev ^ state) + * if (examined & generated) + * fail; + */ + xor_states(&generated, &prev, state); + assert(!check_state(&examined, &generated)); + prev = *state; } } else { - /* window buffer, y=0=top */ - yScale = -1.0; - yBias = (intel->driDrawable) ? intel->driDrawable->h : 0.0F; - } + const GLuint nr = intel->driver_state.nr_atoms; - m[MAT_SX] = v[MAT_SX]; - m[MAT_TX] = v[MAT_TX] + SUBPIXEL_X; - - m[MAT_SY] = v[MAT_SY] * yScale; - m[MAT_TY] = v[MAT_TY] * yScale + yBias + SUBPIXEL_Y; - - m[MAT_SZ] = v[MAT_SZ] * depthScale; - m[MAT_TZ] = v[MAT_TZ] * depthScale; -} - -static void -intelViewport(GLcontext * ctx, - GLint x, GLint y, GLsizei width, GLsizei height) -{ - intelCalcViewport(ctx); -} - -static void -intelDepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) -{ - intelCalcViewport(ctx); -} - -/* Fallback to swrast for select and feedback. - */ -static void -intelRenderMode(GLcontext * ctx, GLenum mode) -{ - struct intel_context *intel = intel_context(ctx); - FALLBACK(intel, INTEL_FALLBACK_RENDERMODE, (mode != GL_RENDER)); -} - - -void -intelInitStateFuncs(struct dd_function_table *functions) -{ - functions->RenderMode = intelRenderMode; - functions->Viewport = intelViewport; - functions->DepthRange = intelDepthRange; - functions->ClearColor = intelClearColor; -} - - - - -void -intelInitState(GLcontext * ctx) -{ - /* Mesa should do this for us: - */ - ctx->Driver.AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef); - - ctx->Driver.BlendColor(ctx, ctx->Color.BlendColor); - - ctx->Driver.BlendEquationSeparate(ctx, - ctx->Color.BlendEquationRGB, - ctx->Color.BlendEquationA); - - ctx->Driver.BlendFuncSeparate(ctx, - ctx->Color.BlendSrcRGB, - ctx->Color.BlendDstRGB, - ctx->Color.BlendSrcA, ctx->Color.BlendDstA); - - ctx->Driver.ColorMask(ctx, - ctx->Color.ColorMask[RCOMP], - ctx->Color.ColorMask[GCOMP], - ctx->Color.ColorMask[BCOMP], - ctx->Color.ColorMask[ACOMP]); - - ctx->Driver.CullFace(ctx, ctx->Polygon.CullFaceMode); - ctx->Driver.DepthFunc(ctx, ctx->Depth.Func); - ctx->Driver.DepthMask(ctx, ctx->Depth.Mask); - - ctx->Driver.Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled); - ctx->Driver.Enable(ctx, GL_BLEND, ctx->Color.BlendEnabled); - ctx->Driver.Enable(ctx, GL_COLOR_LOGIC_OP, ctx->Color.ColorLogicOpEnabled); - ctx->Driver.Enable(ctx, GL_COLOR_SUM, ctx->Fog.ColorSumEnabled); - ctx->Driver.Enable(ctx, GL_CULL_FACE, ctx->Polygon.CullFlag); - ctx->Driver.Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test); - ctx->Driver.Enable(ctx, GL_DITHER, ctx->Color.DitherFlag); - ctx->Driver.Enable(ctx, GL_FOG, ctx->Fog.Enabled); - ctx->Driver.Enable(ctx, GL_LIGHTING, ctx->Light.Enabled); - ctx->Driver.Enable(ctx, GL_LINE_SMOOTH, ctx->Line.SmoothFlag); - ctx->Driver.Enable(ctx, GL_POLYGON_STIPPLE, ctx->Polygon.StippleFlag); - ctx->Driver.Enable(ctx, GL_SCISSOR_TEST, ctx->Scissor.Enabled); - ctx->Driver.Enable(ctx, GL_STENCIL_TEST, ctx->Stencil.Enabled); - ctx->Driver.Enable(ctx, GL_TEXTURE_1D, GL_FALSE); - ctx->Driver.Enable(ctx, GL_TEXTURE_2D, GL_FALSE); - ctx->Driver.Enable(ctx, GL_TEXTURE_RECTANGLE_NV, GL_FALSE); - ctx->Driver.Enable(ctx, GL_TEXTURE_3D, GL_FALSE); - ctx->Driver.Enable(ctx, GL_TEXTURE_CUBE_MAP, GL_FALSE); - - ctx->Driver.Fogfv(ctx, GL_FOG_COLOR, ctx->Fog.Color); - ctx->Driver.Fogfv(ctx, GL_FOG_MODE, 0); - ctx->Driver.Fogfv(ctx, GL_FOG_DENSITY, &ctx->Fog.Density); - ctx->Driver.Fogfv(ctx, GL_FOG_START, &ctx->Fog.Start); - ctx->Driver.Fogfv(ctx, GL_FOG_END, &ctx->Fog.End); - - ctx->Driver.FrontFace(ctx, ctx->Polygon.FrontFace); - - { - GLfloat f = (GLfloat) ctx->Light.Model.ColorControl; - ctx->Driver.LightModelfv(ctx, GL_LIGHT_MODEL_COLOR_CONTROL, &f); + for (i = 0; i < nr; i++) { + if (check_state(state, &intel->driver_state.atoms[i]->dirty)) + intel->driver_state.atoms[i]->update( intel ); + } } - ctx->Driver.LineWidth(ctx, ctx->Line.Width); - ctx->Driver.LogicOpcode(ctx, ctx->Color.LogicOp); - ctx->Driver.PointSize(ctx, ctx->Point.Size); - ctx->Driver.PolygonStipple(ctx, (const GLubyte *) ctx->PolygonStipple); - ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y, - ctx->Scissor.Width, ctx->Scissor.Height); - ctx->Driver.ShadeModel(ctx, ctx->Light.ShadeModel); - ctx->Driver.StencilFuncSeparate(ctx, GL_FRONT, - ctx->Stencil.Function[0], - ctx->Stencil.Ref[0], - ctx->Stencil.ValueMask[0]); - ctx->Driver.StencilFuncSeparate(ctx, GL_BACK, - ctx->Stencil.Function[1], - ctx->Stencil.Ref[1], - ctx->Stencil.ValueMask[1]); - ctx->Driver.StencilMaskSeparate(ctx, GL_FRONT, ctx->Stencil.WriteMask[0]); - ctx->Driver.StencilMaskSeparate(ctx, GL_BACK, ctx->Stencil.WriteMask[1]); - ctx->Driver.StencilOpSeparate(ctx, GL_FRONT, - ctx->Stencil.FailFunc[0], - ctx->Stencil.ZFailFunc[0], - ctx->Stencil.ZPassFunc[0]); - ctx->Driver.StencilOpSeparate(ctx, GL_BACK, - ctx->Stencil.FailFunc[1], - ctx->Stencil.ZFailFunc[1], - ctx->Stencil.ZPassFunc[1]); + memset(state, 0, sizeof(*state)); +} - /* XXX this isn't really needed */ - ctx->Driver.DrawBuffer(ctx, ctx->Color.DrawBuffer[0]); -} diff --git a/src/mesa/drivers/dri/i915tex/intel_tex.h b/src/mesa/drivers/dri/i915tex/intel_tex.h index 6e9938fe53..4942ed003c 100644 --- a/src/mesa/drivers/dri/i915tex/intel_tex.h +++ b/src/mesa/drivers/dri/i915tex/intel_tex.h @@ -33,6 +33,46 @@ #include "texmem.h" +struct intel_texture_object +{ + struct gl_texture_object base; /* The "parent" object */ + + /* The mipmap tree must include at least these levels once + * validated: + */ + GLuint firstLevel; + GLuint lastLevel; + + /* Offset for firstLevel image: + */ + GLuint textureOffset; + + /* On validation any active images held in main memory or in other + * regions will be copied to this region and the old storage freed. + */ + struct intel_mipmap_tree *mt; +}; + + + +struct intel_texture_image +{ + struct gl_texture_image base; + + /* These aren't stored in gl_texture_image + */ + GLuint level; + GLuint face; + + /* If intelImage->mt != NULL, image data is stored here. + * Else if intelImage->base.Data != NULL, image is stored there. + * Else there is no image data. + */ + struct intel_mipmap_tree *mt; +}; + + + void intelInitTextureFuncs(struct dd_function_table *functions); const struct gl_texture_format *intelChooseTextureFormat(GLcontext * ctx, diff --git a/src/mesa/drivers/dri/i915tex/intel_tris.c b/src/mesa/drivers/dri/i915tex/intel_tris.c index 1ba49d8f6e..f76be50cc5 100644 --- a/src/mesa/drivers/dri/i915tex/intel_tris.c +++ b/src/mesa/drivers/dri/i915tex/intel_tris.c @@ -88,7 +88,7 @@ intelStartInlinePrimitive(struct intel_context *intel, { BATCH_LOCALS; - intel->vtbl.emit_state(intel); + intel_emit_state(intel); /* Need to make sure at the very least that we don't wrap * batchbuffers in BEGIN_BATCH below, otherwise the primitive will @@ -97,7 +97,7 @@ intelStartInlinePrimitive(struct intel_context *intel, */ if (intel_batchbuffer_space(intel->batch) < 100) { intel_batchbuffer_flush(intel->batch); - intel->vtbl.emit_state(intel); + intel_emit_state(intel); } /* _mesa_printf("%s *", __progname); */ @@ -143,7 +143,7 @@ intelExtendInlinePrimitive(struct intel_context *intel, GLuint dwords) /* _mesa_printf("."); */ - intel->vtbl.assert_not_dirty(intel); + assert(intel->state.dirty.intel == 0); ptr = (GLuint *) intel->batch->ptr; intel->batch->ptr += sz; @@ -750,76 +750,79 @@ intelFastRenderClippedPoly(GLcontext * ctx, const GLuint * elts, GLuint n) -#define ANY_FALLBACK_FLAGS (DD_LINE_STIPPLE | DD_TRI_STIPPLE | DD_POINT_ATTEN | DD_POINT_SMOOTH | DD_TRI_SMOOTH) -#define ANY_RASTER_FLAGS (DD_TRI_LIGHT_TWOSIDE | DD_TRI_OFFSET | DD_TRI_UNFILLED) - -void -intelChooseRenderState(GLcontext * ctx) +static void update_render_index( struct intel_context *intel ) { + GLcontext *ctx = &intel->ctx; TNLcontext *tnl = TNL_CONTEXT(ctx); - struct intel_context *intel = intel_context(ctx); - GLuint flags = ctx->_TriangleCaps; + + /* INTEL_NEW_FRAGMENT_PROGRAM, XXX! + */ const struct gl_fragment_program *fprog = ctx->FragmentProgram._Current; GLboolean have_wpos = (fprog && (fprog->Base.InputsRead & FRAG_BIT_WPOS)); GLuint index = 0; - if (INTEL_DEBUG & DEBUG_STATE) - fprintf(stderr, "\n%s\n", __FUNCTION__); + intel->draw_point = intel_draw_point; + intel->draw_line = intel_draw_line; + intel->draw_tri = intel_draw_triangle; - if ((flags & (ANY_FALLBACK_FLAGS | ANY_RASTER_FLAGS)) || have_wpos) { + /* _NEW_LIGHT + */ + if (intel->state.Light->Enabled && intel->state.Light->Model.TwoSide) + index |= INTEL_TWOSIDE_BIT; - if (flags & ANY_RASTER_FLAGS) { - if (flags & DD_TRI_LIGHT_TWOSIDE) - index |= INTEL_TWOSIDE_BIT; - if (flags & DD_TRI_OFFSET) - index |= INTEL_OFFSET_BIT; - if (flags & DD_TRI_UNFILLED) - index |= INTEL_UNFILLED_BIT; - } + /* _NEW_POLYGON + */ + if (intel->state.Polygon->OffsetPoint || + intel->state.Polygon->OffsetLine || + intel->state.Polygon->OffsetFill) + index |= INTEL_OFFSET_BIT; + + if (intel->state.Polygon->FrontMode != GL_FILL || + intel->state.Polygon->BackMode != GL_FILL) + index |= INTEL_UNFILLED_BIT; + + if (have_wpos) { + intel->draw_point = intel_wpos_point; + intel->draw_line = intel_wpos_line; + intel->draw_tri = intel_wpos_triangle; + + /* Make sure these get called: + */ + index |= INTEL_FALLBACK_BIT; + } - if (have_wpos) { - intel->draw_point = intel_wpos_point; - intel->draw_line = intel_wpos_line; - intel->draw_tri = intel_wpos_triangle; + /* _NEW_LINE + */ + if (intel->state.Line->StippleFlag) { + intel->draw_line = intel_fallback_line; + index |= INTEL_FALLBACK_BIT; + } + + /* INTEL_NEW_FALLBACK ?? _NEW_POLYGON_STIPPLE at least... + */ + if (intel->state.Polygon->StippleFlag && !intel->hw_stipple) { + intel->draw_tri = intel_fallback_tri; + index |= INTEL_FALLBACK_BIT; + } - /* Make sure these get called: - */ - index |= INTEL_FALLBACK_BIT; - } - else { - intel->draw_point = intel_draw_point; - intel->draw_line = intel_draw_line; - intel->draw_tri = intel_draw_triangle; - } + if (intel->state.Line->SmoothFlag && intel->strict_conformance) { + intel->draw_tri = intel_fallback_tri; + index |= INTEL_FALLBACK_BIT; + } - /* Hook in fallbacks for specific primitives. - */ - if (flags & ANY_FALLBACK_FLAGS) { - if (flags & DD_LINE_STIPPLE) - intel->draw_line = intel_fallback_line; - - if ((flags & DD_TRI_STIPPLE) && !intel->hw_stipple) - intel->draw_tri = intel_fallback_tri; - - if (flags & DD_TRI_SMOOTH) { - if (intel->strict_conformance) - intel->draw_tri = intel_fallback_tri; - } - - if (flags & DD_POINT_ATTEN) { - if (0) - intel->draw_point = intel_atten_point; - else - intel->draw_point = intel_fallback_point; - } - - if (flags & DD_POINT_SMOOTH) { - if (intel->strict_conformance) - intel->draw_point = intel_fallback_point; - } - - index |= INTEL_FALLBACK_BIT; - } + /* _NEW_POINT + */ + if (intel->state.Point->_Attenuated) { + if (0) + intel->draw_point = intel_atten_point; + else + intel->draw_point = intel_fallback_point; + index |= INTEL_FALLBACK_BIT; + } + + if (intel->state.Point->SmoothFlag && intel->strict_conformance) { + intel->draw_point = intel_fallback_point; + index |= INTEL_FALLBACK_BIT; } if (intel->RenderIndex != index) { @@ -845,6 +848,21 @@ intelChooseRenderState(GLcontext * ctx) } } + +const struct intel_tracked_state intel_update_render_index = { + .dirty = { + .mesa = (_NEW_LINE | + _NEW_POLYGON | + _NEW_LIGHT | + _NEW_POLYGONSTIPPLE), + + .intel = INTEL_NEW_FRAGMENT_PROGRAM, + .extra = 0 + }, + .update = update_render_index +}; + + static const GLenum reduced_prim[GL_POLYGON + 1] = { GL_POINTS, GL_LINES, @@ -876,18 +894,7 @@ intelRunPipeline(GLcontext * ctx) if (ctx->NewState) _mesa_update_state_locked(ctx); - if (intel->NewGLState) { - if (intel->NewGLState & _NEW_TEXTURE) { - intel->vtbl.update_texture_state(intel); - } - - if (!intel->Fallback) { - if (intel->NewGLState & _INTEL_NEW_RENDERSTATE) - intelChooseRenderState(ctx); - } - - intel->NewGLState = 0; - } + intel_emit_state( intel ); _tnl_run_pipeline(ctx); @@ -899,8 +906,7 @@ intelRenderStart(GLcontext * ctx) { struct intel_context *intel = intel_context(ctx); - intel->vtbl.render_start(intel_context(ctx)); - intel->vtbl.emit_state(intel); + intel_emit_state(intel); } static void @@ -929,7 +935,12 @@ intelRasterPrimitive(GLcontext * ctx, GLenum rprim, GLuint hwprim) fprintf(stderr, "%s %s %x\n", __FUNCTION__, _mesa_lookup_enum_by_nr(rprim), hwprim); - intel->vtbl.reduced_primitive_state(intel, rprim); + if (intel->reduced_primitive != rprim) { + INTEL_FIREVERTICES(intel); + + intel->reduced_primitive = rprim; + intel->state.dirty.intel |= INTEL_NEW_REDUCED_PRIMITIVE; + } /* Start a new primitive. Arrange to have it flushed later on. */ @@ -1023,6 +1034,7 @@ intelFallback(struct intel_context *intel, GLuint bit, GLboolean mode) bit, getFallbackString(bit)); _swsetup_Wakeup(ctx); intel->RenderIndex = ~0; + intel->state.dirty.intel |= INTEL_NEW_FALLBACK; } } else { @@ -1045,7 +1057,7 @@ intelFallback(struct intel_context *intel, GLuint bit, GLboolean mode) intel->vertex_attr_count, intel->ViewportMatrix.m, 0); - intel->NewGLState |= _INTEL_NEW_RENDERSTATE; + intel->state.dirty.intel |= INTEL_NEW_FALLBACK; } } } @@ -1060,65 +1072,6 @@ union fi /**********************************************************************/ /* Used only with the metaops callbacks. */ /**********************************************************************/ -void -intel_meta_draw_poly(struct intel_context *intel, - GLuint n, - GLfloat xy[][2], - GLfloat z, GLuint color, GLfloat tex[][2]) -{ - union fi *vb; - GLint i; - - /* All 3d primitives should be emitted with INTEL_BATCH_CLIPRECTS, - * otherwise the drawing origin (DR4) might not be set correctly. - */ - intelStartInlinePrimitive(intel, PRIM3D_TRIFAN, INTEL_BATCH_CLIPRECTS); - vb = (union fi *) intelExtendInlinePrimitive(intel, n * 6); - - for (i = 0; i < n; i++) { - vb[0].f = xy[i][0]; - vb[1].f = xy[i][1]; - vb[2].f = z; - vb[3].i = color; - vb[4].f = tex[i][0]; - vb[5].f = tex[i][1]; - vb += 6; - } - - INTEL_FIREVERTICES(intel); -} - -void -intel_meta_draw_quad(struct intel_context *intel, - GLfloat x0, GLfloat x1, - GLfloat y0, GLfloat y1, - GLfloat z, - GLuint color, - GLfloat s0, GLfloat s1, GLfloat t0, GLfloat t1) -{ - GLfloat xy[4][2]; - GLfloat tex[4][2]; - - xy[0][0] = x0; - xy[0][1] = y0; - xy[1][0] = x1; - xy[1][1] = y0; - xy[2][0] = x1; - xy[2][1] = y1; - xy[3][0] = x0; - xy[3][1] = y1; - - tex[0][0] = s0; - tex[0][1] = t0; - tex[1][0] = s1; - tex[1][1] = t0; - tex[2][0] = s1; - tex[2][1] = t1; - tex[3][0] = s0; - tex[3][1] = t1; - - intel_meta_draw_poly(intel, 4, xy, z, color, tex); -} diff --git a/src/mesa/drivers/dri/i915tex/intel_tris.h b/src/mesa/drivers/dri/i915tex/intel_tris.h index b7bae8cd3b..9ea5520c77 100644 --- a/src/mesa/drivers/dri/i915tex/intel_tris.h +++ b/src/mesa/drivers/dri/i915tex/intel_tris.h @@ -32,14 +32,6 @@ -#define _INTEL_NEW_RENDERSTATE (_DD_NEW_LINE_STIPPLE | \ - _DD_NEW_TRI_UNFILLED | \ - _DD_NEW_TRI_LIGHT_TWOSIDE | \ - _DD_NEW_TRI_OFFSET | \ - _DD_NEW_TRI_STIPPLE | \ - _NEW_PROGRAM | \ - _NEW_POLYGONSTIPPLE) - extern void intelInitTriFuncs(GLcontext * ctx); extern void intelChooseRenderState(GLcontext * ctx); @@ -51,19 +43,4 @@ extern void intelWrapInlinePrimitive(struct intel_context *intel); GLuint *intelExtendInlinePrimitive(struct intel_context *intel, GLuint dwords); - -void intel_meta_draw_quad(struct intel_context *intel, - GLfloat x0, GLfloat x1, - GLfloat y0, GLfloat y1, - GLfloat z, - GLuint color, - GLfloat s0, GLfloat s1, GLfloat t0, GLfloat t1); - -void intel_meta_draw_poly(struct intel_context *intel, - GLuint n, - GLfloat xy[][2], - GLfloat z, GLuint color, GLfloat tex[][2]); - - - #endif |