diff options
Diffstat (limited to 'bsd/r128')
| -rw-r--r-- | bsd/r128/Makefile | 20 | ||||
| -rw-r--r-- | bsd/r128/r128_cce.c | 1024 | ||||
| -rw-r--r-- | bsd/r128/r128_drv.c | 153 | ||||
| -rw-r--r-- | bsd/r128/r128_state.c | 1572 |
4 files changed, 12 insertions, 2757 deletions
diff --git a/bsd/r128/Makefile b/bsd/r128/Makefile index ae5622ed3..99b728bc5 100644 --- a/bsd/r128/Makefile +++ b/bsd/r128/Makefile @@ -1,9 +1,10 @@ # $FreeBSD$ +.PATH: ${.CURDIR}/.. KMOD = r128 NOMAN= YES SRCS = r128_cce.c r128_drv.c r128_state.c -SRCS += device_if.h bus_if.h pci_if.h opt_drm_linux.h +SRCS += device_if.h bus_if.h pci_if.h opt_drm.h CFLAGS += ${DEBUG_FLAGS} -I. -I.. @: @@ -12,14 +13,17 @@ CFLAGS += ${DEBUG_FLAGS} -I. -I.. machine: ln -sf /sys/i386/include machine -.if ${MACHINE_ARCH} == "i386" -# This line enables linux ioctl handling -# If you want support for this uncomment this line -#R128_OPTS= "\#define DRM_LINUX" 1 +.if defined(DRM_DEBUG) +DRM_DEBUG_OPT= "\#define DRM_DEBUG 1" .endif -opt_drm_linux.h: - touch opt_drm_linux.h - echo $(R128_OPTS) >> opt_drm_linux.h +.if !defined(DRM_NOLINUX) +DRM_LINUX_OPT= "\#define DRM_LINUX 1" +.endif + +opt_drm.h: + touch opt_drm.h + echo $(DRM_DEBUG_OPT) >> opt_drm.h + echo $(DRM_LINUX_OPT) >> opt_drm.h .include <bsd.kmod.mk> diff --git a/bsd/r128/r128_cce.c b/bsd/r128/r128_cce.c deleted file mode 100644 index 36cc31206..000000000 --- a/bsd/r128/r128_cce.c +++ /dev/null @@ -1,1024 +0,0 @@ -/* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*- - * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com - * - * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Gareth Hughes <gareth@valinux.com> - */ - -#define __NO_VERSION__ -#include "r128.h" -#include "drmP.h" -#include "drm.h" -#include "r128_drm.h" -#include "r128_drv.h" - - -#define R128_FIFO_DEBUG 0 - -int r128_do_wait_for_idle( drm_r128_private_t *dev_priv ); - -/* CCE microcode (from ATI) */ -static u32 r128_cce_microcode[] = { - 0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0, - 1617039951, 0, 774592877, 0, 1987540286, 0, 2307490946U, 0, - 599558925, 0, 589505315, 0, 596487092, 0, 589505315, 1, - 11544576, 1, 206848, 1, 311296, 1, 198656, 2, 912273422, 11, - 262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, 28, - 1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9, - 30, 1, 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656, - 1, 15630, 1, 51200, 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1, - 15717, 1, 15718, 2, 43, 1, 15936948, 1, 570480831, 1, 14715071, - 12, 322123831, 1, 33953125, 12, 55, 1, 33559908, 1, 15718, 2, - 46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, 509952, 1, - 459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1, - 18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1, - 15975928, 1, 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2, - 268449859, 2, 10307, 12, 176, 1, 15734, 1, 15735, 1, 15630, 1, - 15631, 1, 5253120, 6, 3145810, 16, 2150645232U, 1, 15864, 2, 82, - 1, 343310, 1, 1064207, 2, 3145813, 1, 15728, 1, 7817, 1, 15729, - 3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, 1, 16008, - 1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0, - 15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1, - 180224, 1, 103824738, 2, 112, 2, 3145839, 0, 536885440, 1, - 114880, 14, 125, 12, 206975, 1, 33559995, 12, 198784, 0, - 33570236, 1, 15803, 0, 15804, 3, 294912, 1, 294912, 3, 442370, - 1, 11544576, 0, 811612160, 1, 12593152, 1, 11536384, 1, - 14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, 14793, - 1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1, - 198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1, - 114880, 14, 159, 12, 198784, 1, 1109409213, 12, 198783, 1, - 1107312059, 12, 198784, 1, 1109409212, 2, 162, 1, 1075854781, 1, - 1073757627, 1, 1075854780, 1, 540672, 1, 10485760, 6, 3145894, - 16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, 0, 0, 256, 14, - 174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, 1, - 33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1, - 33560360, 1, 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1, - 409611, 9, 188, 0, 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -}; - - -int R128_READ_PLL(drm_device_t *dev, int addr) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - - R128_WRITE8(R128_CLOCK_CNTL_INDEX, addr & 0x1f); - return R128_READ(R128_CLOCK_CNTL_DATA); -} - -#if R128_FIFO_DEBUG -static void r128_status( drm_r128_private_t *dev_priv ) -{ - printk( "GUI_STAT = 0x%08x\n", - (unsigned int)R128_READ( R128_GUI_STAT ) ); - printk( "PM4_STAT = 0x%08x\n", - (unsigned int)R128_READ( R128_PM4_STAT ) ); - printk( "PM4_BUFFER_DL_WPTR = 0x%08x\n", - (unsigned int)R128_READ( R128_PM4_BUFFER_DL_WPTR ) ); - printk( "PM4_BUFFER_DL_RPTR = 0x%08x\n", - (unsigned int)R128_READ( R128_PM4_BUFFER_DL_RPTR ) ); - printk( "PM4_MICRO_CNTL = 0x%08x\n", - (unsigned int)R128_READ( R128_PM4_MICRO_CNTL ) ); - printk( "PM4_BUFFER_CNTL = 0x%08x\n", - (unsigned int)R128_READ( R128_PM4_BUFFER_CNTL ) ); -} -#endif - - -/* ================================================================ - * Engine, FIFO control - */ - -static int r128_do_pixcache_flush( drm_r128_private_t *dev_priv ) -{ - u32 tmp; - int i; - - tmp = R128_READ( R128_PC_NGUI_CTLSTAT ) | R128_PC_FLUSH_ALL; - R128_WRITE( R128_PC_NGUI_CTLSTAT, tmp ); - - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - if ( !(R128_READ( R128_PC_NGUI_CTLSTAT ) & R128_PC_BUSY) ) { - return 0; - } - DRM_OS_DELAY( 1 ); - } - -#if R128_FIFO_DEBUG - DRM_ERROR( "%s failed!\n", __FUNCTION__ ); -#endif - DRM_OS_RETURN( EBUSY ); -} - -static int r128_do_wait_for_fifo( drm_r128_private_t *dev_priv, int entries ) -{ - int i; - - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - int slots = R128_READ( R128_GUI_STAT ) & R128_GUI_FIFOCNT_MASK; - if ( slots >= entries ) return 0; - DRM_OS_DELAY( 1 ); - } - -#if R128_FIFO_DEBUG - DRM_ERROR( "%s failed!\n", __FUNCTION__ ); -#endif - DRM_OS_RETURN( EBUSY ); -} - -int r128_do_wait_for_idle( drm_r128_private_t *dev_priv ) -{ - int i, ret; - - ret = r128_do_wait_for_fifo( dev_priv, 64 ); - if ( ret ) return ret; - - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - if ( !(R128_READ( R128_GUI_STAT ) & R128_GUI_ACTIVE) ) { - r128_do_pixcache_flush( dev_priv ); - return 0; - } - DRM_OS_DELAY( 1 ); - } - -#if R128_FIFO_DEBUG - DRM_ERROR( "%s failed!\n", __FUNCTION__ ); -#endif - DRM_OS_RETURN( EBUSY ); -} - - -/* ================================================================ - * CCE control, initialization - */ - -/* Load the microcode for the CCE */ -static void r128_cce_load_microcode( drm_r128_private_t *dev_priv ) -{ - int i; - - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - r128_do_wait_for_idle( dev_priv ); - - R128_WRITE( R128_PM4_MICROCODE_ADDR, 0 ); - for ( i = 0 ; i < 256 ; i++ ) { - R128_WRITE( R128_PM4_MICROCODE_DATAH, - r128_cce_microcode[i * 2] ); - R128_WRITE( R128_PM4_MICROCODE_DATAL, - r128_cce_microcode[i * 2 + 1] ); - } -} - -/* Flush any pending commands to the CCE. This should only be used just - * prior to a wait for idle, as it informs the engine that the command - * stream is ending. - */ -static void r128_do_cce_flush( drm_r128_private_t *dev_priv ) -{ - u32 tmp; - - tmp = R128_READ( R128_PM4_BUFFER_DL_WPTR ) | R128_PM4_BUFFER_DL_DONE; - R128_WRITE( R128_PM4_BUFFER_DL_WPTR, tmp ); -} - -/* Wait for the CCE to go idle. - */ -int r128_do_cce_idle( drm_r128_private_t *dev_priv ) -{ - int i; - - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - if ( GET_RING_HEAD( &dev_priv->ring ) == dev_priv->ring.tail ) { - int pm4stat = R128_READ( R128_PM4_STAT ); - if ( ( (pm4stat & R128_PM4_FIFOCNT_MASK) >= - dev_priv->cce_fifo_size ) && - !(pm4stat & (R128_PM4_BUSY | - R128_PM4_GUI_ACTIVE)) ) { - return r128_do_pixcache_flush( dev_priv ); - } - } - DRM_OS_DELAY( 1 ); - } - -#if R128_FIFO_DEBUG - DRM_ERROR( "failed!\n" ); - r128_status( dev_priv ); -#endif - DRM_OS_RETURN( EBUSY ); -} - -/* Start the Concurrent Command Engine. - */ -static void r128_do_cce_start( drm_r128_private_t *dev_priv ) -{ - r128_do_wait_for_idle( dev_priv ); - - R128_WRITE( R128_PM4_BUFFER_CNTL, - dev_priv->cce_mode | dev_priv->ring.size_l2qw ); - R128_READ( R128_PM4_BUFFER_ADDR ); /* as per the sample code */ - R128_WRITE( R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN ); - - dev_priv->cce_running = 1; -} - -/* Reset the Concurrent Command Engine. This will not flush any pending - * commands, so you must wait for the CCE command stream to complete - * before calling this routine. - */ -static void r128_do_cce_reset( drm_r128_private_t *dev_priv ) -{ - R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 ); - R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 ); - SET_RING_HEAD( &dev_priv->ring, 0 ); - dev_priv->ring.tail = 0; -} - -/* Stop the Concurrent Command Engine. This will not flush any pending - * commands, so you must flush the command stream and wait for the CCE - * to go idle before calling this routine. - */ -static void r128_do_cce_stop( drm_r128_private_t *dev_priv ) -{ - R128_WRITE( R128_PM4_MICRO_CNTL, 0 ); - R128_WRITE( R128_PM4_BUFFER_CNTL, R128_PM4_NONPM4 ); - - dev_priv->cce_running = 0; -} - -/* Reset the engine. This will stop the CCE if it is running. - */ -static int r128_do_engine_reset( drm_device_t *dev ) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - u32 clock_cntl_index, mclk_cntl, gen_reset_cntl; - - r128_do_pixcache_flush( dev_priv ); - - clock_cntl_index = R128_READ( R128_CLOCK_CNTL_INDEX ); - mclk_cntl = R128_READ_PLL( dev, R128_MCLK_CNTL ); - - R128_WRITE_PLL( R128_MCLK_CNTL, - mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP ); - - gen_reset_cntl = R128_READ( R128_GEN_RESET_CNTL ); - - /* Taken from the sample code - do not change */ - R128_WRITE( R128_GEN_RESET_CNTL, - gen_reset_cntl | R128_SOFT_RESET_GUI ); - R128_READ( R128_GEN_RESET_CNTL ); - R128_WRITE( R128_GEN_RESET_CNTL, - gen_reset_cntl & ~R128_SOFT_RESET_GUI ); - R128_READ( R128_GEN_RESET_CNTL ); - - R128_WRITE_PLL( R128_MCLK_CNTL, mclk_cntl ); - R128_WRITE( R128_CLOCK_CNTL_INDEX, clock_cntl_index ); - R128_WRITE( R128_GEN_RESET_CNTL, gen_reset_cntl ); - - /* Reset the CCE ring */ - r128_do_cce_reset( dev_priv ); - - /* The CCE is no longer running after an engine reset */ - dev_priv->cce_running = 0; - - /* Reset any pending vertex, indirect buffers */ - r128_freelist_reset( dev ); - - return 0; -} - -static void r128_cce_init_ring_buffer( drm_device_t *dev, - drm_r128_private_t *dev_priv ) -{ - u32 ring_start; - u32 tmp; - - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - /* The manual (p. 2) says this address is in "VM space". This - * means it's an offset from the start of AGP space. - */ -#if __REALLY_HAVE_AGP - if ( !dev_priv->is_pci ) - ring_start = dev_priv->cce_ring->offset - dev->agp->base; - else -#endif - ring_start = dev_priv->cce_ring->offset - dev->sg->handle; - - R128_WRITE( R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET ); - - R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 ); - R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 ); - - /* DL_RPTR_ADDR is a physical address in AGP space. */ - SET_RING_HEAD( &dev_priv->ring, 0 ); - -#if __REALLY_HAVE_SG - if ( !dev_priv->is_pci ) { -#endif - R128_WRITE( R128_PM4_BUFFER_DL_RPTR_ADDR, - dev_priv->ring_rptr->offset ); -#if __REALLY_HAVE_SG - } else { - drm_sg_mem_t *entry = dev->sg; - unsigned long tmp_ofs, page_ofs; - - tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle; - page_ofs = tmp_ofs >> PAGE_SHIFT; - - R128_WRITE( R128_PM4_BUFFER_DL_RPTR_ADDR, - entry->busaddr[page_ofs]); - DRM_DEBUG( "ring rptr: offset=0x%08x handle=0x%08lx\n", - entry->busaddr[page_ofs], - entry->handle + tmp_ofs ); - } -#endif - - /* Set watermark control */ - R128_WRITE( R128_PM4_BUFFER_WM_CNTL, - ((R128_WATERMARK_L/4) << R128_WMA_SHIFT) - | ((R128_WATERMARK_M/4) << R128_WMB_SHIFT) - | ((R128_WATERMARK_N/4) << R128_WMC_SHIFT) - | ((R128_WATERMARK_K/64) << R128_WB_WM_SHIFT) ); - - /* Force read. Why? Because it's in the examples... */ - R128_READ( R128_PM4_BUFFER_ADDR ); - - /* Turn on bus mastering */ - tmp = R128_READ( R128_BUS_CNTL ) & ~R128_BUS_MASTER_DIS; - R128_WRITE( R128_BUS_CNTL, tmp ); -} - -static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init ) -{ - drm_r128_private_t *dev_priv; - drm_map_list_entry_t *listentry; - - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - dev_priv = DRM(alloc)( sizeof(drm_r128_private_t), DRM_MEM_DRIVER ); - if ( dev_priv == NULL ) - DRM_OS_RETURN( ENOMEM ); - - memset( dev_priv, 0, sizeof(drm_r128_private_t) ); - - dev_priv->is_pci = init->is_pci; - - if ( dev_priv->is_pci && !dev->sg ) { - DRM_ERROR( "PCI GART memory not allocated!\n" ); - dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); - DRM_OS_RETURN( EINVAL ); - } - - dev_priv->usec_timeout = init->usec_timeout; - if ( dev_priv->usec_timeout < 1 || - dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT ) { - DRM_DEBUG( "TIMEOUT problem!\n" ); - dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); - DRM_OS_RETURN( EINVAL ); - } - - dev_priv->cce_mode = init->cce_mode; - - /* GH: Simple idle check. - */ - atomic_set( &dev_priv->idle_count, 0 ); - - /* We don't support anything other than bus-mastering ring mode, - * but the ring can be in either AGP or PCI space for the ring - * read pointer. - */ - if ( ( init->cce_mode != R128_PM4_192BM ) && - ( init->cce_mode != R128_PM4_128BM_64INDBM ) && - ( init->cce_mode != R128_PM4_64BM_128INDBM ) && - ( init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM ) ) { - DRM_DEBUG( "Bad cce_mode!\n" ); - dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); - DRM_OS_RETURN( EINVAL ); - } - - switch ( init->cce_mode ) { - case R128_PM4_NONPM4: - dev_priv->cce_fifo_size = 0; - break; - case R128_PM4_192PIO: - case R128_PM4_192BM: - dev_priv->cce_fifo_size = 192; - break; - case R128_PM4_128PIO_64INDBM: - case R128_PM4_128BM_64INDBM: - dev_priv->cce_fifo_size = 128; - break; - case R128_PM4_64PIO_128INDBM: - case R128_PM4_64BM_128INDBM: - case R128_PM4_64PIO_64VCBM_64INDBM: - case R128_PM4_64BM_64VCBM_64INDBM: - case R128_PM4_64PIO_64VCPIO_64INDPIO: - dev_priv->cce_fifo_size = 64; - break; - } - - switch ( init->fb_bpp ) { - case 16: - dev_priv->color_fmt = R128_DATATYPE_RGB565; - break; - case 32: - default: - dev_priv->color_fmt = R128_DATATYPE_ARGB8888; - break; - } - dev_priv->front_offset = init->front_offset; - dev_priv->front_pitch = init->front_pitch; - dev_priv->back_offset = init->back_offset; - dev_priv->back_pitch = init->back_pitch; - - switch ( init->depth_bpp ) { - case 16: - dev_priv->depth_fmt = R128_DATATYPE_RGB565; - break; - case 24: - case 32: - default: - dev_priv->depth_fmt = R128_DATATYPE_ARGB8888; - break; - } - dev_priv->depth_offset = init->depth_offset; - dev_priv->depth_pitch = init->depth_pitch; - dev_priv->span_offset = init->span_offset; - - dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch/8) << 21) | - (dev_priv->front_offset >> 5)); - dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch/8) << 21) | - (dev_priv->back_offset >> 5)); - dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) | - (dev_priv->depth_offset >> 5) | - R128_DST_TILE); - dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) | - (dev_priv->span_offset >> 5)); - - TAILQ_FOREACH(listentry, dev->maplist, link) { - drm_map_t *map = listentry->map; - if (map->type == _DRM_SHM && - map->flags & _DRM_CONTAINS_LOCK) { - dev_priv->sarea = map; - break; - } - } - - if(!dev_priv->sarea) { - DRM_ERROR("could not find sarea!\n"); - dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); - DRM_OS_RETURN(EINVAL); - } - - DRM_FIND_MAP( dev_priv->fb, init->fb_offset ); - if(!dev_priv->fb) { - DRM_ERROR("could not find framebuffer!\n"); - dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); - DRM_OS_RETURN(EINVAL); - } - DRM_FIND_MAP( dev_priv->mmio, init->mmio_offset ); - if(!dev_priv->mmio) { - DRM_ERROR("could not find mmio region!\n"); - dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); - DRM_OS_RETURN(EINVAL); - } - DRM_FIND_MAP( dev_priv->cce_ring, init->ring_offset ); - if(!dev_priv->cce_ring) { - DRM_ERROR("could not find cce ring region!\n"); - dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); - DRM_OS_RETURN(EINVAL); - } - DRM_FIND_MAP( dev_priv->ring_rptr, init->ring_rptr_offset ); - if(!dev_priv->ring_rptr) { - DRM_ERROR("could not find ring read pointer!\n"); - dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); - DRM_OS_RETURN(EINVAL); - } - DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset ); - if(!dev_priv->buffers) { - DRM_ERROR("could not find dma buffer region!\n"); - dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); - DRM_OS_RETURN(EINVAL); - } - - if ( !dev_priv->is_pci ) { - DRM_FIND_MAP( dev_priv->agp_textures, - init->agp_textures_offset ); - if(!dev_priv->agp_textures) { - DRM_ERROR("could not find agp texture region!\n"); - dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); - DRM_OS_RETURN(EINVAL); - } - } - - dev_priv->sarea_priv = - (drm_r128_sarea_t *)((u8 *)dev_priv->sarea->handle + - init->sarea_priv_offset); - - if ( !dev_priv->is_pci ) { - DRM_IOREMAP( dev_priv->cce_ring ); - DRM_IOREMAP( dev_priv->ring_rptr ); - DRM_IOREMAP( dev_priv->buffers ); - if(!dev_priv->cce_ring->handle || - !dev_priv->ring_rptr->handle || - !dev_priv->buffers->handle) { - DRM_ERROR("Could not ioremap agp regions!\n"); - dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); - DRM_OS_RETURN(ENOMEM); - } - } else { - dev_priv->cce_ring->handle = - (void *)dev_priv->cce_ring->offset; - dev_priv->ring_rptr->handle = - (void *)dev_priv->ring_rptr->offset; - dev_priv->buffers->handle = (void *)dev_priv->buffers->offset; - } - -#if __REALLY_HAVE_AGP - if ( !dev_priv->is_pci ) - dev_priv->cce_buffers_offset = dev->agp->base; - else -#endif - dev_priv->cce_buffers_offset = dev->sg->handle; - - dev_priv->ring.head = ((__volatile__ u32 *) - dev_priv->ring_rptr->handle); - - dev_priv->ring.start = (u32 *)dev_priv->cce_ring->handle; - dev_priv->ring.end = ((u32 *)dev_priv->cce_ring->handle - + init->ring_size / sizeof(u32)); - dev_priv->ring.size = init->ring_size; - dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 ); - - dev_priv->ring.tail_mask = - (dev_priv->ring.size / sizeof(u32)) - 1; - - dev_priv->ring.high_mark = 128; - - dev_priv->sarea_priv->last_frame = 0; - R128_WRITE( R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame ); - - dev_priv->sarea_priv->last_dispatch = 0; - R128_WRITE( R128_LAST_DISPATCH_REG, - dev_priv->sarea_priv->last_dispatch ); - -#if __REALLY_HAVE_SG - if ( dev_priv->is_pci ) { - if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart, - &dev_priv->bus_pci_gart) ) { - DRM_ERROR( "failed to init PCI GART!\n" ); - dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); - DRM_OS_RETURN(ENOMEM); - } - R128_WRITE( R128_PCI_GART_PAGE, dev_priv->bus_pci_gart ); - } -#endif - - r128_cce_init_ring_buffer( dev, dev_priv ); - r128_cce_load_microcode( dev_priv ); - - dev->dev_private = (void *)dev_priv; - - r128_do_engine_reset( dev ); - - return 0; -} - -int r128_do_cleanup_cce( drm_device_t *dev ) -{ - if ( dev->dev_private ) { - drm_r128_private_t *dev_priv = dev->dev_private; - -#if __REALLY_HAVE_SG - if ( !dev_priv->is_pci ) { -#endif - DRM_IOREMAPFREE( dev_priv->cce_ring ); - DRM_IOREMAPFREE( dev_priv->ring_rptr ); - DRM_IOREMAPFREE( dev_priv->buffers ); -#if __REALLY_HAVE_SG - } else { - if (!DRM(ati_pcigart_cleanup)( dev, - dev_priv->phys_pci_gart, - dev_priv->bus_pci_gart )) - DRM_ERROR( "failed to cleanup PCI GART!\n" ); - } -#endif - - DRM(free)( dev->dev_private, sizeof(drm_r128_private_t), - DRM_MEM_DRIVER ); - dev->dev_private = NULL; - } - - return 0; -} - -int r128_cce_init( DRM_OS_IOCTL ) -{ - DRM_OS_DEVICE; - drm_r128_init_t init; - - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - DRM_OS_KRNFROMUSR( init, (drm_r128_init_t *)data, sizeof(init) ); - - switch ( init.func ) { - case R128_INIT_CCE: - return r128_do_init_cce( dev, &init ); - case R128_CLEANUP_CCE: - return r128_do_cleanup_cce( dev ); - } - - DRM_OS_RETURN( EINVAL ); -} - -int r128_cce_start( DRM_OS_IOCTL ) -{ - DRM_OS_DEVICE; - drm_r128_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - LOCK_TEST_WITH_RETURN( dev ); - - if ( dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4 ) { - DRM_DEBUG( "%s while CCE running\n", __FUNCTION__ ); - return 0; - } - - r128_do_cce_start( dev_priv ); - - return 0; -} - -/* Stop the CCE. The engine must have been idled before calling this - * routine. - */ -int r128_cce_stop( DRM_OS_IOCTL ) -{ - DRM_OS_DEVICE; - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_cce_stop_t stop; - int ret; - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - LOCK_TEST_WITH_RETURN( dev ); - - DRM_OS_KRNFROMUSR(stop, (drm_r128_cce_stop_t *)data, sizeof(stop) ); - - /* Flush any pending CCE commands. This ensures any outstanding - * commands are exectuted by the engine before we turn it off. - */ - if ( stop.flush ) { - r128_do_cce_flush( dev_priv ); - } - - /* If we fail to make the engine go idle, we return an error - * code so that the DRM ioctl wrapper can try again. - */ - if ( stop.idle ) { - ret = r128_do_cce_idle( dev_priv ); - if ( ret ) return ret; - } - - /* Finally, we can turn off the CCE. If the engine isn't idle, - * we will get some dropped triangles as they won't be fully - * rendered before the CCE is shut down. - */ - r128_do_cce_stop( dev_priv ); - - /* Reset the engine */ - r128_do_engine_reset( dev ); - - return 0; -} - -/* Just reset the CCE ring. Called as part of an X Server engine reset. - */ -int r128_cce_reset( DRM_OS_IOCTL ) -{ - DRM_OS_DEVICE; - drm_r128_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - LOCK_TEST_WITH_RETURN( dev ); - - if ( !dev_priv ) { - DRM_DEBUG( "%s called before init done\n", __FUNCTION__ ); - DRM_OS_RETURN( EINVAL ); - } - - r128_do_cce_reset( dev_priv ); - - /* The CCE is no longer running after an engine reset */ - dev_priv->cce_running = 0; - - return 0; -} - -int r128_cce_idle( DRM_OS_IOCTL ) -{ - DRM_OS_DEVICE; - drm_r128_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - LOCK_TEST_WITH_RETURN( dev ); - - if ( dev_priv->cce_running ) { - r128_do_cce_flush( dev_priv ); - } - - return r128_do_cce_idle( dev_priv ); -} - -int r128_engine_reset( DRM_OS_IOCTL ) -{ - DRM_OS_DEVICE; - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - LOCK_TEST_WITH_RETURN( dev ); - - return r128_do_engine_reset( dev ); -} - - -/* ================================================================ - * Fullscreen mode - */ - -static int r128_do_init_pageflip( drm_device_t *dev ) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - dev_priv->crtc_offset = R128_READ( R128_CRTC_OFFSET ); - dev_priv->crtc_offset_cntl = R128_READ( R128_CRTC_OFFSET_CNTL ); - - R128_WRITE( R128_CRTC_OFFSET, dev_priv->front_offset ); - R128_WRITE( R128_CRTC_OFFSET_CNTL, - dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL ); - - dev_priv->page_flipping = 1; - dev_priv->current_page = 0; - - return 0; -} - -int r128_do_cleanup_pageflip( drm_device_t *dev ) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - R128_WRITE( R128_CRTC_OFFSET, dev_priv->crtc_offset ); - R128_WRITE( R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl ); - - dev_priv->page_flipping = 0; - dev_priv->current_page = 0; - - return 0; -} - -int r128_fullscreen( DRM_OS_IOCTL ) -{ - DRM_OS_DEVICE; - drm_r128_fullscreen_t fs; - - LOCK_TEST_WITH_RETURN( dev ); - - DRM_OS_KRNFROMUSR( fs, (drm_r128_fullscreen_t *)data, sizeof(fs) ); - - switch ( fs.func ) { - case R128_INIT_FULLSCREEN: - return r128_do_init_pageflip( dev ); - case R128_CLEANUP_FULLSCREEN: - return r128_do_cleanup_pageflip( dev ); - } - - DRM_OS_RETURN( EINVAL ); -} - - -/* ================================================================ - * Freelist management - */ -#define R128_BUFFER_USED 0xffffffff -#define R128_BUFFER_FREE 0 - -#if 0 -static int r128_freelist_init( drm_device_t *dev ) -{ - drm_device_dma_t *dma = dev->dma; - drm_r128_private_t *dev_priv = dev->dev_private; - drm_buf_t *buf; - drm_r128_buf_priv_t *buf_priv; - drm_r128_freelist_t *entry; - int i; - - dev_priv->head = DRM(alloc)( sizeof(drm_r128_freelist_t), - DRM_MEM_DRIVER ); - if ( dev_priv->head == NULL ) - DRM_OS_RETURN( ENOMEM ); - - memset( dev_priv->head, 0, sizeof(drm_r128_freelist_t) ); - dev_priv->head->age = R128_BUFFER_USED; - - for ( i = 0 ; i < dma->buf_count ; i++ ) { - buf = dma->buflist[i]; - buf_priv = buf->dev_private; - - entry = DRM(alloc)( sizeof(drm_r128_freelist_t), - DRM_MEM_DRIVER ); - if ( !entry ) DRM_OS_RETURN( ENOMEM ); - - entry->age = R128_BUFFER_FREE; - entry->buf = buf; - entry->prev = dev_priv->head; - entry->next = dev_priv->head->next; - if ( !entry->next ) - dev_priv->tail = entry; - - buf_priv->discard = 0; - buf_priv->dispatched = 0; - buf_priv->list_entry = entry; - - dev_priv->head->next = entry; - - if ( dev_priv->head->next ) - dev_priv->head->next->prev = entry; - } - - return 0; - -} -#endif - -drm_buf_t *r128_freelist_get( drm_device_t *dev ) -{ - drm_device_dma_t *dma = dev->dma; - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_buf_priv_t *buf_priv; - drm_buf_t *buf; - int i, t; - - /* FIXME: Optimize -- use freelist code */ - - for ( i = 0 ; i < dma->buf_count ; i++ ) { - buf = dma->buflist[i]; - buf_priv = buf->dev_private; - if ( buf->pid == 0 ) - return buf; - } - - for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) { - u32 done_age = R128_READ( R128_LAST_DISPATCH_REG ); - - for ( i = 0 ; i < dma->buf_count ; i++ ) { - buf = dma->buflist[i]; - buf_priv = buf->dev_private; - if ( buf->pending && buf_priv->age <= done_age ) { - /* The buffer has been processed, so it - * can now be used. - */ - buf->pending = 0; - return buf; - } - } - DRM_OS_DELAY( 1 ); - } - - DRM_ERROR( "returning NULL!\n" ); - return NULL; -} - -void r128_freelist_reset( drm_device_t *dev ) -{ - drm_device_dma_t *dma = dev->dma; - int i; - - for ( i = 0 ; i < dma->buf_count ; i++ ) { - drm_buf_t *buf = dma->buflist[i]; - drm_r128_buf_priv_t *buf_priv = buf->dev_private; - buf_priv->age = 0; - } -} - - -/* ================================================================ - * CCE command submission - */ - -int r128_wait_ring( drm_r128_private_t *dev_priv, int n ) -{ - drm_r128_ring_buffer_t *ring = &dev_priv->ring; - int i; - - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - r128_update_ring_snapshot( ring ); - if ( ring->space >= n ) - return 0; - DRM_OS_DELAY( 1 ); - } - - /* FIXME: This is being ignored... */ - DRM_ERROR( "failed!\n" ); - DRM_OS_RETURN( EBUSY ); -} - -static int r128_cce_get_buffers( drm_device_t *dev, drm_dma_t *d) -{ - int i; - drm_buf_t *buf; - - for ( i = d->granted_count ; i < d->request_count ; i++ ) { - buf = r128_freelist_get( dev ); - if ( !buf ) DRM_OS_RETURN( EAGAIN ); - - buf->pid = DRM_OS_CURRENTPID; - - if ( DRM_OS_COPYTOUSR( &d->request_indices[i], &buf->idx, - sizeof(buf->idx) ) ) - DRM_OS_RETURN( EFAULT ); - if ( DRM_OS_COPYTOUSR( &d->request_sizes[i], &buf->total, - sizeof(buf->total) ) ) - DRM_OS_RETURN( EFAULT ); - d->granted_count++; - } - return 0; -} - -int r128_cce_buffers( DRM_OS_IOCTL ) -{ - DRM_OS_DEVICE; - drm_device_dma_t *dma = dev->dma; - int ret = 0; - drm_dma_t d; - - LOCK_TEST_WITH_RETURN( dev ); - - DRM_OS_KRNFROMUSR( d, (drm_dma_t *) data, sizeof(d) ); - - /* Please don't send us buffers. - */ - if ( d.send_count != 0 ) { - DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n", - DRM_OS_CURRENTPID, d.send_count ); - DRM_OS_RETURN( EINVAL ); - } - - /* We'll send you buffers. - */ - if ( d.request_count < 0 || d.request_count > dma->buf_count ) { - DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n", - DRM_OS_CURRENTPID, d.request_count, dma->buf_count ); - DRM_OS_RETURN( EINVAL ); - } - - d.granted_count = 0; - - if ( d.request_count ) { - ret = r128_cce_get_buffers( dev, &d ); - } - - DRM_OS_KRNTOUSR((drm_dma_t *) data, d, sizeof(d) ); - - return ret; -} diff --git a/bsd/r128/r128_drv.c b/bsd/r128/r128_drv.c deleted file mode 100644 index cf59aa0d0..000000000 --- a/bsd/r128/r128_drv.c +++ /dev/null @@ -1,153 +0,0 @@ -/* r128_drv.c -- ATI Rage 128 driver -*- linux-c -*- - * Created: Mon Dec 13 09:47:27 1999 by faith@precisioninsight.com - * - * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Rickard E. (Rik) Faith <faith@valinux.com> - * Gareth Hughes <gareth@valinux.com> - */ - - -#include <sys/types.h> -#include <sys/bus.h> -#include <pci/pcivar.h> -#include <opt_drm_linux.h> - -#include "r128.h" -#include "drmP.h" -#include "drm.h" -#include "r128_drm.h" -#include "r128_drv.h" -#if __REALLY_HAVE_SG -#include "ati_pcigart.h" -#endif - -#define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc." - -#define DRIVER_NAME "r128" -#define DRIVER_DESC "ATI Rage 128" -#define DRIVER_DATE "20010405" - -#define DRIVER_MAJOR 2 -#define DRIVER_MINOR 2 -#define DRIVER_PATCHLEVEL 0 - -/* List acquired from http://www.yourvote.com/pci/pcihdr.h and xc/xc/programs/Xserver/hw/xfree86/common/xf86PciInfo.h - * Please report to anholt@teleport.com inaccuracies or if a chip you have works that is marked unsupported here. - */ -drm_chipinfo_t DRM(devicelist)[] = { - {0x1002, 0x4c45, 1, "ATI Rage 128 Mobility LE"}, - {0x1002, 0x4c46, 1, "ATI Rage 128 Mobility LF"}, - {0x1002, 0x4d46, 1, "ATI Rage 128 Mobility MF (AGP 4x)"}, - {0x1002, 0x4d4c, 1, "ATI Rage 128 Mobility ML"}, - {0x1002, 0x5041, 0, "ATI Rage 128 Pro PA (PCI)"}, - {0x1002, 0x5042, 1, "ATI Rage 128 Pro PB (AGP 2x)"}, - {0x1002, 0x5043, 1, "ATI Rage 128 Pro PC (AGP 4x)"}, - {0x1002, 0x5044, 0, "ATI Rage 128 Pro PD (PCI)"}, - {0x1002, 0x5045, 1, "ATI Rage 128 Pro PE (AGP 2x)"}, - {0x1002, 0x5046, 1, "ATI Rage 128 Pro PF (AGP 4x)"}, - {0x1002, 0x5047, 0, "ATI Rage 128 Pro PG (PCI)"}, - {0x1002, 0x5048, 1, "ATI Rage 128 Pro PH (AGP)"}, - {0x1002, 0x5049, 1, "ATI Rage 128 Pro PI (AGP)"}, - {0x1002, 0x504a, 0, "ATI Rage 128 Pro PJ (PCI)"}, - {0x1002, 0x504b, 1, "ATI Rage 128 Pro PK (AGP)"}, - {0x1002, 0x504c, 1, "ATI Rage 128 Pro PL (AGP)"}, - {0x1002, 0x504d, 0, "ATI Rage 128 Pro PM (PCI)"}, - {0x1002, 0x504e, 1, "ATI Rage 128 Pro PN (AGP)"}, - {0x1002, 0x505f, 1, "ATI Rage 128 Pro PO (AGP)"}, - {0x1002, 0x5050, 0, "ATI Rage 128 Pro PP (PCI)"}, - {0x1002, 0x5051, 1, "ATI Rage 128 Pro PQ (AGP)"}, - {0x1002, 0x5052, 1, "ATI Rage 128 Pro PR (AGP)"}, - {0x1002, 0x5053, 0, "ATI Rage 128 Pro PS (PCI)"}, - {0x1002, 0x5054, 1, "ATI Rage 128 Pro PT (AGP)"}, - {0x1002, 0x5055, 1, "ATI Rage 128 Pro PU (AGP)"}, - {0x1002, 0x5056, 0, "ATI Rage 128 Pro PV (PCI)"}, - {0x1002, 0x5057, 1, "ATI Rage 128 Pro PW (AGP)"}, - {0x1002, 0x5058, 1, "ATI Rage 128 Pro PX (AGP)"}, - {0x1002, 0x5245, 0, "ATI Rage 128 GL (PCI)"}, - {0x1002, 0x5246, 1, "ATI Rage 128 GL (AGP 2x)"}, - {0x1002, 0x524b, 0, "ATI Rage 128 VR (PCI)"}, - {0x1002, 0x524c, 1, "ATI Rage 128 VR (AGP 2x)"}, - {0x1002, 0x5345, 0, "ATI Rage 128 SE (PCI)"}, - {0x1002, 0x5346, 1, "ATI Rage 128 SF (AGP 2x)"}, - {0x1002, 0x5347, 1, "ATI Rage 128 SG (AGP 4x)"}, - {0x1002, 0x5348, 0, "ATI Rage 128 SH (unknown)"}, - {0x1002, 0x534b, 0, "ATI Rage 128 SK (PCI)"}, - {0x1002, 0x534c, 1, "ATI Rage 128 SL (AGP 2x)"}, - {0x1002, 0x534d, 1, "ATI Rage 128 SM (AGP 4x)"}, - {0x1002, 0x534e, 1, "ATI Rage 128 (AGP 4x?)"}, - {0, 0, 0, NULL} -}; - -#define DRIVER_IOCTLS \ - [DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { r128_cce_buffers, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_R128_INIT)] = { r128_cce_init, 1, 1 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_START)] = { r128_cce_start, 1, 1 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_STOP)] = { r128_cce_stop, 1, 1 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_RESET)] = { r128_cce_reset, 1, 1 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_IDLE)] = { r128_cce_idle, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_R128_RESET)] = { r128_engine_reset, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_R128_FULLSCREEN)] = { r128_fullscreen, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_R128_SWAP)] = { r128_cce_swap, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_R128_CLEAR)] = { r128_cce_clear, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_R128_VERTEX)] = { r128_cce_vertex, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_R128_INDICES)] = { r128_cce_indices, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_R128_BLIT)] = { r128_cce_blit, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_R128_DEPTH)] = { r128_cce_depth, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_R128_STIPPLE)] = { r128_cce_stipple, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_R128_INDIRECT)] = { r128_cce_indirect, 1, 1 }, - - -#if 0 -/* GH: Count data sent to card via ring or vertex/indirect buffers. - */ -#define __HAVE_COUNTERS 3 -#define __HAVE_COUNTER6 _DRM_STAT_IRQ -#define __HAVE_COUNTER7 _DRM_STAT_PRIMARY -#define __HAVE_COUNTER8 _DRM_STAT_SECONDARY -#endif - - -#include "drm_agpsupport.h" -#include "drm_auth.h" -#include "drm_bufs.h" -#include "drm_context.h" -#include "drm_dma.h" -#include "drm_drawable.h" -#include "drm_drv.h" - - -#include "drm_fops.h" -#include "drm_init.h" -#include "drm_ioctl.h" -#include "drm_lock.h" -#include "drm_memory.h" -#include "drm_sysctl.h" -#include "drm_vm.h" -#if __REALLY_HAVE_SG -#include "drm_scatter.h" -#endif - -DRIVER_MODULE(r128, pci, r128_driver, r128_devclass, 0, 0); diff --git a/bsd/r128/r128_state.c b/bsd/r128/r128_state.c deleted file mode 100644 index 34500bb3f..000000000 --- a/bsd/r128/r128_state.c +++ /dev/null @@ -1,1572 +0,0 @@ -/* r128_state.c -- State support for r128 -*- linux-c -*- - * Created: Thu Jan 27 02:53:43 2000 by gareth@valinux.com - * - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Gareth Hughes <gareth@valinux.com> - */ - - -#include "r128.h" -#include "drmP.h" -#include "drm.h" -#include "r128_drm.h" -#include "r128_drv.h" -#include "drm.h" - - - -/* ================================================================ - * CCE hardware state programming functions - */ - -static void r128_emit_clip_rects( drm_r128_private_t *dev_priv, - drm_clip_rect_t *boxes, int count ) -{ - u32 aux_sc_cntl = 0x00000000; - RING_LOCALS; - DRM_DEBUG( " %s\n", __FUNCTION__ ); - - BEGIN_RING( 17 ); - - if ( count >= 1 ) { - OUT_RING( CCE_PACKET0( R128_AUX1_SC_LEFT, 3 ) ); - OUT_RING( boxes[0].x1 ); - OUT_RING( boxes[0].x2 - 1 ); - OUT_RING( boxes[0].y1 ); - OUT_RING( boxes[0].y2 - 1 ); - - aux_sc_cntl |= (R128_AUX1_SC_EN | R128_AUX1_SC_MODE_OR); - } - if ( count >= 2 ) { - OUT_RING( CCE_PACKET0( R128_AUX2_SC_LEFT, 3 ) ); - OUT_RING( boxes[1].x1 ); - OUT_RING( boxes[1].x2 - 1 ); - OUT_RING( boxes[1].y1 ); - OUT_RING( boxes[1].y2 - 1 ); - - aux_sc_cntl |= (R128_AUX2_SC_EN | R128_AUX2_SC_MODE_OR); - } - if ( count >= 3 ) { - OUT_RING( CCE_PACKET0( R128_AUX3_SC_LEFT, 3 ) ); - OUT_RING( boxes[2].x1 ); - OUT_RING( boxes[2].x2 - 1 ); - OUT_RING( boxes[2].y1 ); - OUT_RING( boxes[2].y2 - 1 ); - - aux_sc_cntl |= (R128_AUX3_SC_EN | R128_AUX3_SC_MODE_OR); - } - - OUT_RING( CCE_PACKET0( R128_AUX_SC_CNTL, 0 ) ); - OUT_RING( aux_sc_cntl ); - - ADVANCE_RING(); -} - -static __inline__ void r128_emit_core( drm_r128_private_t *dev_priv ) -{ - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_r128_context_regs_t *ctx = &sarea_priv->context_state; - RING_LOCALS; - DRM_DEBUG( " %s\n", __FUNCTION__ ); - - BEGIN_RING( 2 ); - - OUT_RING( CCE_PACKET0( R128_SCALE_3D_CNTL, 0 ) ); - OUT_RING( ctx->scale_3d_cntl ); - - ADVANCE_RING(); -} - -static __inline__ void r128_emit_context( drm_r128_private_t *dev_priv ) -{ - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_r128_context_regs_t *ctx = &sarea_priv->context_state; - RING_LOCALS; - DRM_DEBUG( " %s\n", __FUNCTION__ ); - - BEGIN_RING( 13 ); - - OUT_RING( CCE_PACKET0( R128_DST_PITCH_OFFSET_C, 11 ) ); - OUT_RING( ctx->dst_pitch_offset_c ); - OUT_RING( ctx->dp_gui_master_cntl_c ); - OUT_RING( ctx->sc_top_left_c ); - OUT_RING( ctx->sc_bottom_right_c ); - OUT_RING( ctx->z_offset_c ); - OUT_RING( ctx->z_pitch_c ); - OUT_RING( ctx->z_sten_cntl_c ); - OUT_RING( ctx->tex_cntl_c ); - OUT_RING( ctx->misc_3d_state_cntl_reg ); - OUT_RING( ctx->texture_clr_cmp_clr_c ); - OUT_RING( ctx->texture_clr_cmp_msk_c ); - OUT_RING( ctx->fog_color_c ); - - ADVANCE_RING(); -} - -static __inline__ void r128_emit_setup( drm_r128_private_t *dev_priv ) -{ - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_r128_context_regs_t *ctx = &sarea_priv->context_state; - RING_LOCALS; - DRM_DEBUG( " %s\n", __FUNCTION__ ); - - BEGIN_RING( 3 ); - - OUT_RING( CCE_PACKET1( R128_SETUP_CNTL, R128_PM4_VC_FPU_SETUP ) ); - OUT_RING( ctx->setup_cntl ); - OUT_RING( ctx->pm4_vc_fpu_setup ); - - ADVANCE_RING(); -} - -static __inline__ void r128_emit_masks( drm_r128_private_t *dev_priv ) -{ - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_r128_context_regs_t *ctx = &sarea_priv->context_state; - RING_LOCALS; - DRM_DEBUG( " %s\n", __FUNCTION__ ); - - BEGIN_RING( 5 ); - - OUT_RING( CCE_PACKET0( R128_DP_WRITE_MASK, 0 ) ); - OUT_RING( ctx->dp_write_mask ); - - OUT_RING( CCE_PACKET0( R128_STEN_REF_MASK_C, 1 ) ); - OUT_RING( ctx->sten_ref_mask_c ); - OUT_RING( ctx->plane_3d_mask_c ); - - ADVANCE_RING(); -} - -static __inline__ void r128_emit_window( drm_r128_private_t *dev_priv ) -{ - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_r128_context_regs_t *ctx = &sarea_priv->context_state; - RING_LOCALS; - DRM_DEBUG( " %s\n", __FUNCTION__ ); - - BEGIN_RING( 2 ); - - OUT_RING( CCE_PACKET0( R128_WINDOW_XY_OFFSET, 0 ) ); - OUT_RING( ctx->window_xy_offset ); - - ADVANCE_RING(); -} - -static __inline__ void r128_emit_tex0( drm_r128_private_t *dev_priv ) -{ - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_r128_context_regs_t *ctx = &sarea_priv->context_state; - drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[0]; - int i; - RING_LOCALS; - DRM_DEBUG( " %s\n", __FUNCTION__ ); - - BEGIN_RING( 7 + R128_MAX_TEXTURE_LEVELS ); - - OUT_RING( CCE_PACKET0( R128_PRIM_TEX_CNTL_C, - 2 + R128_MAX_TEXTURE_LEVELS ) ); - OUT_RING( tex->tex_cntl ); - OUT_RING( tex->tex_combine_cntl ); - OUT_RING( ctx->tex_size_pitch_c ); - for ( i = 0 ; i < R128_MAX_TEXTURE_LEVELS ; i++ ) { - OUT_RING( tex->tex_offset[i] ); - } - - OUT_RING( CCE_PACKET0( R128_CONSTANT_COLOR_C, 1 ) ); - OUT_RING( ctx->constant_color_c ); - OUT_RING( tex->tex_border_color ); - - ADVANCE_RING(); -} - -static __inline__ void r128_emit_tex1( drm_r128_private_t *dev_priv ) -{ - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[1]; - int i; - RING_LOCALS; - DRM_DEBUG( " %s\n", __FUNCTION__ ); - - BEGIN_RING( 5 + R128_MAX_TEXTURE_LEVELS ); - - OUT_RING( CCE_PACKET0( R128_SEC_TEX_CNTL_C, - 1 + R128_MAX_TEXTURE_LEVELS ) ); - OUT_RING( tex->tex_cntl ); - OUT_RING( tex->tex_combine_cntl ); - for ( i = 0 ; i < R128_MAX_TEXTURE_LEVELS ; i++ ) { - OUT_RING( tex->tex_offset[i] ); - } - - OUT_RING( CCE_PACKET0( R128_SEC_TEXTURE_BORDER_COLOR_C, 0 ) ); - OUT_RING( tex->tex_border_color ); - - ADVANCE_RING(); -} - -static __inline__ void r128_emit_state( drm_r128_private_t *dev_priv ) -{ - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - unsigned int dirty = sarea_priv->dirty; - - DRM_DEBUG( "%s: dirty=0x%08x\n", __FUNCTION__, dirty ); - - if ( dirty & R128_UPLOAD_CORE ) { - r128_emit_core( dev_priv ); - sarea_priv->dirty &= ~R128_UPLOAD_CORE; - } - - if ( dirty & R128_UPLOAD_CONTEXT ) { - r128_emit_context( dev_priv ); - sarea_priv->dirty &= ~R128_UPLOAD_CONTEXT; - } - - if ( dirty & R128_UPLOAD_SETUP ) { - r128_emit_setup( dev_priv ); - sarea_priv->dirty &= ~R128_UPLOAD_SETUP; - } - - if ( dirty & R128_UPLOAD_MASKS ) { - r128_emit_masks( dev_priv ); - sarea_priv->dirty &= ~R128_UPLOAD_MASKS; - } - - if ( dirty & R128_UPLOAD_WINDOW ) { - r128_emit_window( dev_priv ); - sarea_priv->dirty &= ~R128_UPLOAD_WINDOW; - } - - if ( dirty & R128_UPLOAD_TEX0 ) { - r128_emit_tex0( dev_priv ); - sarea_priv->dirty &= ~R128_UPLOAD_TEX0; - } - - if ( dirty & R128_UPLOAD_TEX1 ) { - r128_emit_tex1( dev_priv ); - sarea_priv->dirty &= ~R128_UPLOAD_TEX1; - } - - /* Turn off the texture cache flushing */ - sarea_priv->context_state.tex_cntl_c &= ~R128_TEX_CACHE_FLUSH; - - sarea_priv->dirty &= ~R128_REQUIRE_QUIESCENCE; -} - - -#if R128_PERFORMANCE_BOXES -/* ================================================================ - * Performance monitoring functions - */ - -static void r128_clear_box( drm_r128_private_t *dev_priv, - int x, int y, int w, int h, - int r, int g, int b ) -{ - u32 pitch, offset; - u32 fb_bpp, color; - RING_LOCALS; - - switch ( dev_priv->fb_bpp ) { - case 16: - fb_bpp = R128_GMC_DST_16BPP; - color = (((r & 0xf8) << 8) | - ((g & 0xfc) << 3) | - ((b & 0xf8) >> 3)); - break; - case 24: - fb_bpp = R128_GMC_DST_24BPP; - color = ((r << 16) | (g << 8) | b); - break; - case 32: - fb_bpp = R128_GMC_DST_32BPP; - color = (((0xff) << 24) | (r << 16) | (g << 8) | b); - break; - default: - return; - } - - offset = dev_priv->back_offset; - pitch = dev_priv->back_pitch >> 3; - - BEGIN_RING( 6 ); - - OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - fb_bpp | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_AUX_CLIP_DIS ); - - OUT_RING( (pitch << 21) | (offset >> 5) ); - OUT_RING( color ); - - OUT_RING( (x << 16) | y ); - OUT_RING( (w << 16) | h ); - - ADVANCE_RING(); -} - -static void r128_cce_performance_boxes( drm_r128_private_t *dev_priv ) -{ - if ( atomic_read( &dev_priv->idle_count ) == 0 ) { - r128_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 ); - } else { - atomic_set( &dev_priv->idle_count, 0 ); - } -} - -#endif - - -/* ================================================================ - * CCE command dispatch functions - */ - -static void r128_print_dirty( const char *msg, unsigned int flags ) -{ - DRM_INFO( "%s: (0x%x) %s%s%s%s%s%s%s%s%s\n", - msg, - flags, - (flags & R128_UPLOAD_CORE) ? "core, " : "", - (flags & R128_UPLOAD_CONTEXT) ? "context, " : "", - (flags & R128_UPLOAD_SETUP) ? "setup, " : "", - (flags & R128_UPLOAD_TEX0) ? "tex0, " : "", - (flags & R128_UPLOAD_TEX1) ? "tex1, " : "", - (flags & R128_UPLOAD_MASKS) ? "masks, " : "", - (flags & R128_UPLOAD_WINDOW) ? "window, " : "", - (flags & R128_UPLOAD_CLIPRECTS) ? "cliprects, " : "", - (flags & R128_REQUIRE_QUIESCENCE) ? "quiescence, " : "" ); -} - -static void r128_cce_dispatch_clear( drm_device_t *dev, - drm_r128_clear_t *clear ) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - int nbox = sarea_priv->nbox; - drm_clip_rect_t *pbox = sarea_priv->boxes; - unsigned int flags = clear->flags; - int i; - RING_LOCALS; - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) { - unsigned int tmp = flags; - - flags &= ~(R128_FRONT | R128_BACK); - if ( tmp & R128_FRONT ) flags |= R128_BACK; - if ( tmp & R128_BACK ) flags |= R128_FRONT; - } - - for ( i = 0 ; i < nbox ; i++ ) { - int x = pbox[i].x1; - int y = pbox[i].y1; - int w = pbox[i].x2 - x; - int h = pbox[i].y2 - y; - - DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n", - pbox[i].x1, pbox[i].y1, pbox[i].x2, - pbox[i].y2, flags ); - - if ( flags & (R128_FRONT | R128_BACK) ) { - BEGIN_RING( 2 ); - - OUT_RING( CCE_PACKET0( R128_DP_WRITE_MASK, 0 ) ); - OUT_RING( clear->color_mask ); - - ADVANCE_RING(); - } - - if ( flags & R128_FRONT ) { - BEGIN_RING( 6 ); - - OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->color_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_AUX_CLIP_DIS ); - - OUT_RING( dev_priv->front_pitch_offset_c ); - OUT_RING( clear->clear_color ); - - OUT_RING( (x << 16) | y ); - OUT_RING( (w << 16) | h ); - - ADVANCE_RING(); - } - - if ( flags & R128_BACK ) { - BEGIN_RING( 6 ); - - OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->color_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_AUX_CLIP_DIS ); - - OUT_RING( dev_priv->back_pitch_offset_c ); - OUT_RING( clear->clear_color ); - - OUT_RING( (x << 16) | y ); - OUT_RING( (w << 16) | h ); - - ADVANCE_RING(); - } - - if ( flags & R128_DEPTH ) { - BEGIN_RING( 6 ); - - OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_AUX_CLIP_DIS | - R128_GMC_WR_MSK_DIS ); - - OUT_RING( dev_priv->depth_pitch_offset_c ); - OUT_RING( clear->clear_depth ); - - OUT_RING( (x << 16) | y ); - OUT_RING( (w << 16) | h ); - - ADVANCE_RING(); - } - } -} - -static void r128_cce_dispatch_swap( drm_device_t *dev ) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - int nbox = sarea_priv->nbox; - drm_clip_rect_t *pbox = sarea_priv->boxes; - int i; - RING_LOCALS; - DRM_DEBUG( "%s\n", __FUNCTION__ ); - -#if R128_PERFORMANCE_BOXES - /* Do some trivial performance monitoring... - */ - r128_cce_performance_boxes( dev_priv ); -#endif - - for ( i = 0 ; i < nbox ; i++ ) { - int x = pbox[i].x1; - int y = pbox[i].y1; - int w = pbox[i].x2 - x; - int h = pbox[i].y2 - y; - - BEGIN_RING( 7 ); - - OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) ); - OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL | - R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_NONE | - (dev_priv->color_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_S | - R128_DP_SRC_SOURCE_MEMORY | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_AUX_CLIP_DIS | - R128_GMC_WR_MSK_DIS ); - - OUT_RING( dev_priv->back_pitch_offset_c ); - OUT_RING( dev_priv->front_pitch_offset_c ); - - OUT_RING( (x << 16) | y ); - OUT_RING( (x << 16) | y ); - OUT_RING( (w << 16) | h ); - - ADVANCE_RING(); - } - - /* Increment the frame counter. The client-side 3D driver must - * throttle the framerate by waiting for this value before - * performing the swapbuffer ioctl. - */ - dev_priv->sarea_priv->last_frame++; - - BEGIN_RING( 2 ); - - OUT_RING( CCE_PACKET0( R128_LAST_FRAME_REG, 0 ) ); - OUT_RING( dev_priv->sarea_priv->last_frame ); - - ADVANCE_RING(); -} - -static void r128_cce_dispatch_flip( drm_device_t *dev ) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - RING_LOCALS; - DRM_DEBUG( "%s: page=%d\n", __FUNCTION__, dev_priv->current_page ); - -#if R128_PERFORMANCE_BOXES - /* Do some trivial performance monitoring... - */ - r128_cce_performance_boxes( dev_priv ); -#endif - - BEGIN_RING( 4 ); - - R128_WAIT_UNTIL_PAGE_FLIPPED(); - OUT_RING( CCE_PACKET0( R128_CRTC_OFFSET, 0 ) ); - - if ( dev_priv->current_page == 0 ) { - OUT_RING( dev_priv->back_offset ); - dev_priv->current_page = 1; - } else { - OUT_RING( dev_priv->front_offset ); - dev_priv->current_page = 0; - } - - ADVANCE_RING(); - - /* Increment the frame counter. The client-side 3D driver must - * throttle the framerate by waiting for this value before - * performing the swapbuffer ioctl. - */ - dev_priv->sarea_priv->last_frame++; - - BEGIN_RING( 2 ); - - OUT_RING( CCE_PACKET0( R128_LAST_FRAME_REG, 0 ) ); - OUT_RING( dev_priv->sarea_priv->last_frame ); - - ADVANCE_RING(); -} - -static void r128_cce_dispatch_vertex( drm_device_t *dev, - drm_buf_t *buf ) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_buf_priv_t *buf_priv = buf->dev_private; - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - int format = sarea_priv->vc_format; - int offset = buf->bus_address; - int size = buf->used; - int prim = buf_priv->prim; - int i = 0; - RING_LOCALS; - DRM_DEBUG( "%s: buf=%d nbox=%d\n", - __FUNCTION__, buf->idx, sarea_priv->nbox ); - - if ( 0 ) - r128_print_dirty( "dispatch_vertex", sarea_priv->dirty ); - - if ( buf->used ) { - buf_priv->dispatched = 1; - - if ( sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS ) { - r128_emit_state( dev_priv ); - } - - do { - /* Emit the next set of up to three cliprects */ - if ( i < sarea_priv->nbox ) { - r128_emit_clip_rects( dev_priv, - &sarea_priv->boxes[i], - sarea_priv->nbox - i ); - } - - /* Emit the vertex buffer rendering commands */ - BEGIN_RING( 5 ); - - OUT_RING( CCE_PACKET3( R128_3D_RNDR_GEN_INDX_PRIM, 3 ) ); - OUT_RING( offset ); - OUT_RING( size ); - OUT_RING( format ); - OUT_RING( prim | R128_CCE_VC_CNTL_PRIM_WALK_LIST | - (size << R128_CCE_VC_CNTL_NUM_SHIFT) ); - - ADVANCE_RING(); - - i += 3; - } while ( i < sarea_priv->nbox ); - } - - if ( buf_priv->discard ) { - buf_priv->age = dev_priv->sarea_priv->last_dispatch; - - /* Emit the vertex buffer age */ - BEGIN_RING( 2 ); - - OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) ); - OUT_RING( buf_priv->age ); - - ADVANCE_RING(); - - buf->pending = 1; - buf->used = 0; - /* FIXME: Check dispatched field */ - buf_priv->dispatched = 0; - } - - dev_priv->sarea_priv->last_dispatch++; - - sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS; - sarea_priv->nbox = 0; -} - -static void r128_cce_dispatch_indirect( drm_device_t *dev, - drm_buf_t *buf, - int start, int end ) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_buf_priv_t *buf_priv = buf->dev_private; - RING_LOCALS; - DRM_DEBUG( "indirect: buf=%d s=0x%x e=0x%x\n", - buf->idx, start, end ); - - if ( start != end ) { - int offset = buf->bus_address + start; - int dwords = (end - start + 3) / sizeof(u32); - - /* Indirect buffer data must be an even number of - * dwords, so if we've been given an odd number we must - * pad the data with a Type-2 CCE packet. - */ - if ( dwords & 1 ) { - u32 *data = (u32 *) - ((char *)dev_priv->buffers->handle - + buf->offset + start); - data[dwords++] = cpu_to_le32( R128_CCE_PACKET2 ); - } - - buf_priv->dispatched = 1; - - /* Fire off the indirect buffer */ - BEGIN_RING( 3 ); - - OUT_RING( CCE_PACKET0( R128_PM4_IW_INDOFF, 1 ) ); - OUT_RING( offset ); - OUT_RING( dwords ); - - ADVANCE_RING(); - } - - if ( buf_priv->discard ) { - buf_priv->age = dev_priv->sarea_priv->last_dispatch; - - /* Emit the indirect buffer age */ - BEGIN_RING( 2 ); - - OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) ); - OUT_RING( buf_priv->age ); - - ADVANCE_RING(); - - buf->pending = 1; - buf->used = 0; - /* FIXME: Check dispatched field */ - buf_priv->dispatched = 0; - } - - dev_priv->sarea_priv->last_dispatch++; -} - -static void r128_cce_dispatch_indices( drm_device_t *dev, - drm_buf_t *buf, - int start, int end, - int count ) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_buf_priv_t *buf_priv = buf->dev_private; - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - int format = sarea_priv->vc_format; - int offset = dev_priv->buffers->offset - dev_priv->cce_buffers_offset; - int prim = buf_priv->prim; - u32 *data; - int dwords; - int i = 0; - RING_LOCALS; - DRM_DEBUG( "indices: s=%d e=%d c=%d\n", start, end, count ); - - if ( 0 ) - r128_print_dirty( "dispatch_indices", sarea_priv->dirty ); - - if ( start != end ) { - buf_priv->dispatched = 1; - - if ( sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS ) { - r128_emit_state( dev_priv ); - } - - dwords = (end - start + 3) / sizeof(u32); - - data = (u32 *)((char *)dev_priv->buffers->handle - + buf->offset + start); - - data[0] = cpu_to_le32( CCE_PACKET3( R128_3D_RNDR_GEN_INDX_PRIM, - dwords-2 ) ); - - data[1] = cpu_to_le32( offset ); - data[2] = cpu_to_le32( R128_MAX_VB_VERTS ); - data[3] = cpu_to_le32( format ); - data[4] = cpu_to_le32( (prim | R128_CCE_VC_CNTL_PRIM_WALK_IND | - (count << 16)) ); - - if ( count & 0x1 ) { -#if BYTE_ORDER==LITTLE_ENDIAN - data[dwords-1] &= 0x0000ffff; -#else - data[dwords-1] &= 0xffff0000; -#endif - } - - do { - /* Emit the next set of up to three cliprects */ - if ( i < sarea_priv->nbox ) { - r128_emit_clip_rects( dev_priv, - &sarea_priv->boxes[i], - sarea_priv->nbox - i ); - } - - r128_cce_dispatch_indirect( dev, buf, start, end ); - - i += 3; - } while ( i < sarea_priv->nbox ); - } - - if ( buf_priv->discard ) { - buf_priv->age = dev_priv->sarea_priv->last_dispatch; - - /* Emit the vertex buffer age */ - BEGIN_RING( 2 ); - - OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) ); - OUT_RING( buf_priv->age ); - - ADVANCE_RING(); - - buf->pending = 1; - /* FIXME: Check dispatched field */ - buf_priv->dispatched = 0; - } - - dev_priv->sarea_priv->last_dispatch++; - - sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS; - sarea_priv->nbox = 0; -} - -static int r128_cce_dispatch_blit( drm_device_t *dev, - drm_r128_blit_t *blit, int pid ) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - drm_device_dma_t *dma = dev->dma; - drm_buf_t *buf; - drm_r128_buf_priv_t *buf_priv; - u32 *data; - int dword_shift, dwords; - RING_LOCALS; - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - /* The compiler won't optimize away a division by a variable, - * even if the only legal values are powers of two. Thus, we'll - * use a shift instead. - */ - switch ( blit->format ) { - case R128_DATATYPE_ARGB8888: - dword_shift = 0; - break; - case R128_DATATYPE_ARGB1555: - case R128_DATATYPE_RGB565: - case R128_DATATYPE_ARGB4444: - dword_shift = 1; - break; - case R128_DATATYPE_CI8: - case R128_DATATYPE_RGB8: - dword_shift = 2; - break; - default: - DRM_ERROR( "invalid blit format %d\n", blit->format ); - DRM_OS_RETURN( EINVAL ); - } - - /* Flush the pixel cache, and mark the contents as Read Invalid. - * This ensures no pixel data gets mixed up with the texture - * data from the host data blit, otherwise part of the texture - * image may be corrupted. - */ - BEGIN_RING( 2 ); - - OUT_RING( CCE_PACKET0( R128_PC_GUI_CTLSTAT, 0 ) ); - OUT_RING( R128_PC_RI_GUI | R128_PC_FLUSH_GUI ); - - ADVANCE_RING(); - - /* Dispatch the indirect buffer. - */ - buf = dma->buflist[blit->idx]; - buf_priv = buf->dev_private; - - if ( buf->pid != pid ) { - DRM_ERROR( "process %d using buffer owned by %d\n", - pid, buf->pid ); - DRM_OS_RETURN( EINVAL ); - } - if ( buf->pending ) { - DRM_ERROR( "sending pending buffer %d\n", blit->idx ); - DRM_OS_RETURN( EINVAL ); - } - - buf_priv->discard = 1; - - dwords = (blit->width * blit->height) >> dword_shift; - - data = (u32 *)((char *)dev_priv->buffers->handle + buf->offset); - - data[0] = cpu_to_le32( CCE_PACKET3( R128_CNTL_HOSTDATA_BLT, dwords + 6 ) ); - data[1] = cpu_to_le32( (R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_NONE | - (blit->format << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_S | - R128_DP_SRC_SOURCE_HOST_DATA | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_AUX_CLIP_DIS | - R128_GMC_WR_MSK_DIS) ); - - data[2] = cpu_to_le32( (blit->pitch << 21) | (blit->offset >> 5) ); - data[3] = cpu_to_le32( 0xffffffff ); - data[4] = cpu_to_le32( 0xffffffff ); - data[5] = cpu_to_le32( (blit->y << 16) | blit->x ); - data[6] = cpu_to_le32( (blit->height << 16) | blit->width ); - data[7] = cpu_to_le32( dwords ); - - buf->used = (dwords + 8) * sizeof(u32); - - r128_cce_dispatch_indirect( dev, buf, 0, buf->used ); - - /* Flush the pixel cache after the blit completes. This ensures - * the texture data is written out to memory before rendering - * continues. - */ - BEGIN_RING( 2 ); - - OUT_RING( CCE_PACKET0( R128_PC_GUI_CTLSTAT, 0 ) ); - OUT_RING( R128_PC_FLUSH_GUI ); - - ADVANCE_RING(); - - return 0; -} - - -/* ================================================================ - * Tiled depth buffer management - * - * FIXME: These should all set the destination write mask for when we - * have hardware stencil support. - */ - -static int r128_cce_dispatch_write_span( drm_device_t *dev, - drm_r128_depth_t *depth ) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - int count, x, y; - u32 *buffer; - u8 *mask; - int i; - RING_LOCALS; - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - count = depth->n; - if ( DRM_OS_COPYFROMUSR( &x, depth->x, sizeof(x) ) ) { - DRM_OS_RETURN( EFAULT ); - } - if ( DRM_OS_COPYFROMUSR( &y, depth->y, sizeof(y) ) ) { - DRM_OS_RETURN( EFAULT ); - } - - buffer = DRM_OS_MALLOC( depth->n * sizeof(u32) ); - if ( buffer == NULL ) - DRM_OS_RETURN( ENOMEM ); - if ( DRM_OS_COPYFROMUSR( buffer, depth->buffer, - depth->n * sizeof(u32) ) ) { - DRM_OS_FREE( buffer ); - DRM_OS_RETURN( EFAULT ); - } - - if ( depth->mask ) { - mask = DRM_OS_MALLOC( depth->n * sizeof(u8) ); - if ( mask == NULL ) { - DRM_OS_FREE( buffer ); - DRM_OS_RETURN( ENOMEM ); - } - if ( DRM_OS_COPYFROMUSR( mask, depth->mask, - depth->n * sizeof(u8) ) ) { - DRM_OS_FREE( buffer ); - DRM_OS_FREE( mask ); - DRM_OS_RETURN( EFAULT ); - } - - for ( i = 0 ; i < count ; i++, x++ ) { - if ( mask[i] ) { - BEGIN_RING( 6 ); - - OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_WR_MSK_DIS ); - - OUT_RING( dev_priv->depth_pitch_offset_c ); - OUT_RING( buffer[i] ); - - OUT_RING( (x << 16) | y ); - OUT_RING( (1 << 16) | 1 ); - - ADVANCE_RING(); - } - } - - DRM_OS_FREE( mask ); - } else { - for ( i = 0 ; i < count ; i++, x++ ) { - BEGIN_RING( 6 ); - - OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_WR_MSK_DIS ); - - OUT_RING( dev_priv->depth_pitch_offset_c ); - OUT_RING( buffer[i] ); - - OUT_RING( (x << 16) | y ); - OUT_RING( (1 << 16) | 1 ); - - ADVANCE_RING(); - } - } - - DRM_OS_FREE( buffer ); - - return 0; -} - -static int r128_cce_dispatch_write_pixels( drm_device_t *dev, - drm_r128_depth_t *depth ) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - int count, *x, *y; - u32 *buffer; - u8 *mask; - int i; - RING_LOCALS; - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - count = depth->n; - - x = DRM_OS_MALLOC( count * sizeof(*x) ); - if ( x == NULL ) { - DRM_OS_RETURN( ENOMEM ); - } - y = DRM_OS_MALLOC( count * sizeof(*y) ); - if ( y == NULL ) { - DRM_OS_FREE( x ); - DRM_OS_RETURN( ENOMEM ); - } - if ( DRM_OS_COPYFROMUSR( x, depth->x, count * sizeof(int) ) ) { - DRM_OS_FREE( x ); - DRM_OS_FREE( y ); - DRM_OS_RETURN( EFAULT ); - } - if ( DRM_OS_COPYFROMUSR( y, depth->y, count * sizeof(int) ) ) { - DRM_OS_FREE( x ); - DRM_OS_FREE( y ); - DRM_OS_RETURN( EFAULT ); - } - - buffer = DRM_OS_MALLOC( depth->n * sizeof(u32) ); - if ( buffer == NULL ) { - DRM_OS_FREE( x ); - DRM_OS_FREE( y ); - DRM_OS_RETURN( ENOMEM ); - } - if ( DRM_OS_COPYFROMUSR( buffer, depth->buffer, - depth->n * sizeof(u32) ) ) { - DRM_OS_FREE( x ); - DRM_OS_FREE( y ); - DRM_OS_FREE( buffer ); - DRM_OS_RETURN( EFAULT ); - } - - if ( depth->mask ) { - mask = DRM_OS_MALLOC( depth->n * sizeof(u8) ); - if ( mask == NULL ) { - DRM_OS_FREE( x ); - DRM_OS_FREE( y ); - DRM_OS_FREE( buffer ); - DRM_OS_RETURN( ENOMEM ); - } - if ( DRM_OS_COPYFROMUSR( mask, depth->mask, - depth->n * sizeof(u8) ) ) { - DRM_OS_FREE( x ); - DRM_OS_FREE( y ); - DRM_OS_FREE( buffer ); - DRM_OS_FREE( mask ); - DRM_OS_RETURN( EFAULT ); - } - - for ( i = 0 ; i < count ; i++ ) { - if ( mask[i] ) { - BEGIN_RING( 6 ); - - OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_WR_MSK_DIS ); - - OUT_RING( dev_priv->depth_pitch_offset_c ); - OUT_RING( buffer[i] ); - - OUT_RING( (x[i] << 16) | y[i] ); - OUT_RING( (1 << 16) | 1 ); - - ADVANCE_RING(); - } - } - - DRM_OS_FREE( mask ); - } else { - for ( i = 0 ; i < count ; i++ ) { - BEGIN_RING( 6 ); - - OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_WR_MSK_DIS ); - - OUT_RING( dev_priv->depth_pitch_offset_c ); - OUT_RING( buffer[i] ); - - OUT_RING( (x[i] << 16) | y[i] ); - OUT_RING( (1 << 16) | 1 ); - - ADVANCE_RING(); - } - } - - DRM_OS_FREE( x ); - DRM_OS_FREE( y ); - DRM_OS_FREE( buffer ); - - return 0; -} - -static int r128_cce_dispatch_read_span( drm_device_t *dev, - drm_r128_depth_t *depth ) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - int count, x, y; - RING_LOCALS; - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - count = depth->n; - if ( DRM_OS_COPYFROMUSR( &x, depth->x, sizeof(x) ) ) { - DRM_OS_RETURN( EFAULT ); - } - if ( DRM_OS_COPYFROMUSR( &y, depth->y, sizeof(y) ) ) { - DRM_OS_RETURN( EFAULT ); - } - - BEGIN_RING( 7 ); - - OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) ); - OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL | - R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_NONE | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_S | - R128_DP_SRC_SOURCE_MEMORY | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_WR_MSK_DIS ); - - OUT_RING( dev_priv->depth_pitch_offset_c ); - OUT_RING( dev_priv->span_pitch_offset_c ); - - OUT_RING( (x << 16) | y ); - OUT_RING( (0 << 16) | 0 ); - OUT_RING( (count << 16) | 1 ); - - ADVANCE_RING(); - - return 0; -} - -static int r128_cce_dispatch_read_pixels( drm_device_t *dev, - drm_r128_depth_t *depth ) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - int count, *x, *y; - int i; - RING_LOCALS; - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - count = depth->n; - if ( count > dev_priv->depth_pitch ) { - count = dev_priv->depth_pitch; - } - - x = DRM_OS_MALLOC( count * sizeof(*x) ); - if ( x == NULL ) { - DRM_OS_RETURN( ENOMEM ); - } - y = DRM_OS_MALLOC( count * sizeof(*y) ); - if ( y == NULL ) { - DRM_OS_FREE( x ); - DRM_OS_RETURN( ENOMEM ); - } - if ( DRM_OS_COPYFROMUSR( x, depth->x, count * sizeof(int) ) ) { - DRM_OS_FREE( x ); - DRM_OS_FREE( y ); - DRM_OS_RETURN( EFAULT ); - } - if ( DRM_OS_COPYFROMUSR( y, depth->y, count * sizeof(int) ) ) { - DRM_OS_FREE( x ); - DRM_OS_FREE( y ); - DRM_OS_RETURN( EFAULT ); - } - - for ( i = 0 ; i < count ; i++ ) { - BEGIN_RING( 7 ); - - OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) ); - OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL | - R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_NONE | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_S | - R128_DP_SRC_SOURCE_MEMORY | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_WR_MSK_DIS ); - - OUT_RING( dev_priv->depth_pitch_offset_c ); - OUT_RING( dev_priv->span_pitch_offset_c ); - - OUT_RING( (x[i] << 16) | y[i] ); - OUT_RING( (i << 16) | 0 ); - OUT_RING( (1 << 16) | 1 ); - - ADVANCE_RING(); - } - - DRM_OS_FREE( x ); - DRM_OS_FREE( y ); - - return 0; -} - - -/* ================================================================ - * Polygon stipple - */ - -static void r128_cce_dispatch_stipple( drm_device_t *dev, u32 *stipple ) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - int i; - RING_LOCALS; - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - BEGIN_RING( 33 ); - - OUT_RING( CCE_PACKET0( R128_BRUSH_DATA0, 31 ) ); - for ( i = 0 ; i < 32 ; i++ ) { - OUT_RING( stipple[i] ); - } - - ADVANCE_RING(); -} - - -/* ================================================================ - * IOCTL functions - */ - -int r128_cce_clear( DRM_OS_IOCTL ) -{ - DRM_OS_DEVICE; - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_r128_clear_t clear; - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - LOCK_TEST_WITH_RETURN( dev ); - - DRM_OS_KRNFROMUSR( clear, (drm_r128_clear_t *) data, - sizeof(clear) ); - - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - - if ( sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS ) - sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS; - - r128_cce_dispatch_clear( dev, &clear ); - - /* Make sure we restore the 3D state next time. - */ - dev_priv->sarea_priv->dirty |= R128_UPLOAD_CONTEXT | R128_UPLOAD_MASKS; - - return 0; -} - -int r128_cce_swap( DRM_OS_IOCTL ) -{ - DRM_OS_DEVICE; - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - LOCK_TEST_WITH_RETURN( dev ); - - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - - if ( sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS ) - sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS; - - if ( !dev_priv->page_flipping ) { - r128_cce_dispatch_swap( dev ); - dev_priv->sarea_priv->dirty |= (R128_UPLOAD_CONTEXT | - R128_UPLOAD_MASKS); - } else { - r128_cce_dispatch_flip( dev ); - } - - return 0; -} - -int r128_cce_vertex( DRM_OS_IOCTL ) -{ - DRM_OS_DEVICE; - drm_r128_private_t *dev_priv = dev->dev_private; - drm_device_dma_t *dma = dev->dma; - drm_buf_t *buf; - drm_r128_buf_priv_t *buf_priv; - drm_r128_vertex_t vertex; - - LOCK_TEST_WITH_RETURN( dev ); - - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); - DRM_OS_RETURN( EINVAL ); - } - - DRM_OS_KRNFROMUSR( vertex, (drm_r128_vertex_t *) data, - sizeof(vertex) ); - - DRM_DEBUG( "%s: pid=%d index=%d count=%d discard=%d\n", - __FUNCTION__, DRM_OS_CURRENTPID, - vertex.idx, vertex.count, vertex.discard ); - - if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) { - DRM_ERROR( "buffer index %d (of %d max)\n", - vertex.idx, dma->buf_count - 1 ); - DRM_OS_RETURN( EINVAL ); - } - if ( vertex.prim < 0 || - vertex.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 ) { - DRM_ERROR( "buffer prim %d\n", vertex.prim ); - DRM_OS_RETURN( EINVAL ); - } - - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - VB_AGE_TEST_WITH_RETURN( dev_priv ); - - buf = dma->buflist[vertex.idx]; - buf_priv = buf->dev_private; - - if ( buf->pid != DRM_OS_CURRENTPID ) { - DRM_ERROR( "process %d using buffer owned by %d\n", - DRM_OS_CURRENTPID, buf->pid ); - DRM_OS_RETURN( EINVAL ); - } - if ( buf->pending ) { - DRM_ERROR( "sending pending buffer %d\n", vertex.idx ); - DRM_OS_RETURN( EINVAL ); - } - - buf->used = vertex.count; - buf_priv->prim = vertex.prim; - buf_priv->discard = vertex.discard; - - r128_cce_dispatch_vertex( dev, buf ); - - return 0; -} - -int r128_cce_indices( DRM_OS_IOCTL ) -{ - DRM_OS_DEVICE; - drm_r128_private_t *dev_priv = dev->dev_private; - drm_device_dma_t *dma = dev->dma; - drm_buf_t *buf; - drm_r128_buf_priv_t *buf_priv; - drm_r128_indices_t elts; - int count; - - LOCK_TEST_WITH_RETURN( dev ); - - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); - DRM_OS_RETURN( EINVAL ); - } - - DRM_OS_KRNFROMUSR( elts, (drm_r128_indices_t *) data, - sizeof(elts) ); - - DRM_DEBUG( "%s: pid=%d buf=%d s=%d e=%d d=%d\n", - __FUNCTION__, DRM_OS_CURRENTPID, - elts.idx, elts.start, elts.end, elts.discard ); - - if ( elts.idx < 0 || elts.idx >= dma->buf_count ) { - DRM_ERROR( "buffer index %d (of %d max)\n", - elts.idx, dma->buf_count - 1 ); - DRM_OS_RETURN( EINVAL ); - } - if ( elts.prim < 0 || - elts.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 ) { - DRM_ERROR( "buffer prim %d\n", elts.prim ); - DRM_OS_RETURN( EINVAL ); - } - - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - VB_AGE_TEST_WITH_RETURN( dev_priv ); - - buf = dma->buflist[elts.idx]; - buf_priv = buf->dev_private; - - if ( buf->pid != DRM_OS_CURRENTPID ) { - DRM_ERROR( "process %d using buffer owned by %d\n", - DRM_OS_CURRENTPID, buf->pid ); - DRM_OS_RETURN( EINVAL ); - } - if ( buf->pending ) { - DRM_ERROR( "sending pending buffer %d\n", elts.idx ); - DRM_OS_RETURN( EINVAL ); - } - - count = (elts.end - elts.start) / sizeof(u16); - elts.start -= R128_INDEX_PRIM_OFFSET; - - if ( elts.start & 0x7 ) { - DRM_ERROR( "misaligned buffer 0x%x\n", elts.start ); - DRM_OS_RETURN( EINVAL ); - } - if ( elts.start < buf->used ) { - DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used ); - DRM_OS_RETURN( EINVAL ); - } - - buf->used = elts.end; - buf_priv->prim = elts.prim; - buf_priv->discard = elts.discard; - - r128_cce_dispatch_indices( dev, buf, elts.start, elts.end, count ); - - return 0; -} - -int r128_cce_blit( DRM_OS_IOCTL ) -{ - DRM_OS_DEVICE; - drm_device_dma_t *dma = dev->dma; - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_blit_t blit; - - LOCK_TEST_WITH_RETURN( dev ); - - DRM_OS_KRNFROMUSR( blit, (drm_r128_blit_t *) data, - sizeof(blit) ); - - DRM_DEBUG( "%s: pid=%d index=%d\n", - __FUNCTION__, DRM_OS_CURRENTPID, blit.idx ); - - if ( blit.idx < 0 || blit.idx >= dma->buf_count ) { - DRM_ERROR( "buffer index %d (of %d max)\n", - blit.idx, dma->buf_count - 1 ); - DRM_OS_RETURN( EINVAL ); - } - - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - VB_AGE_TEST_WITH_RETURN( dev_priv ); - - return r128_cce_dispatch_blit( dev, &blit, DRM_OS_CURRENTPID ); -} - -int r128_cce_depth( DRM_OS_IOCTL ) -{ - DRM_OS_DEVICE; - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_depth_t depth; - - LOCK_TEST_WITH_RETURN( dev ); - - DRM_OS_KRNFROMUSR( depth, (drm_r128_depth_t *) data, - sizeof(depth) ); - - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - - switch ( depth.func ) { - case R128_WRITE_SPAN: - return r128_cce_dispatch_write_span( dev, &depth ); - case R128_WRITE_PIXELS: - return r128_cce_dispatch_write_pixels( dev, &depth ); - case R128_READ_SPAN: - return r128_cce_dispatch_read_span( dev, &depth ); - case R128_READ_PIXELS: - return r128_cce_dispatch_read_pixels( dev, &depth ); - } - - DRM_OS_RETURN( EINVAL ); -} - -int r128_cce_stipple( DRM_OS_IOCTL ) -{ - DRM_OS_DEVICE; - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_stipple_t stipple; - u32 mask[32]; - - LOCK_TEST_WITH_RETURN( dev ); - - DRM_OS_KRNFROMUSR( stipple, (drm_r128_stipple_t *) data, - sizeof(stipple) ); - - if ( DRM_OS_COPYFROMUSR( &mask, stipple.mask, - 32 * sizeof(u32) ) ) - DRM_OS_RETURN( EFAULT ); - - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - - r128_cce_dispatch_stipple( dev, mask ); - - return 0; -} - -int r128_cce_indirect( DRM_OS_IOCTL ) -{ - DRM_OS_DEVICE; - drm_r128_private_t *dev_priv = dev->dev_private; - drm_device_dma_t *dma = dev->dma; - drm_buf_t *buf; - drm_r128_buf_priv_t *buf_priv; - drm_r128_indirect_t indirect; -#if 0 - RING_LOCALS; -#endif - - LOCK_TEST_WITH_RETURN( dev ); - - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); - DRM_OS_RETURN(EINVAL); - } - - DRM_OS_KRNFROMUSR( indirect, (drm_r128_indirect_t *) data, - sizeof(indirect) ); - - DRM_DEBUG( "indirect: idx=%d s=%d e=%d d=%d\n", - indirect.idx, indirect.start, - indirect.end, indirect.discard ); - - if ( indirect.idx < 0 || indirect.idx >= dma->buf_count ) { - DRM_ERROR( "buffer index %d (of %d max)\n", - indirect.idx, dma->buf_count - 1 ); - DRM_OS_RETURN(EINVAL); - } - - buf = dma->buflist[indirect.idx]; - buf_priv = buf->dev_private; - - if ( buf->pid != DRM_OS_CURRENTPID ) { - DRM_ERROR( "process %d using buffer owned by %d\n", - DRM_OS_CURRENTPID, buf->pid ); - DRM_OS_RETURN(EINVAL); - } - if ( buf->pending ) { - DRM_ERROR( "sending pending buffer %d\n", indirect.idx ); - DRM_OS_RETURN(EINVAL); - } - - if ( indirect.start < buf->used ) { - DRM_ERROR( "reusing indirect: start=0x%x actual=0x%x\n", - indirect.start, buf->used ); - DRM_OS_RETURN(EINVAL); - } - - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - VB_AGE_TEST_WITH_RETURN( dev_priv ); - - buf->used = indirect.end; - buf_priv->discard = indirect.discard; - -#if 0 - /* Wait for the 3D stream to idle before the indirect buffer - * containing 2D acceleration commands is processed. - */ - BEGIN_RING( 2 ); - RADEON_WAIT_UNTIL_3D_IDLE(); - ADVANCE_RING(); -#endif - - /* Dispatch the indirect buffer full of commands from the - * X server. This is insecure and is thus only available to - * privileged clients. - */ - r128_cce_dispatch_indirect( dev, buf, indirect.start, indirect.end ); - - return 0; -} |