diff options
| author | Kevin E Martin <kem@kem.org> | 2001-04-06 17:53:32 +0000 |
|---|---|---|
| committer | Kevin E Martin <kem@kem.org> | 2001-04-06 17:53:32 +0000 |
| commit | 0e7f6c0726e5ff08eeab8e17a5aa63fbe44b3410 (patch) | |
| tree | d55647e810bf5e2654bbadf141f9c04c9cc2f264 /linux/radeon_drv.h | |
| parent | 908d32f84c33a4192b8381d74fc6bccc73e309f9 (diff) | |
- Fix typoX_4_0_99_2-20010409-preimport
- Clean up some macros
Diffstat (limited to 'linux/radeon_drv.h')
| -rw-r--r-- | linux/radeon_drv.h | 23 |
1 files changed, 14 insertions, 9 deletions
diff --git a/linux/radeon_drv.h b/linux/radeon_drv.h index 249358477..ee5e113b1 100644 --- a/linux/radeon_drv.h +++ b/linux/radeon_drv.h @@ -521,13 +521,15 @@ extern int radeon_cp_indirect( struct inode *inode, struct file *filp, #define RADEON_DEREF(reg) *(volatile u32 *)RADEON_ADDR( reg ) #ifdef __alpha__ #define RADEON_READ(reg) (_RADEON_READ((u32 *)RADEON_ADDR( reg ))) -static inline u32 _RADEON_READ(u32 *addr) { +static inline u32 _RADEON_READ(u32 *addr) +{ mb(); return *(volatile u32 *)addr; } -#define RADEON_WRITE(reg,val) do { \ - wmb(); - RADEON_DEREF(reg) = val; +#define RADEON_WRITE(reg,val) \ +do { \ + wmb(); \ + RADEON_DEREF(reg) = val; \ } while (0) #else #define RADEON_READ(reg) RADEON_DEREF( reg ) @@ -537,20 +539,23 @@ static inline u32 _RADEON_READ(u32 *addr) { #define RADEON_DEREF8(reg) *(volatile u8 *)RADEON_ADDR( reg ) #ifdef __alpha__ #define RADEON_READ8(reg) _RADEON_READ8((u8 *)RADEON_ADDR( reg )) -static inline u8 _RADEON_READ8(u8 *addr) { +static inline u8 _RADEON_READ8(u8 *addr) +{ mb(); return *(volatile u8 *)addr; } -#define RADEON_WRITE8(reg,val) do { \ - wmb(); - RADEON_DEREF8( reg ) = val; +#define RADEON_WRITE8(reg,val) \ +do { \ + wmb(); \ + RADEON_DEREF8( reg ) = val; \ } while (0) #else #define RADEON_READ8(reg) RADEON_DEREF8( reg ) #define RADEON_WRITE8(reg, val) do { RADEON_DEREF8( reg ) = val; } while (0) #endif -#define RADEON_WRITE_PLL( addr, val ) do { \ +#define RADEON_WRITE_PLL( addr, val ) \ +do { \ RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \ ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \ RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \ |