- Added texture support (not yet working; also texblits not implementedati-5-0-0-20001223-freeze

    yet)
- Added workaround for overwriting VB problem (does not completely solve
    the problem -- Q3A, gloss among others will still demonstrate the
    problem)
- Added window offsets support
- Fixed depth offset initialization
- Changed visuals to support 24bpp instead of 32bpp depth buffers to match
    Mesa's depth buffer support

4 files changed, 74 insertions, 49 deletions

diff --git a/linux/radeon_cp.c b/linux/radeon_cp.c
index 3c31f65d3..087996c15 100644
--- a/linux/radeon_cp.c
+++ b/linux/radeon_cp.c
@@ -709,6 +709,10 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
 	radeon_cp_init_ring_buffer( dev );
 	radeon_do_engine_reset( dev );
 
+#if ROTATE_BUFS
+	dev_priv->last_buf = 0;
+#endif
+
 	return 0;
 }
 
@@ -952,6 +956,9 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev )
 	drm_radeon_buf_priv_t *buf_priv;
 	drm_buf_t *buf;
 	int i, t;
+#if ROTATE_BUFS
+	int start;
+#endif
 
 	/* FIXME: Optimize -- use freelist code */
 
@@ -962,10 +969,18 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev )
 			return buf;
 	}
 
+#if ROTATE_BUFS
+	if (++dev_priv->last_buf >= dma->buf_count)
+		dev_priv->last_buf = 0;
+	start = dev_priv->last_buf;
+#endif
 	for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
 		u32 done_age = RADEON_READ( RADEON_LAST_DISPATCH_REG );
-
+#if ROTATE_BUFS
+		for ( i = start ; i < dma->buf_count ; i++ ) {
+#else
 		for ( i = 0 ; i < dma->buf_count ; i++ ) {
+#endif
 			buf = dma->buflist[i];
 			buf_priv = buf->dev_private;
 			if ( buf->pending && buf_priv->age <= done_age ) {
@@ -975,6 +990,9 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev )
 				buf->pending = 0;
 				return buf;
 			}
+#if ROTATE_BUFS
+			start = 0;
+#endif
 		}
 		udelay( 1 );
 	}
@@ -986,8 +1004,14 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev )
 void radeon_freelist_reset( drm_device_t *dev )
 {
 	drm_device_dma_t *dma = dev->dma;
+#if ROTATE_BUFS
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+#endif
 	int i;
 
+#if ROTATE_BUFS
+	dev_priv->last_buf = 0;
+#endif
 	for ( i = 0 ; i < dma->buf_count ; i++ ) {
 		drm_buf_t *buf = dma->buflist[i];
 		drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
diff --git a/linux/radeon_drm.h b/linux/radeon_drm.h
index b758660f1..3f890661b 100644
--- a/linux/radeon_drm.h
+++ b/linux/radeon_drm.h
@@ -187,11 +187,12 @@ typedef struct {
 	unsigned int pp_txablend;
 	unsigned int pp_tfactor;
 
-	unsigned int pp_cubic_faces;
-
 	unsigned int pp_border_color;
 
+#ifdef CUBIC_ENABLE
+	unsigned int pp_cubic_faces;
 	unsigned int pp_cubic_offset[5];
+#endif
 } drm_radeon_texture_regs_t;
 
 typedef struct {
diff --git a/linux/radeon_drv.h b/linux/radeon_drv.h
index 2e27398b3..016e24de6 100644
--- a/linux/radeon_drv.h
+++ b/linux/radeon_drv.h
@@ -65,6 +65,14 @@ typedef struct drm_radeon_private {
 
    	drm_radeon_freelist_t *head;
    	drm_radeon_freelist_t *tail;
+/* FIXME: ROTATE_BUFS is a hask to cycle through bufs until freelist
+   code is used.  Note this hides a problem with the scratch register
+   (used to keep track of last buffer completed) being written to before
+   the last buffer has actually completed rendering. */
+#define ROTATE_BUFS 1
+#if ROTATE_BUFS
+	int last_buf;
+#endif
 
 	int usec_timeout;
 	int is_pci;
@@ -220,10 +228,16 @@ extern int  radeon_context_switch_complete(drm_device_t *dev, int new);
 #define RADEON_MC_FB_LOCATION		0x0148
 #define RADEON_MCLK_CNTL		0x0012
 
+#define RADEON_PP_BORDER_COLOR_0	0x1d40
+#define RADEON_PP_BORDER_COLOR_1	0x1d44
+#define RADEON_PP_BORDER_COLOR_2	0x1d48
 #define RADEON_PP_CNTL			0x1c38
 #define RADEON_PP_LUM_MATRIX		0x1d00
 #define RADEON_PP_MISC			0x1c14
 #define RADEON_PP_ROT_MATRIX_0		0x1d58
+#define RADEON_PP_TXFILTER_0		0x1c54
+#define RADEON_PP_TXFILTER_1		0x1c6c
+#define RADEON_PP_TXFILTER_2		0x1c84
 
 #define RADEON_RB2D_DSTCACHE_CTLSTAT	0x342c
 #	define RADEON_RB2D_DC_FLUSH_ALL		0xf
diff --git a/linux/radeon_state.c b/linux/radeon_state.c
index 30949ee27..8253e9f29 100644
--- a/linux/radeon_state.c
+++ b/linux/radeon_state.c
@@ -299,83 +299,71 @@ static inline void radeon_emit_misc( drm_radeon_private_t *dev_priv )
 
 static inline void radeon_emit_tex0( drm_radeon_private_t *dev_priv )
 {
-#if 0
 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_radeon_context_regs_t *ctx = &sarea_priv->context_state;
 	drm_radeon_texture_regs_t *tex = &sarea_priv->tex_state[0];
-	int i;
 	RING_LOCALS;
 	DRM_DEBUG( "    %s\n", __FUNCTION__ );
 
-	BEGIN_RING( 7 + RADEON_TEX_MAXLEVELS );
+	BEGIN_RING( 9 );
 
-	OUT_RING( CP_PACKET0( RADEON_PRIM_TEX_CNTL_C,
-			       2 + RADEON_TEX_MAXLEVELS ) );
-	OUT_RING( tex->tex_cntl );
-	OUT_RING( tex->tex_combine_cntl );
-	OUT_RING( ctx->tex_size_pitch_c );
-	for ( i = 0 ; i < RADEON_TEX_MAXLEVELS ; i++ ) {
-		OUT_RING( tex->tex_offset[i] );
-	}
+	OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_0, 5 ) );
+	OUT_RING( tex->pp_txfilter );
+	OUT_RING( tex->pp_txformat );
+	OUT_RING( tex->pp_txoffset );
+	OUT_RING( tex->pp_txcblend );
+	OUT_RING( tex->pp_txablend );
+	OUT_RING( tex->pp_tfactor );
 
-	OUT_RING( CP_PACKET0( RADEON_CONSTANT_COLOR_C, 1 ) );
-	OUT_RING( ctx->constant_color_c );
-	OUT_RING( tex->tex_border_color );
+	OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_0, 0 ) );
+	OUT_RING( tex->pp_border_color );
 
 	ADVANCE_RING();
-#endif
 }
 
 static inline void radeon_emit_tex1( drm_radeon_private_t *dev_priv )
 {
-#if 0
 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	drm_radeon_texture_regs_t *tex = &sarea_priv->tex_state[1];
-	int i;
 	RING_LOCALS;
 	DRM_DEBUG( "    %s\n", __FUNCTION__ );
 
-	BEGIN_RING( 5 + RADEON_TEX_MAXLEVELS );
+	BEGIN_RING( 9 );
 
-	OUT_RING( CP_PACKET0( RADEON_SEC_TEX_CNTL_C,
-			       1 + RADEON_TEX_MAXLEVELS ) );
-	OUT_RING( tex->tex_cntl );
-	OUT_RING( tex->tex_combine_cntl );
-	for ( i = 0 ; i < RADEON_TEX_MAXLEVELS ; i++ ) {
-		OUT_RING( tex->tex_offset[i] );
-	}
+	OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_1, 5 ) );
+	OUT_RING( tex->pp_txfilter );
+	OUT_RING( tex->pp_txformat );
+	OUT_RING( tex->pp_txoffset );
+	OUT_RING( tex->pp_txcblend );
+	OUT_RING( tex->pp_txablend );
+	OUT_RING( tex->pp_tfactor );
 
-	OUT_RING( CP_PACKET0( RADEON_SEC_TEXTURE_BORDER_COLOR_C, 0 ) );
-	OUT_RING( tex->tex_border_color );
+	OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_1, 0 ) );
+	OUT_RING( tex->pp_border_color );
 
 	ADVANCE_RING();
-#endif
 }
 
 static inline void radeon_emit_tex2( drm_radeon_private_t *dev_priv )
 {
-#if 0
 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	drm_radeon_texture_regs_t *tex = &sarea_priv->tex_state[2];
-	int i;
 	RING_LOCALS;
 	DRM_DEBUG( "    %s\n", __FUNCTION__ );
 
-	BEGIN_RING( 5 + RADEON_TEX_MAXLEVELS );
+	BEGIN_RING( 9 );
 
-	OUT_RING( CP_PACKET0( RADEON_SEC_TEX_CNTL_C,
-			       1 + RADEON_TEX_MAXLEVELS ) );
-	OUT_RING( tex->tex_cntl );
-	OUT_RING( tex->tex_combine_cntl );
-	for ( i = 0 ; i < RADEON_TEX_MAXLEVELS ; i++ ) {
-		OUT_RING( tex->tex_offset[i] );
-	}
+	OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_2, 5 ) );
+	OUT_RING( tex->pp_txfilter );
+	OUT_RING( tex->pp_txformat );
+	OUT_RING( tex->pp_txoffset );
+	OUT_RING( tex->pp_txcblend );
+	OUT_RING( tex->pp_txablend );
+	OUT_RING( tex->pp_tfactor );
 
-	OUT_RING( CP_PACKET0( RADEON_SEC_TEXTURE_BORDER_COLOR_C, 0 ) );
-	OUT_RING( tex->tex_border_color );
+	OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_2, 0 ) );
+	OUT_RING( tex->pp_border_color );
 
 	ADVANCE_RING();
-#endif
 }
 
 static inline void radeon_emit_state( drm_radeon_private_t *dev_priv )
@@ -1083,10 +1071,7 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev,
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
-
-	int vertsize = sarea_priv->vertsize;
 	int format = sarea_priv->vc_format;
-	int index = buf->idx;
 	int offset = dev_priv->buffers->offset - dev->agp->base;
 	int prim = buf_priv->prim;
 
@@ -1477,7 +1462,8 @@ int radeon_cp_indices( struct inode *inode, struct file *filp,
 		return -EINVAL;
 	}
 	if ( (buf->offset + elts.start) & 0x3 ) {
-		DRM_ERROR( "buffer start 0x%x\n", buf->offset + elts.start );
+		DRM_ERROR( "buffer start 0x%x\n",
+			   (u32)(buf->offset + elts.start) );
 		return -EINVAL;
 	}