diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2017-11-16 14:05:12 -0800 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2017-11-16 14:05:12 -0800 |
commit | 8c609698569578913ad40bb160b97c3f6cfa15ec (patch) | |
tree | a8a0a3b90ec9056a05f62a1c84970b5f34a3c139 /arch/arm/include | |
parent | 18c83d2c0390fd0e8336ad090a047c56037d19f5 (diff) | |
parent | fa32475ad56d339178c9be12678906f2b39e3b47 (diff) |
Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform updates from Arnd Bergmann:
"Most of the commits are for defconfig changes, to enable newly added
drivers or features that people have started using. For the changed
lines lines, we have mostly cleanups, the affected platforms are OMAP,
Versatile, EP93xx, Samsung, Broadcom, i.MX, and Actions.
The largest single change is the introduction of the TI "sysc" bus
driver, with the intention of cleaning up more legacy code.
Two new SoC platforms get added this time:
- Allwinner R40 is a modernized version of the A20 chip, now with a
Quad-Core ARM Cortex-A7. According to the manufacturer, it is
intended for "Smart Hardware"
- Broadcom Hurricane 2 (Aka Strataconnect BCM5334X) is a family of
chips meant for managed gigabit ethernet switches, based around a
Cortex-A9 CPU.
Finally, we gain SMP support for two platforms: Renesas R-Car E2 and
Amlogic Meson8/8b, which were previously added but only supported
uniprocessor operation"
* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (118 commits)
ARM: multi_v7_defconfig: Select RPMSG_VIRTIO as module
ARM: multi_v7_defconfig: enable CONFIG_GPIO_UNIPHIER
arm64: defconfig: enable CONFIG_GPIO_UNIPHIER
ARM: meson: enable MESON_IRQ_GPIO in Kconfig for meson8b
ARM: meson: Add SMP bringup code for Meson8 and Meson8b
ARM: smp_scu: allow the platform code to read the SCU CPU status
ARM: smp_scu: add a helper for powering on a specific CPU
dt-bindings: Amlogic: Add Meson8 and Meson8b SMP related documentation
ARM: OMAP3: Delete an unnecessary variable initialisation in omap3xxx_hwmod_init()
ARM: OMAP3: Use common error handling code in omap3xxx_hwmod_init()
ARM: defconfig: select the right SX150X driver
arm64: defconfig: Enable QCOM_IOMMU
arm64: Add ThunderX drivers to defconfig
arm64: defconfig: Enable Tegra PCI controller
cpufreq: imx6q: Move speed grading check to cpufreq driver
arm64: defconfig: re-enable Qualcomm DB410c USB
ARM: configs: stm32: Add MDMA support in STM32 defconfig
ARM: imx: Enable cpuidle for i.MX6DL starting at 1.1
bus: ti-sysc: Fix unbalanced pm_runtime_enable by adding remove
bus: ti-sysc: mark PM functions as __maybe_unused
...
Diffstat (limited to 'arch/arm/include')
-rw-r--r-- | arch/arm/include/asm/smp_scu.h | 12 | ||||
-rw-r--r-- | arch/arm/include/debug/brcmstb.S | 3 | ||||
-rw-r--r-- | arch/arm/include/uapi/asm/ptrace.h | 1 |
3 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h index 800f5228939f..b818e5d0cd78 100644 --- a/arch/arm/include/asm/smp_scu.h +++ b/arch/arm/include/asm/smp_scu.h @@ -28,6 +28,8 @@ static inline unsigned long scu_a9_get_base(void) #ifdef CONFIG_HAVE_ARM_SCU unsigned int scu_get_core_count(void __iomem *); int scu_power_mode(void __iomem *, unsigned int); +int scu_cpu_power_enable(void __iomem *, unsigned int); +int scu_get_cpu_power_mode(void __iomem *scu_base, unsigned int logical_cpu); #else static inline unsigned int scu_get_core_count(void __iomem *scu_base) { @@ -37,6 +39,16 @@ static inline int scu_power_mode(void __iomem *scu_base, unsigned int mode) { return -EINVAL; } +static inline int scu_cpu_power_enable(void __iomem *scu_base, + unsigned int mode) +{ + return -EINVAL; +} +static inline int scu_get_cpu_power_mode(void __iomem *scu_base, + unsigned int logical_cpu) +{ + return -EINVAL; +} #endif #if defined(CONFIG_SMP) && defined(CONFIG_HAVE_ARM_SCU) diff --git a/arch/arm/include/debug/brcmstb.S b/arch/arm/include/debug/brcmstb.S index 52aaed2b936f..c826f15d2f80 100644 --- a/arch/arm/include/debug/brcmstb.S +++ b/arch/arm/include/debug/brcmstb.S @@ -58,6 +58,7 @@ /* Check SUN_TOP_CTRL base */ ldr \rp, =SUN_TOP_CTRL_BASE @ load SUN_TOP_CTRL PA ldr \rv, [\rp, #0] @ get register contents +ARM_BE8( rev \rv, \rv ) and \rv, \rv, #0xffffff00 @ strip revision bits [7:0] /* Chip specific detection starts here */ @@ -98,11 +99,13 @@ .endm .macro store, rd, rx:vararg +ARM_BE8( rev \rd, \rd ) str \rd, \rx .endm .macro load, rd, rx:vararg ldr \rd, \rx +ARM_BE8( rev \rd, \rd ) .endm .macro senduart,rd,rx diff --git a/arch/arm/include/uapi/asm/ptrace.h b/arch/arm/include/uapi/asm/ptrace.h index 3287d790c83c..e61c65b4018d 100644 --- a/arch/arm/include/uapi/asm/ptrace.h +++ b/arch/arm/include/uapi/asm/ptrace.h @@ -58,6 +58,7 @@ #endif #define FIQ_MODE 0x00000011 #define IRQ_MODE 0x00000012 +#define MON_MODE 0x00000016 #define ABT_MODE 0x00000017 #define HYP_MODE 0x0000001a #define UND_MODE 0x0000001b |