diff options
| author | Yang Rong <rong.r.yang@intel.com> | 2014-11-17 11:08:20 +0800 |
|---|---|---|
| committer | Zhigang Gong <zhigang.gong@intel.com> | 2015-01-09 14:39:40 +0800 |
| commit | fba875f3f50d6acc8218f5859a7fb9eedcdb54f2 (patch) | |
| tree | 7bd06e19b3cecd0402cb5d939e96a845287c9011 /src | |
| parent | d4cdd6a22f2296d233087e43ec77048f989d958f (diff) | |
Change the IVB/HSW L3 SQC credit setting.
Set the L3SQ General Priority Credit to max, and L3SQ High Priority Credit
to zero, it can slightly improve the performacne, about 2% of luxmark.
Signed-off-by: Yang Rong <rong.r.yang@intel.com>
Reviewed-by: Zhigang Gong <zhigang.gong@linux.intel.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/intel/intel_gpgpu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/intel/intel_gpgpu.c b/src/intel/intel_gpgpu.c index 8f4b14f3..2666f96b 100644 --- a/src/intel/intel_gpgpu.c +++ b/src/intel/intel_gpgpu.c @@ -582,7 +582,7 @@ intel_gpgpu_set_L3_gen7(intel_gpgpu_t *gpgpu, uint32_t use_slm) BEGIN_BATCH(gpgpu->batch, 9); OUT_BATCH(gpgpu->batch, CMD_LOAD_REGISTER_IMM | 1); /* length - 2 */ OUT_BATCH(gpgpu->batch, GEN7_L3_SQC_REG1_ADDRESS_OFFSET); - OUT_BATCH(gpgpu->batch, 0x00730000); + OUT_BATCH(gpgpu->batch, 0x00A00000); OUT_BATCH(gpgpu->batch, CMD_LOAD_REGISTER_IMM | 1); /* length - 2 */ OUT_BATCH(gpgpu->batch, GEN7_L3_CNTL_REG2_ADDRESS_OFFSET); @@ -644,7 +644,7 @@ intel_gpgpu_set_L3_gen75(intel_gpgpu_t *gpgpu, uint32_t use_slm) OUT_BATCH(gpgpu->batch, (1 << 6ul) << 16); /* enable atomic in L3 */ OUT_BATCH(gpgpu->batch, CMD_LOAD_REGISTER_IMM | 1); /* length - 2 */ OUT_BATCH(gpgpu->batch, GEN7_L3_SQC_REG1_ADDRESS_OFFSET); - OUT_BATCH(gpgpu->batch, 0x00610000); + OUT_BATCH(gpgpu->batch, 0x00800000); OUT_BATCH(gpgpu->batch, CMD_LOAD_REGISTER_IMM | 1); /* length - 2 */ OUT_BATCH(gpgpu->batch, GEN7_L3_CNTL_REG2_ADDRESS_OFFSET); |