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| author | Guo Yejun <yejun.guo@intel.com> | 2014-05-23 01:24:20 +0800 |
|---|---|---|
| committer | Zhigang Gong <zhigang.gong@intel.com> | 2014-05-23 11:07:32 +0800 |
| commit | d365c54253050dd280b79250c3e9e0ed0da324a8 (patch) | |
| tree | 915831ee8db1b90e602b45c004e8b491ac34cd4f /backend | |
| parent | 4a3e69d6df6141777dd67e97aff2a451bc01aa00 (diff) | |
correct L3 cache settings for baytrail
baytrail and ivb have different register bits layout for L3 cache,
so, add a special path for baytrail.
Signed-off-by: Guo Yejun <yejun.guo@intel.com>
Reviewed-by: Zhigang Gong <zhigang.gong@linux.intel.com>
Reviewed-bu: "Song, Ruiling" <ruiling.song@intel.com>
Diffstat (limited to 'backend')
0 files changed, 0 insertions, 0 deletions