diff options
| author | Zhigang Gong <zhigang.gong@intel.com> | 2015-03-02 12:23:21 +0800 |
|---|---|---|
| committer | Zhigang Gong <zhigang.gong@intel.com> | 2015-03-02 15:57:05 +0800 |
| commit | ec7b27cc18be4704ba25562a41e2f01ac12e9621 (patch) | |
| tree | 65e7f9b5c13a8c460783cb30d09fcc85f0b13a7e | |
| parent | 43e98c59917995917f6d719d5285ebc139760086 (diff) | |
GBE: support compare two bool variables.
LLVM 3.6 may generate the following instructions:
%Pivot = icmp slt i1 %trunc49, false
when do siwth lowering pass.
To support it we must use GEN_TYPE_W to represent B rather
than GEN_TYPE_UW and we also need to remove the corresponding
assertions.
Signed-off-by: Zhigang Gong <zhigang.gong@intel.com>
Reviewed-by: "Yang, Rong R" <rong.r.yang@intel.com>
| -rw-r--r-- | backend/src/backend/gen_insn_selection.cpp | 4 | ||||
| -rw-r--r-- | backend/src/ir/instruction.cpp | 1 | ||||
| -rw-r--r-- | backend/src/llvm/llvm_gen_backend.cpp | 2 |
3 files changed, 2 insertions, 5 deletions
diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp index 629823d3..0f5e496f 100644 --- a/backend/src/backend/gen_insn_selection.cpp +++ b/backend/src/backend/gen_insn_selection.cpp @@ -115,7 +115,7 @@ namespace gbe uint32_t getGenType(ir::Type type) { using namespace ir; switch (type) { - case TYPE_BOOL: return GEN_TYPE_UW; + case TYPE_BOOL: return GEN_TYPE_W; case TYPE_S8: return GEN_TYPE_B; case TYPE_U8: return GEN_TYPE_UB; case TYPE_S16: return GEN_TYPE_W; @@ -1853,7 +1853,7 @@ namespace gbe case TYPE_U8: return GenRegister::immuw(imm.getIntegerValue() * sign); case TYPE_S8: return GenRegister::immw((int8_t)imm.getIntegerValue() * sign); case TYPE_DOUBLE: return GenRegister::immdf(imm.getDoubleValue() * sign); - case TYPE_BOOL: return GenRegister::immuw(-imm.getIntegerValue()); //return 0xffff when true + case TYPE_BOOL: return GenRegister::immw((imm.getIntegerValue() == 0) ? 0 : -1); //return 0xffff when true default: NOT_SUPPORTED; return GenRegister::immuw(0); } } diff --git a/backend/src/ir/instruction.cpp b/backend/src/ir/instruction.cpp index d86d1543..039f0854 100644 --- a/backend/src/ir/instruction.cpp +++ b/backend/src/ir/instruction.cpp @@ -887,7 +887,6 @@ namespace ir { for (uint32_t srcID = 0; srcID < 2; ++srcID) if (UNLIKELY(checkRegisterData(family, src[srcID], fn, whyNot) == false)) return false; - CHECK_TYPE(this->type, allButBool); return true; } diff --git a/backend/src/llvm/llvm_gen_backend.cpp b/backend/src/llvm/llvm_gen_backend.cpp index 201944ad..4080c58c 100644 --- a/backend/src/llvm/llvm_gen_backend.cpp +++ b/backend/src/llvm/llvm_gen_backend.cpp @@ -2151,8 +2151,6 @@ namespace gbe } void GenWriter::emitICmpInst(ICmpInst &I) { - GBE_ASSERT(I.getOperand(0)->getType() != Type::getInt1Ty(I.getContext())); - // Get the element type and the number of elements Type *operandType = I.getOperand(0)->getType(); const ir::Type type = getType(ctx, operandType); |