From 70fe9ba8cf83e27c48f80767565149c7d40ea665 Mon Sep 17 00:00:00 2001
From: Sirisha Muppavarapu <sirisha.muppavarapu@intel.com>
Date: Thu, 29 Jan 2015 06:41:04 -0800
Subject: Initial support for Broxton in the intel-driver

Added PCIIDs, Device info and the relevant code.

Signed-off-by: Sirisha Muppavarapu <sirisha.muppavarapu@intel.com>
[Peng: disable MPEG-2 encoding on BXT]
Signed-off-by: peng.chen <peng.c.chen@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
---
 src/i965_device_info.c | 56 ++++++++++++++++++++++++++++++++++++++++++++++++++
 src/i965_pciids.h      |  3 +++
 src/intel_driver.h     |  1 +
 3 files changed, 60 insertions(+)

diff --git a/src/i965_device_info.c b/src/i965_device_info.c
index d5b5cb8..a844374 100644
--- a/src/i965_device_info.c
+++ b/src/i965_device_info.c
@@ -359,6 +359,54 @@ static struct hw_codec_info skl_hw_codec_info = {
     },
 };
 
+
+static struct hw_codec_info bxt_hw_codec_info = {
+    .dec_hw_context_init = gen9_dec_hw_context_init,
+    .enc_hw_context_init = gen9_enc_hw_context_init,
+    .proc_hw_context_init = gen75_proc_context_init,
+    .render_init = gen9_render_init,
+    .post_processing_context_init = gen9_post_processing_context_init,
+
+    .max_width = 4096,
+    .max_height = 4096,
+    .min_linear_wpitch = 64,
+    .min_linear_hpitch = 16,
+
+    .h264_mvc_dec_profiles = (VA_PROFILE_MASK(H264StereoHigh) |
+                              VA_PROFILE_MASK(H264MultiviewHigh)),
+    .h264_dec_chroma_formats = EXTRA_H264_DEC_CHROMA_FORMATS,
+    .jpeg_dec_chroma_formats = EXTRA_JPEG_DEC_CHROMA_FORMATS,
+    .jpeg_enc_chroma_formats = EXTRA_JPEG_ENC_CHROMA_FORMATS,
+
+    .has_mpeg2_decoding = 1,
+    .has_h264_decoding = 1,
+    .has_h264_encoding = 1,
+    .has_vc1_decoding = 1,
+    .has_jpeg_decoding = 1,
+    .has_jpeg_encoding = 1,
+    .has_vpp = 1,
+    .has_accelerated_getimage = 1,
+    .has_accelerated_putimage = 1,
+    .has_tiled_surface = 1,
+    .has_di_motion_adptive = 1,
+    .has_di_motion_compensated = 1,
+    .has_vp8_decoding = 1,
+    .has_vp8_encoding = 1,
+    .has_h264_mvc_encoding = 1,
+    .has_hevc_decoding = 1,
+    .has_hevc_encoding = 1,
+
+    .num_filters = 5,
+    .filters = {
+        { VAProcFilterNoiseReduction, I965_RING_VEBOX },
+        { VAProcFilterDeinterlacing, I965_RING_VEBOX },
+        { VAProcFilterSharpening, I965_RING_NULL },
+        { VAProcFilterColorBalance, I965_RING_VEBOX},
+        { VAProcFilterSkinToneEnhancement, I965_RING_VEBOX},
+    },
+};
+
+
 struct hw_codec_info *
 i965_get_codec_info(int devid)
 {
@@ -487,6 +535,14 @@ static const struct intel_device_info skl_device_info = {
     .max_wm_threads = 64,       /* per PSD */
 };
 
+static const struct intel_device_info bxt_device_info = {
+    .gen = 9,
+
+    .urb_size = 4096,
+    .max_wm_threads = 64,       /* per PSD */
+    .is_broxton = 1,
+};
+
 const struct intel_device_info *
 i965_get_device_info(int devid)
 {
diff --git a/src/i965_pciids.h b/src/i965_pciids.h
index 22a43b1..cf46b9e 100644
--- a/src/i965_pciids.h
+++ b/src/i965_pciids.h
@@ -155,3 +155,6 @@ CHIPSET(0x1932, skl, skl,       "Intel(R) Skylake")
 CHIPSET(0x193A, skl, skl,       "Intel(R) Skylake")
 CHIPSET(0x193B, skl, skl,       "Intel(R) Skylake")
 CHIPSET(0x193D, skl, skl,       "Intel(R) Skylake")
+CHIPSET(0x0A84, bxt, bxt,       "Intel(R) Broxton")
+CHIPSET(0x1A84, bxt, bxt,       "Intel(R) Broxton")
+CHIPSET(0x5A84, bxt, bxt,       "Intel(R) Broxton")
diff --git a/src/intel_driver.h b/src/intel_driver.h
index 3c20ce4..def5f9e 100644
--- a/src/intel_driver.h
+++ b/src/intel_driver.h
@@ -136,6 +136,7 @@ struct intel_device_info
     unsigned int is_baytrail    : 1; /* gen7 */
     unsigned int is_haswell     : 1; /* gen7 */
     unsigned int is_cherryview  : 1; /* gen8 */
+    unsigned int is_broxton     : 1; /* gen9 */
 };
 
 struct intel_driver_data 
-- 
cgit v1.2.3


From 5ec92f48aeff12c7db0a96b65aca44feb4965d92 Mon Sep 17 00:00:00 2001
From: Peng Chen <peng.c.chen@intel.com>
Date: Mon, 15 Jun 2015 22:28:22 +0800
Subject: support HEVC 10bits decoding

v2: code cleanup

v3: store shift in an int to make it more readable (Emil)

Signed-off-by: Peng Chen <peng.c.chen@intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Cc: Emil Velikov <emil.l.velikov@gmail.com>
---
 src/gen9_mfd.c           |  46 ++++++++++++++---
 src/i965_decoder_utils.c |  21 +++++++-
 src/i965_defines.h       |   2 +
 src/i965_device_info.c   |   7 ++-
 src/i965_drv_video.c     | 127 +++++++++++++++++++++++++++++++++--------------
 src/i965_drv_video.h     |   2 +
 6 files changed, 157 insertions(+), 48 deletions(-)

diff --git a/src/gen9_mfd.c b/src/gen9_mfd.c
index da76378..dab4213 100644
--- a/src/gen9_mfd.c
+++ b/src/gen9_mfd.c
@@ -109,6 +109,7 @@ gen9_hcpd_hevc_decode_init(VADriverContextP ctx,
     VAPictureParameterBufferHEVC *pic_param;
     struct object_surface *obj_surface;
     uint32_t size;
+    int size_shift = 3;
 
     assert(decode_state->pic_param && decode_state->pic_param->buffer);
     pic_param = (VAPictureParameterBufferHEVC *)decode_state->pic_param->buffer;
@@ -134,12 +135,16 @@ gen9_hcpd_hevc_decode_init(VADriverContextP ctx,
     hevc_ensure_surface_bo(ctx, decode_state, obj_surface, pic_param);
     gen9_hcpd_init_hevc_surface(ctx, pic_param, obj_surface, gen9_hcpd_context);
 
-    size = ALIGN(gen9_hcpd_context->picture_width_in_pixels, 32) >> 3;
+    if((pic_param->bit_depth_luma_minus8 > 0)
+        || (pic_param->bit_depth_chroma_minus8 > 0))
+        size_shift = 2;
+
+    size = ALIGN(gen9_hcpd_context->picture_width_in_pixels, 32) >> size_shift;
     size <<= 6;
     ALLOC_GEN_BUFFER((&gen9_hcpd_context->deblocking_filter_line_buffer), "line buffer", size);
     ALLOC_GEN_BUFFER((&gen9_hcpd_context->deblocking_filter_tile_line_buffer), "tile line buffer", size);
 
-    size = ALIGN(gen9_hcpd_context->picture_height_in_pixels + 6 * gen9_hcpd_context->picture_height_in_ctbs, 32) >> 3;
+    size = ALIGN(gen9_hcpd_context->picture_height_in_pixels + 6 * gen9_hcpd_context->picture_height_in_ctbs, 32) >> size_shift;
     size <<= 6;
     ALLOC_GEN_BUFFER((&gen9_hcpd_context->deblocking_filter_tile_column_buffer), "tile column buffer", size);
 
@@ -158,15 +163,15 @@ gen9_hcpd_hevc_decode_init(VADriverContextP ctx,
     size <<= 6;
     ALLOC_GEN_BUFFER((&gen9_hcpd_context->metadata_tile_column_buffer), "metadata tile column buffer", size);
 
-    size = ALIGN(((gen9_hcpd_context->picture_width_in_pixels >> 1) + 3 * gen9_hcpd_context->picture_width_in_ctbs), 16) >> 3;
+    size = ALIGN(((gen9_hcpd_context->picture_width_in_pixels >> 1) + 3 * gen9_hcpd_context->picture_width_in_ctbs), 16) >> size_shift;
     size <<= 6;
     ALLOC_GEN_BUFFER((&gen9_hcpd_context->sao_line_buffer), "sao line buffer", size);
 
-    size = ALIGN(((gen9_hcpd_context->picture_width_in_pixels >> 1) + 6 * gen9_hcpd_context->picture_width_in_ctbs), 16) >> 3;
+    size = ALIGN(((gen9_hcpd_context->picture_width_in_pixels >> 1) + 6 * gen9_hcpd_context->picture_width_in_ctbs), 16) >> size_shift;
     size <<= 6;
     ALLOC_GEN_BUFFER((&gen9_hcpd_context->sao_tile_line_buffer), "sao tile line buffer", size);
 
-    size = ALIGN(((gen9_hcpd_context->picture_height_in_pixels >> 1) + 6 * gen9_hcpd_context->picture_height_in_ctbs), 16) >> 3;
+    size = ALIGN(((gen9_hcpd_context->picture_height_in_pixels >> 1) + 6 * gen9_hcpd_context->picture_height_in_ctbs), 16) >> size_shift;
     size <<= 6;
     ALLOC_GEN_BUFFER((&gen9_hcpd_context->sao_tile_column_buffer), "sao tile column buffer", size);
 
@@ -208,9 +213,11 @@ gen9_hcpd_surface_state(VADriverContextP ctx,
     struct intel_batchbuffer *batch = gen9_hcpd_context->base.batch;
     struct object_surface *obj_surface = decode_state->render_object;
     unsigned int y_cb_offset;
+    VAPictureParameterBufferHEVC *pic_param;
 
     assert(obj_surface);
 
+    pic_param = (VAPictureParameterBufferHEVC *)decode_state->pic_param->buffer;
     y_cb_offset = obj_surface->y_cb_offset;
 
     BEGIN_BCS_BATCH(batch, 3);
@@ -219,9 +226,19 @@ gen9_hcpd_surface_state(VADriverContextP ctx,
     OUT_BCS_BATCH(batch,
                   (0 << 28) |                   /* surface id */
                   (obj_surface->width - 1));    /* pitch - 1 */
-    OUT_BCS_BATCH(batch,
+    if((pic_param->bit_depth_luma_minus8 > 0)
+        || (pic_param->bit_depth_chroma_minus8 > 0))
+    {
+        OUT_BCS_BATCH(batch,
+                  (SURFACE_FORMAT_P010 << 28) |
+                  y_cb_offset);
+    }
+    else
+    {
+        OUT_BCS_BATCH(batch,
                   (SURFACE_FORMAT_PLANAR_420_8 << 28) |
                   y_cb_offset);
+    }
 
     ADVANCE_BCS_BATCH(batch);
 }
@@ -466,6 +483,8 @@ gen9_hcpd_pic_state(VADriverContextP ctx,
                   pic_param->slice_parsing_fields.bits.sample_adaptive_offset_enabled_flag << 3 |
                   0);
     OUT_BCS_BATCH(batch,
+                  pic_param->bit_depth_luma_minus8 << 27 |
+                  pic_param->bit_depth_chroma_minus8 << 24 |
                   pcm_sample_bit_depth_luma_minus1 << 20 |
                   pcm_sample_bit_depth_chroma_minus1 << 16 |
                   pic_param->max_transform_hierarchy_depth_inter << 13 |
@@ -760,6 +779,7 @@ gen9_hcpd_slice_state(VADriverContextP ctx,
     struct intel_batchbuffer *batch = gen9_hcpd_context->base.batch;
     int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos;
     unsigned short collocated_ref_idx, collocated_from_l0_flag;
+    int sliceqp_sign_flag = 0, sliceqp = 0;
 
     slice_hor_pos = slice_param->slice_segment_address % gen9_hcpd_context->picture_width_in_ctbs;
     slice_ver_pos = slice_param->slice_segment_address / gen9_hcpd_context->picture_width_in_ctbs;
@@ -791,6 +811,17 @@ gen9_hcpd_slice_state(VADriverContextP ctx,
         collocated_from_l0_flag = gen9_hcpd_context->first_inter_slice_collocated_from_l0_flag;
     }
 
+    sliceqp = pic_param->init_qp_minus26 + 26 + slice_param->slice_qp_delta;
+    if((pic_param->bit_depth_luma_minus8 > 0)
+        || (pic_param->bit_depth_chroma_minus8 > 0))
+    {
+        if(sliceqp < 0)
+        {
+            sliceqp_sign_flag = 1;
+            sliceqp = -sliceqp;
+        }
+    }
+
     BEGIN_BCS_BATCH(batch, 9);
 
     OUT_BCS_BATCH(batch, HCP_SLICE_STATE | (9 - 2));
@@ -804,9 +835,10 @@ gen9_hcpd_slice_state(VADriverContextP ctx,
     OUT_BCS_BATCH(batch,
                   (slice_param->slice_cr_qp_offset & 0x1f) << 17 |
                   (slice_param->slice_cb_qp_offset & 0x1f) << 12 |
-                  (pic_param->init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 6 |
+                  sliceqp << 6 |
                   slice_param->LongSliceFlags.fields.slice_temporal_mvp_enabled_flag << 5 |
                   slice_param->LongSliceFlags.fields.dependent_slice_segment_flag << 4 |
+                  sliceqp_sign_flag << 3 |
                   !next_slice_param << 2 |
                   slice_param->LongSliceFlags.fields.slice_type);
     OUT_BCS_BATCH(batch,
diff --git a/src/i965_decoder_utils.c b/src/i965_decoder_utils.c
index 3085a56..53a5aa1 100644
--- a/src/i965_decoder_utils.c
+++ b/src/i965_decoder_utils.c
@@ -1121,9 +1121,26 @@ hevc_ensure_surface_bo(
 )
 {
     VAStatus va_status = VA_STATUS_SUCCESS;
+    int update = 0;
+    unsigned int fourcc = VA_FOURCC_NV12;
+
+    if((pic_param->bit_depth_luma_minus8 > 0)
+        || (pic_param->bit_depth_chroma_minus8 > 0))
+    {
+        if(obj_surface->fourcc != VA_FOURCC_P010)
+        {
+            update = 1;
+            fourcc = VA_FOURCC_P010;
+        }
+    }
+    else if(obj_surface->fourcc != VA_FOURCC_NV12)
+    {
+        update = 1;
+        fourcc = VA_FOURCC_NV12;
+    }
 
     /* (Re-)allocate the underlying surface buffer store, if necessary */
-    if (!obj_surface->bo || obj_surface->fourcc != VA_FOURCC_NV12) {
+    if (!obj_surface->bo || update) {
         struct i965_driver_data * const i965 = i965_driver_data(ctx);
 
         i965_destroy_surface_storage(obj_surface);
@@ -1131,7 +1148,7 @@ hevc_ensure_surface_bo(
         va_status = i965_check_alloc_surface_bo(ctx,
                                                 obj_surface,
                                                 i965->codec_info->has_tiled_surface,
-                                                VA_FOURCC_NV12,
+                                                fourcc,
                                                 SUBSAMPLE_YUV420);
     }
 
diff --git a/src/i965_defines.h b/src/i965_defines.h
index 86a3725..65c0b11 100755
--- a/src/i965_defines.h
+++ b/src/i965_defines.h
@@ -797,6 +797,8 @@
 #define SURFACE_FORMAT_R8B8_UNORM       10
 #define SURFACE_FORMAT_R8_UNORM         11
 #define SURFACE_FORMAT_Y8_UNORM         12
+#define SURFACE_FORMAT_P010             13
+#define SURFACE_FORMAT_P016             14
 
 #define AVS_FILTER_ADAPTIVE_8_TAP       0
 #define AVS_FILTER_NEAREST              1
diff --git a/src/i965_device_info.c b/src/i965_device_info.c
index a844374..db904ae 100644
--- a/src/i965_device_info.c
+++ b/src/i965_device_info.c
@@ -44,7 +44,10 @@
 /* Extra set of chroma formats supported for JPEG encoding (beyond YUV 4:2:0) */
 #define EXTRA_JPEG_ENC_CHROMA_FORMATS \
     (VA_RT_FORMAT_YUV400| VA_RT_FORMAT_YUV422 | VA_RT_FORMAT_YUV444 | VA_RT_FORMAT_RGB32)
-     
+
+#define EXTRA_HEVC_DEC_CHROMA_FORMATS \
+    (VA_RT_FORMAT_YUV420_10BPP)
+
 /* Defines VA profile as a 32-bit unsigned integer mask */
 #define VA_PROFILE_MASK(PROFILE) \
     (1U << VAProfile##PROFILE)
@@ -377,6 +380,7 @@ static struct hw_codec_info bxt_hw_codec_info = {
     .h264_dec_chroma_formats = EXTRA_H264_DEC_CHROMA_FORMATS,
     .jpeg_dec_chroma_formats = EXTRA_JPEG_DEC_CHROMA_FORMATS,
     .jpeg_enc_chroma_formats = EXTRA_JPEG_ENC_CHROMA_FORMATS,
+    .hevc_dec_chroma_formats = EXTRA_HEVC_DEC_CHROMA_FORMATS,
 
     .has_mpeg2_decoding = 1,
     .has_h264_decoding = 1,
@@ -395,6 +399,7 @@ static struct hw_codec_info bxt_hw_codec_info = {
     .has_h264_mvc_encoding = 1,
     .has_hevc_decoding = 1,
     .has_hevc_encoding = 1,
+    .has_hevc10_decoding = 1,
 
     .num_filters = 5,
     .filters = {
diff --git a/src/i965_drv_video.c b/src/i965_drv_video.c
index 54c7030..e52e982 100644
--- a/src/i965_drv_video.c
+++ b/src/i965_drv_video.c
@@ -106,6 +106,9 @@
 #define HAS_HEVC_ENCODING(ctx)          ((ctx)->codec_info->has_hevc_encoding && \
                                          (ctx)->intel.has_bsd)
 
+#define HAS_HEVC10_DECODING(ctx)        ((ctx)->codec_info->has_hevc10_decoding && \
+                                         (ctx)->intel.has_bsd)
+
 static int get_sampling_from_fourcc(unsigned int fourcc);
 
 /* Check whether we are rendering to X11 (VA/X11 or VA/GLX API) */
@@ -141,6 +144,8 @@ static int get_sampling_from_fourcc(unsigned int fourcc);
 #define I_YV12  2, 2, 3, {I965_8BITS, I965_2BITS, I965_2BITS}, 3, { {PLANE_0, OFFSET_0}, {PLANE_2, OFFSET_0}, {PLANE_1, OFFSET_0} }
 #define I_IMC1  I_YV12
 
+#define I_P010  2, 2, 2, {I965_16BITS, I965_8BITS}, 3, { {PLANE_0, OFFSET_0}, {PLANE_1, OFFSET_0}, {PLANE_1, OFFSET_16} }
+
 #define I_422H  2, 1, 3, {I965_8BITS, I965_4BITS, I965_4BITS}, 3, { {PLANE_0, OFFSET_0}, {PLANE_1, OFFSET_0}, {PLANE_2, OFFSET_0} }
 #define I_422V  1, 2, 3, {I965_8BITS, I965_4BITS, I965_4BITS}, 3, { {PLANE_0, OFFSET_0}, {PLANE_1, OFFSET_0}, {PLANE_2, OFFSET_0} }
 #define I_YV16  2, 1, 3, {I965_8BITS, I965_4BITS, I965_4BITS}, 3, { {PLANE_0, OFFSET_0}, {PLANE_2, OFFSET_0}, {PLANE_1, OFFSET_0} }
@@ -185,6 +190,8 @@ static const i965_fourcc_info i965_fourcc_infos[] = {
     DEF_YUV(YV12, YUV420, I_SI),
     DEF_YUV(IMC1, YUV420, I_S),
 
+    DEF_YUV(P010, YUV420, I_SI),
+
     DEF_YUV(422H, YUV422H, I_SI),
     DEF_YUV(422V, YUV422V, I_S),
     DEF_YUV(YV16, YUV422H, I_S),
@@ -580,6 +587,10 @@ i965_QueryConfigProfiles(VADriverContextP ctx,
         profile_list[i++] = VAProfileHEVCMain;
     }
 
+    if (HAS_HEVC10_DECODING(i965)) {
+        profile_list[i++] = VAProfileHEVCMain10;
+    }
+
     if (i965->wrapper_pdrvctx) {
         VAProfile wrapper_list[4];
         int wrapper_num;
@@ -683,6 +694,12 @@ i965_QueryConfigEntrypoints(VADriverContextP ctx,
 
         break;
 
+    case VAProfileHEVCMain10:
+        if (HAS_HEVC10_DECODING(i965))
+            entrypoint_list[n++] = VAEntrypointVLD;
+
+        break;
+
     case VAProfileVP9Profile0:
         if (i965->wrapper_pdrvctx) {
             VAStatus va_status = VA_STATUS_SUCCESS;
@@ -794,6 +811,14 @@ i965_validate_config(VADriverContextP ctx, VAProfile profile,
 
         break;
 
+    case VAProfileHEVCMain10:
+        if (HAS_HEVC10_DECODING(i965) && (entrypoint == VAEntrypointVLD))
+            va_status = VA_STATUS_SUCCESS;
+        else
+            va_status = VA_STATUS_ERROR_UNSUPPORTED_ENTRYPOINT;
+
+        break;
+
     case VAProfileVP9Profile0:
         if (i965->wrapper_pdrvctx)
             va_status = VA_STATUS_SUCCESS;
@@ -834,9 +859,13 @@ i965_get_default_chroma_formats(VADriverContextP ctx, VAProfile profile,
             chroma_formats |= i965->codec_info->jpeg_dec_chroma_formats;
         if (HAS_JPEG_ENCODING(i965) && entrypoint == VAEntrypointEncPicture)
             chroma_formats |= i965->codec_info->jpeg_enc_chroma_formats;
-        
         break;
 
+    case VAProfileHEVCMain10:
+        chroma_formats = 0; // clear YUV420 8bits format support
+        if (HAS_HEVC10_DECODING(i965) && entrypoint == VAEntrypointVLD)
+            chroma_formats |= i965->codec_info->hevc_dec_chroma_formats;
+        break;
     default:
         break;
     }
@@ -1197,6 +1226,7 @@ i965_suface_external_memory(VADriverContextP ctx,
 
     switch (obj_surface->fourcc) {
     case VA_FOURCC_NV12:
+    case VA_FOURCC_P010:
         ASSERT_RET(memory_attibute->num_planes == 2, VA_STATUS_ERROR_INVALID_PARAMETER);
         ASSERT_RET(memory_attibute->pitches[0] == memory_attibute->pitches[1], VA_STATUS_ERROR_INVALID_PARAMETER);
 
@@ -1424,6 +1454,7 @@ i965_CreateSurfaces2(
     /* support 420 & 422 & RGB32 format, 422 and RGB32 are only used
      * for post-processing (including color conversion) */
     if (VA_RT_FORMAT_YUV420 != format &&
+        VA_RT_FORMAT_YUV420_10BPP != format &&
         VA_RT_FORMAT_YUV422 != format &&
         VA_RT_FORMAT_YUV444 != format &&
         VA_RT_FORMAT_YUV411 != format &&
@@ -1488,10 +1519,10 @@ i965_CreateSurfaces2(
                 if (memory_attibute->pitches[0]) {
                     int bpp_1stplane = bpp_1stplane_by_fourcc(expected_fourcc);
                     ASSERT_RET(bpp_1stplane, VA_STATUS_ERROR_INVALID_PARAMETER);
-                    obj_surface->width = memory_attibute->pitches[0]/bpp_1stplane;
+                    obj_surface->width = memory_attibute->pitches[0];
                     obj_surface->user_h_stride_set = true;
                     ASSERT_RET(IS_ALIGNED(obj_surface->width, 16), VA_STATUS_ERROR_INVALID_PARAMETER);
-                    ASSERT_RET(obj_surface->width >= width, VA_STATUS_ERROR_INVALID_PARAMETER);
+                    ASSERT_RET(obj_surface->width >= width * bpp_1stplane, VA_STATUS_ERROR_INVALID_PARAMETER);
 
                     if (memory_attibute->offsets[1]) {
                         ASSERT_RET(!memory_attibute->offsets[0], VA_STATUS_ERROR_INVALID_PARAMETER);
@@ -3086,7 +3117,7 @@ i965_encoder_render_picture(VADriverContextP ctx,
             if ((param->type == VAEncPackedHeaderRawData) ||
                 (param->type == VAEncPackedHeaderSlice)) {
                 vaStatus = I965_RENDER_ENCODE_BUFFER(packed_header_params_ext);
-            } else if((obj_config->profile == VAProfileHEVCMain)&&
+            } else if((obj_config->profile == VAProfileHEVCMain) &&
                 (encode->last_packed_header_type == VAEncPackedHeaderSequence)) {
                 vaStatus = i965_encoder_render_packed_header_parameter_buffer(ctx,
                                                                           obj_context,
@@ -3180,7 +3211,7 @@ i965_encoder_render_picture(VADriverContextP ctx,
                     ((encode->last_packed_header_type & (~VAEncPackedHeaderMiscMask)) != 0)),
                     VA_STATUS_ERROR_ENCODING_ERROR);
 
-                if((obj_config->profile == VAProfileHEVCMain)&&
+                if((obj_config->profile == VAProfileHEVCMain) &&
                     (encode->last_packed_header_type == VAEncPackedHeaderSequence)) {
 
                         vaStatus = i965_encoder_render_packed_header_data_buffer(ctx,
@@ -3774,25 +3805,29 @@ i965_check_alloc_surface_bo(VADriverContextP ctx,
     obj_surface->x_cb_offset = 0; /* X offset is always 0 */
     obj_surface->x_cr_offset = 0;
 
+    int bpp_1stplane = bpp_1stplane_by_fourcc(fourcc);
+
+    if (obj_surface->user_h_stride_set) {
+        ASSERT_RET(IS_ALIGNED(obj_surface->width, 128), VA_STATUS_ERROR_INVALID_PARAMETER);
+    } else
+        obj_surface->width = ALIGN(obj_surface->orig_width * bpp_1stplane, 128);
+
+    if (obj_surface->user_v_stride_set) {
+        ASSERT_RET(IS_ALIGNED(obj_surface->height, 32), VA_STATUS_ERROR_INVALID_PARAMETER);
+    } else
+        obj_surface->height = ALIGN(obj_surface->orig_height, 32);
+
     if ((tiled && !obj_surface->user_disable_tiling)) {
         ASSERT_RET(fourcc != VA_FOURCC_I420 &&
                fourcc != VA_FOURCC_IYUV &&
                fourcc != VA_FOURCC_YV12,
                VA_STATUS_ERROR_UNSUPPORTED_RT_FORMAT);
-        if (obj_surface->user_h_stride_set) {
-            ASSERT_RET(IS_ALIGNED(obj_surface->width, 128), VA_STATUS_ERROR_INVALID_PARAMETER);
-        } else
-            obj_surface->width = ALIGN(obj_surface->orig_width, 128);
-
-        if (obj_surface->user_v_stride_set) {
-            ASSERT_RET(IS_ALIGNED(obj_surface->height, 32), VA_STATUS_ERROR_INVALID_PARAMETER);
-        } else
-            obj_surface->height = ALIGN(obj_surface->orig_height, 32);
 
         region_height = obj_surface->height;
 
         switch (fourcc) {
         case VA_FOURCC_NV12:
+        case VA_FOURCC_P010:
             assert(subsampling == SUBSAMPLE_YUV420);
             obj_surface->cb_cr_pitch = obj_surface->width;
             obj_surface->cb_cr_width = obj_surface->orig_width / 2;
@@ -3929,6 +3964,7 @@ i965_check_alloc_surface_bo(VADriverContextP ctx,
 
         switch (fourcc) {
         case VA_FOURCC_NV12:
+        case VA_FOURCC_P010:
             obj_surface->y_cb_offset = obj_surface->height;
             obj_surface->y_cr_offset = obj_surface->height;
             obj_surface->cb_cr_width = obj_surface->orig_width / 2;
@@ -4103,6 +4139,7 @@ VAStatus i965_DeriveImage(VADriverContextP ctx,
         break;
 
     case VA_FOURCC_NV12:
+    case VA_FOURCC_P010:
         image->num_planes = 2;
         image->pitches[0] = w_pitch; /* Y */
         image->offsets[0] = 0;
@@ -5439,7 +5476,13 @@ i965_QuerySurfaceAttributes(VADriverContextP ctx,
                 attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE;
                 attribs[i].value.value.i = VA_FOURCC_444P;
                 i++;
-            } else {
+            } else if (obj_config->profile == VAProfileHEVCMain10) {
+                attribs[i].type = VASurfaceAttribPixelFormat;
+                attribs[i].value.type = VAGenericValueTypeInteger;
+                attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE;
+                attribs[i].value.value.i = VA_FOURCC_P010;
+                i++;
+             } else {
                 attribs[i].type = VASurfaceAttribPixelFormat;
                 attribs[i].value.type = VAGenericValueTypeInteger;
                 attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE;
@@ -5565,29 +5608,37 @@ i965_QuerySurfaceAttributes(VADriverContextP ctx,
         } else if (obj_config->entrypoint == VAEntrypointEncSlice ||  /* encode */
                    obj_config->entrypoint == VAEntrypointVideoProc) { /* vpp */
 
-            attribs[i].type = VASurfaceAttribPixelFormat;
-            attribs[i].value.type = VAGenericValueTypeInteger;
-            attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE;
-            attribs[i].value.value.i = VA_FOURCC_NV12;
-            i++;
-
-            attribs[i].type = VASurfaceAttribPixelFormat;
-            attribs[i].value.type = VAGenericValueTypeInteger;
-            attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE;
-            attribs[i].value.value.i = VA_FOURCC_I420;
-            i++;
-
-            attribs[i].type = VASurfaceAttribPixelFormat;
-            attribs[i].value.type = VAGenericValueTypeInteger;
-            attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE;
-            attribs[i].value.value.i = VA_FOURCC_YV12;
-            i++;
-
-            attribs[i].type = VASurfaceAttribPixelFormat;
-            attribs[i].value.type = VAGenericValueTypeInteger;
-            attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE;
-            attribs[i].value.value.i = VA_FOURCC_IMC3;
-            i++;
+            if (obj_config->profile == VAProfileHEVCMain10) {
+                attribs[i].type = VASurfaceAttribPixelFormat;
+                attribs[i].value.type = VAGenericValueTypeInteger;
+                attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE;
+                attribs[i].value.value.i = VA_FOURCC_P010;
+                i++;
+            } else {
+              attribs[i].type = VASurfaceAttribPixelFormat;
+              attribs[i].value.type = VAGenericValueTypeInteger;
+              attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE;
+              attribs[i].value.value.i = VA_FOURCC_NV12;
+              i++;
+
+              attribs[i].type = VASurfaceAttribPixelFormat;
+              attribs[i].value.type = VAGenericValueTypeInteger;
+              attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE;
+              attribs[i].value.value.i = VA_FOURCC_I420;
+              i++;
+
+              attribs[i].type = VASurfaceAttribPixelFormat;
+              attribs[i].value.type = VAGenericValueTypeInteger;
+              attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE;
+              attribs[i].value.value.i = VA_FOURCC_YV12;
+              i++;
+
+              attribs[i].type = VASurfaceAttribPixelFormat;
+              attribs[i].value.type = VAGenericValueTypeInteger;
+              attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE;
+              attribs[i].value.value.i = VA_FOURCC_IMC3;
+              i++;
+            }
 
             if (obj_config->entrypoint == VAEntrypointVideoProc) {
                 attribs[i].type = VASurfaceAttribPixelFormat;
diff --git a/src/i965_drv_video.h b/src/i965_drv_video.h
index f688ec2..44983da 100644
--- a/src/i965_drv_video.h
+++ b/src/i965_drv_video.h
@@ -365,6 +365,7 @@ struct hw_codec_info
     unsigned int h264_dec_chroma_formats;
     unsigned int jpeg_dec_chroma_formats;
     unsigned int jpeg_enc_chroma_formats;
+    unsigned int hevc_dec_chroma_formats;
 
     unsigned int has_mpeg2_decoding:1;
     unsigned int has_mpeg2_encoding:1;
@@ -385,6 +386,7 @@ struct hw_codec_info
     unsigned int has_h264_mvc_encoding:1;
     unsigned int has_hevc_decoding:1;
     unsigned int has_hevc_encoding:1;
+    unsigned int has_hevc10_decoding:1;
 
     unsigned int num_filters;
     struct i965_filter filters[VAProcFilterCount];
-- 
cgit v1.2.3


From bace1e29c669f3fe47cb41c57fc817b493fc7882 Mon Sep 17 00:00:00 2001
From: "Xiang, Haihao" <haihao.xiang@intel.com>
Date: Tue, 7 Jul 2015 16:32:14 +0800
Subject: Add support for P010 in vaPutSurface() in a X window system

Currently it converts P010 to RGBA32 because the drawable to vaPutSurface() is RGBA color

v2: P010 has interleaved UV planar (Peng)

v3: change commit log

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: peng.chen <peng.c.chen@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Cc: Emil Velikov <emil.l.velikov@gmail.com>
---
 src/gen9_render.c | 60 ++++++++++++++++++++++++++++++++++---------------------
 1 file changed, 37 insertions(+), 23 deletions(-)

diff --git a/src/gen9_render.c b/src/gen9_render.c
index b45543a..4c24443 100644
--- a/src/gen9_render.c
+++ b/src/gen9_render.c
@@ -249,35 +249,48 @@ gen9_render_src_surfaces_state(
     rh = obj_surface->orig_height;
     region = obj_surface->bo;
 
-    gen9_render_src_surface_state(ctx, 1, region, 0, rw, rh, region_pitch, I965_SURFACEFORMAT_R8_UNORM, flags);     /* Y */
-    gen9_render_src_surface_state(ctx, 2, region, 0, rw, rh, region_pitch, I965_SURFACEFORMAT_R8_UNORM, flags);
-
-    if (obj_surface->fourcc == VA_FOURCC('N', 'V', '1', '2')) {
+    if (obj_surface->fourcc == VA_FOURCC('P', '0', '1', '0')) {
+        gen9_render_src_surface_state(ctx, 1, region, 0, rw, rh, region_pitch, I965_SURFACEFORMAT_R16_UNORM, flags);     /* Y */
+        gen9_render_src_surface_state(ctx, 2, region, 0, rw, rh, region_pitch, I965_SURFACEFORMAT_R16_UNORM, flags);
         gen9_render_src_surface_state(ctx, 3, region,
                                       region_pitch * obj_surface->y_cb_offset,
                                       obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
-                                      I965_SURFACEFORMAT_R8G8_UNORM, flags); /* UV */
+                                      I965_SURFACEFORMAT_R16G16_UNORM, flags); /* UV */
         gen9_render_src_surface_state(ctx, 4, region,
                                       region_pitch * obj_surface->y_cb_offset,
                                       obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
-                                      I965_SURFACEFORMAT_R8G8_UNORM, flags);
+                                      I965_SURFACEFORMAT_R16G16_UNORM, flags);
     } else {
-        gen9_render_src_surface_state(ctx, 3, region,
-                                      region_pitch * obj_surface->y_cb_offset,
-                                      obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
-                                      I965_SURFACEFORMAT_R8_UNORM, flags); /* U */
-        gen9_render_src_surface_state(ctx, 4, region,
-                                      region_pitch * obj_surface->y_cb_offset,
-                                      obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
-                                      I965_SURFACEFORMAT_R8_UNORM, flags);
-        gen9_render_src_surface_state(ctx, 5, region,
-                                      region_pitch * obj_surface->y_cr_offset,
-                                      obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
-                                      I965_SURFACEFORMAT_R8_UNORM, flags); /* V */
-        gen9_render_src_surface_state(ctx, 6, region,
-                                      region_pitch * obj_surface->y_cr_offset,
-                                      obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
-                                      I965_SURFACEFORMAT_R8_UNORM, flags);
+        gen9_render_src_surface_state(ctx, 1, region, 0, rw, rh, region_pitch, I965_SURFACEFORMAT_R8_UNORM, flags);     /* Y */
+        gen9_render_src_surface_state(ctx, 2, region, 0, rw, rh, region_pitch, I965_SURFACEFORMAT_R8_UNORM, flags);
+
+        if (obj_surface->fourcc == VA_FOURCC('N', 'V', '1', '2')) {
+            gen9_render_src_surface_state(ctx, 3, region,
+                                          region_pitch * obj_surface->y_cb_offset,
+                                          obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
+                                          I965_SURFACEFORMAT_R8G8_UNORM, flags); /* UV */
+            gen9_render_src_surface_state(ctx, 4, region,
+                                          region_pitch * obj_surface->y_cb_offset,
+                                          obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
+                                          I965_SURFACEFORMAT_R8G8_UNORM, flags);
+        } else {
+            gen9_render_src_surface_state(ctx, 3, region,
+                                          region_pitch * obj_surface->y_cb_offset,
+                                          obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
+                                          I965_SURFACEFORMAT_R8_UNORM, flags); /* U */
+            gen9_render_src_surface_state(ctx, 4, region,
+                                          region_pitch * obj_surface->y_cb_offset,
+                                          obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
+                                          I965_SURFACEFORMAT_R8_UNORM, flags);
+            gen9_render_src_surface_state(ctx, 5, region,
+                                          region_pitch * obj_surface->y_cr_offset,
+                                          obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
+                                          I965_SURFACEFORMAT_R8_UNORM, flags); /* V */
+            gen9_render_src_surface_state(ctx, 6, region,
+                                          region_pitch * obj_surface->y_cr_offset,
+                                          obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
+                                          I965_SURFACEFORMAT_R8_UNORM, flags);
+        }
     }
 }
 
@@ -773,7 +786,8 @@ gen9_render_upload_constants(VADriverContextP ctx,
 
         *constant_buffer = 2;
     } else {
-        if (obj_surface->fourcc == VA_FOURCC('N', 'V', '1', '2'))
+        if (obj_surface->fourcc == VA_FOURCC('N', 'V', '1', '2') ||
+            obj_surface->fourcc == VA_FOURCC('P', '0', '1', '0'))
             *constant_buffer = 1;
         else
             *constant_buffer = 0;
-- 
cgit v1.2.3


From bcab944bc6e898e209b1e09befb81134c31a0b22 Mon Sep 17 00:00:00 2001
From: Sirisha Muppavarapu <sirisha.muppavarapu@intel.com>
Date: Thu, 28 May 2015 08:08:52 -0700
Subject: VP9 HWDec: Added profile and entrypoint for VAProfileVP9Profile0 in
 the driver

v2: don't export VP9 decoding on BXT because VP9 decoding isn't enabled (Peng)

Signed-off-by: Sirisha Muppavarapu <sirisha.muppavarapu@intel.com>
Signed-off-by: Pengfei Qu <Pengfei.Qu@intel.com>
Signed-off-by: peng.chen <peng.c.chen@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
---
 src/i965_drv_video.c | 14 +++++++++++++-
 src/i965_drv_video.h |  1 +
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/src/i965_drv_video.c b/src/i965_drv_video.c
index e52e982..7b7bdf6 100644
--- a/src/i965_drv_video.c
+++ b/src/i965_drv_video.c
@@ -106,6 +106,9 @@
 #define HAS_HEVC_ENCODING(ctx)          ((ctx)->codec_info->has_hevc_encoding && \
                                          (ctx)->intel.has_bsd)
 
+#define HAS_VP9_DECODING(ctx)          ((ctx)->codec_info->has_vp9_decoding && \
+                                         (ctx)->intel.has_bsd)
+
 #define HAS_HEVC10_DECODING(ctx)        ((ctx)->codec_info->has_hevc10_decoding && \
                                          (ctx)->intel.has_bsd)
 
@@ -591,6 +594,10 @@ i965_QueryConfigProfiles(VADriverContextP ctx,
         profile_list[i++] = VAProfileHEVCMain10;
     }
 
+    if(HAS_VP9_DECODING(i965)) {
+        profile_list[i++] = VAProfileVP9Profile0;
+    }
+
     if (i965->wrapper_pdrvctx) {
         VAProfile wrapper_list[4];
         int wrapper_num;
@@ -701,6 +708,9 @@ i965_QueryConfigEntrypoints(VADriverContextP ctx,
         break;
 
     case VAProfileVP9Profile0:
+        if(HAS_VP9_DECODING(i965))
+            entrypoint_list[n++] = VAEntrypointVLD;
+
         if (i965->wrapper_pdrvctx) {
             VAStatus va_status = VA_STATUS_SUCCESS;
             VADriverContextP pdrvctx = i965->wrapper_pdrvctx;
@@ -820,7 +830,9 @@ i965_validate_config(VADriverContextP ctx, VAProfile profile,
         break;
 
     case VAProfileVP9Profile0:
-        if (i965->wrapper_pdrvctx)
+        if ((HAS_VP9_DECODING(i965)) && (entrypoint == VAEntrypointVLD))
+            va_status = VA_STATUS_SUCCESS;
+        else if (i965->wrapper_pdrvctx)
             va_status = VA_STATUS_SUCCESS;
         else
             va_status = VA_STATUS_ERROR_UNSUPPORTED_ENTRYPOINT;
diff --git a/src/i965_drv_video.h b/src/i965_drv_video.h
index 44983da..bdb7512 100644
--- a/src/i965_drv_video.h
+++ b/src/i965_drv_video.h
@@ -387,6 +387,7 @@ struct hw_codec_info
     unsigned int has_hevc_decoding:1;
     unsigned int has_hevc_encoding:1;
     unsigned int has_hevc10_decoding:1;
+    unsigned int has_vp9_decoding:1;
 
     unsigned int num_filters;
     struct i965_filter filters[VAProcFilterCount];
-- 
cgit v1.2.3


From 9bc5ecadd4ea11ebab1e383632be3448eb8411f4 Mon Sep 17 00:00:00 2001
From: Sirisha Muppavarapu <sirisha.muppavarapu@intel.com>
Date: Thu, 22 Oct 2015 04:31:40 -0400
Subject: VP9 HWDEC:add vp9 table file

Signed-off-by: Pengfei Qu <Pengfei.Qu@intel.com>
Signed-off-by: Sirisha Muppavarapu <sirisha.muppavarapu@intel.com>
Signed-off-by: peng.chen <peng.c.chen@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
---
 src/Makefile.am |   1 +
 src/vp9_probs.h | 640 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 641 insertions(+)
 create mode 100644 src/vp9_probs.h

diff --git a/src/Makefile.am b/src/Makefile.am
index f6db887..ad96102 100755
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -139,6 +139,7 @@ source_h = \
 	intel_version.h		\
 	object_heap.h           \
 	vp8_probs.h             \
+	vp9_probs.h             \
 	sysdeps.h		\
 	va_backend_compat.h	\
 	i965_fourcc.h           \
diff --git a/src/vp9_probs.h b/src/vp9_probs.h
new file mode 100644
index 0000000..757969f
--- /dev/null
+++ b/src/vp9_probs.h
@@ -0,0 +1,640 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+/*
+ * This file defines some vp9 probability tables, and
+ * they are ported from libvpx (https://github.com/webmproject/libvpx/).
+ * The original copyright and licence statement as below.
+ */
+
+/*
+ *  Copyright (c) 2010 The WebM project authors. All Rights Reserved.
+ *
+ *  Use of this source code is governed by a BSD-style license
+ *  that can be found in the LICENSE file in the root of the source
+ *  tree. An additional intellectual property rights grant can be found
+ *  in the file PATENTS.  All contributing project authors may
+ *  be found in the AUTHORS file in the root of the source tree.
+ */
+
+#ifndef VP9_PROBS_H
+#define VP9_PROBS_H
+
+#define TX_SIZE_CONTEXTS 2
+#define TX_SIZES 4
+#define PLANE_TYPES 2
+#define SKIP_CONTEXTS 3
+#define INTER_MODE_CONTEXTS 7
+#define INTER_MODES 4
+#define SWITCHABLE_FILTERS 3
+#define SWITCHABLE_FILTER_CONTEXTS (SWITCHABLE_FILTERS + 1)
+#define MAX_SEGMENTS 8
+#define PREDICTION_PROBS 3
+#define SEG_TREE_PROBS (MAX_SEGMENTS-1)
+#define MV_JOINTS 4
+#define INTRA_INTER_CONTEXTS 4
+#define COMP_INTER_CONTEXTS 5
+#define REF_CONTEXTS 5
+#define BLOCK_SIZE_GROUPS 4
+#define INTRA_MODES 10
+#define PARTITION_PLOFFSET   4  // number of probability models per block size
+#define PARTITION_CONTEXTS (4 * PARTITION_PLOFFSET)
+#define PARTITION_TYPES 4
+#define REF_TYPES 2  // intra=0, inter=1
+#define COEF_BANDS 6
+#define COEFF_CONTEXTS 6
+#define UNCONSTRAINED_NODES         3
+#define MV_CLASSES 11
+#define CLASS0_BITS    1  /* bits at integer precision for class 0 */
+#define CLASS0_SIZE    (1 << CLASS0_BITS)
+#define MV_OFFSET_BITS (MV_CLASSES + CLASS0_BITS - 2)
+#define MV_MAX_BITS    (MV_CLASSES + CLASS0_BITS + 2)
+#define MV_FP_SIZE 4
+#define FRAME_CONTEXTS_LOG2 2
+#define FRAME_CONTEXTS (1 << FRAME_CONTEXTS_LOG2)
+
+#define COEFF_PROB_SIZE 132
+#define COEFF_PROB_NUM 3
+
+#define TX_PROBS_IDX 0
+#define COEFF_PROBS_IDX 64
+#define INTRA_PROBS_IDX 1603
+#define SEG_PROBS_IDX 2010
+
+typedef uint8_t vp9_prob;
+
+#define vpx_memset  memset
+#define vpx_memcpy  memcpy
+
+#define vp9_zero(dest) memset(&dest, 0, sizeof(dest))
+
+#define vp9_copy(dest, src) {            \
+    assert(sizeof(dest) == sizeof(src)); \
+    vpx_memcpy(dest, src, sizeof(src));  \
+}
+
+struct tx_probs {
+  vp9_prob p8x8[TX_SIZE_CONTEXTS][TX_SIZES - 3];
+  vp9_prob p16x16[TX_SIZE_CONTEXTS][TX_SIZES - 2];
+  vp9_prob p32x32[TX_SIZE_CONTEXTS][TX_SIZES - 1];
+};
+
+struct tx_counts {
+  unsigned int p32x32[TX_SIZE_CONTEXTS][TX_SIZES];
+  unsigned int p16x16[TX_SIZE_CONTEXTS][TX_SIZES - 1];
+  unsigned int p8x8[TX_SIZE_CONTEXTS][TX_SIZES - 2];
+  unsigned int tx_totals[TX_SIZES];
+};
+
+typedef struct {
+  vp9_prob sign;
+  vp9_prob classes[MV_CLASSES - 1];
+  vp9_prob class0[CLASS0_SIZE - 1];
+  vp9_prob bits[MV_OFFSET_BITS];
+} nmv_component;
+
+//Modified the nmv_context from libvpx to suit our HW needs
+typedef struct {
+  vp9_prob joints[MV_JOINTS-1];
+  nmv_component comps[2];
+  vp9_prob class0_fp0[CLASS0_SIZE][MV_FP_SIZE - 1];
+  vp9_prob fp0[MV_FP_SIZE - 1];
+  vp9_prob class0_fp1[CLASS0_SIZE][MV_FP_SIZE - 1];
+  vp9_prob fp1[MV_FP_SIZE - 1];
+  vp9_prob class0_hp[2];
+  vp9_prob hp[2];
+} nmv_context;
+
+//Modified the FRAME_CONTEXT from libvpx to suit our HW needs
+typedef struct frame_contexts {
+  struct tx_probs tx_probs;
+  vp9_prob dummy1[52];
+  vp9_prob coeff_probs4x4[COEFF_PROB_SIZE][COEFF_PROB_NUM];
+  vp9_prob coeff_probs8x8[COEFF_PROB_SIZE][COEFF_PROB_NUM];
+  vp9_prob coeff_probs16x16[COEFF_PROB_SIZE][COEFF_PROB_NUM];
+  vp9_prob coeff_probs32x32[COEFF_PROB_SIZE][COEFF_PROB_NUM];
+  vp9_prob dummy2[16];
+  vp9_prob skip_probs[SKIP_CONTEXTS];
+  vp9_prob inter_mode_probs[INTER_MODE_CONTEXTS][INTER_MODES - 1];
+  vp9_prob switchable_interp_prob[SWITCHABLE_FILTER_CONTEXTS]
+                                 [SWITCHABLE_FILTERS - 1];
+  vp9_prob intra_inter_prob[INTRA_INTER_CONTEXTS];
+  vp9_prob comp_inter_prob[COMP_INTER_CONTEXTS];
+  vp9_prob single_ref_prob[REF_CONTEXTS][2];
+  vp9_prob comp_ref_prob[REF_CONTEXTS];
+  vp9_prob y_mode_prob[BLOCK_SIZE_GROUPS][INTRA_MODES - 1];
+  vp9_prob partition_prob[PARTITION_CONTEXTS][PARTITION_TYPES - 1];
+  nmv_context nmvc;
+  vp9_prob dummy3[47];
+  vp9_prob uv_mode_prob[INTRA_MODES][INTRA_MODES - 1];
+  vp9_prob seg_tree_probs[SEG_TREE_PROBS];
+  vp9_prob seg_pred_probs[PREDICTION_PROBS];
+  vp9_prob dummy4[28];
+  int initialized;
+} FRAME_CONTEXT;
+
+
+static const struct tx_probs default_tx_probs = {
+    { { 100 },
+    { 66  } },
+
+    { { 20, 152 },
+    { 15, 101 } },
+
+    { { 3, 136, 37 },
+    { 5, 52,  13 } },
+};
+
+static const vp9_prob default_skip_probs[SKIP_CONTEXTS] = {
+  192, 128, 64
+};
+
+static const vp9_prob default_inter_mode_probs[INTER_MODE_CONTEXTS]
+                                              [INTER_MODES - 1] = {
+  {2,       173,   34},  // 0 = both zero mv
+  {7,       145,   85},  // 1 = one zero mv + one a predicted mv
+  {7,       166,   63},  // 2 = two predicted mvs
+  {7,       94,    66},  // 3 = one predicted/zero and one new mv
+  {8,       64,    46},  // 4 = two new mvs
+  {17,      81,    31},  // 5 = one intra neighbour + x
+  {25,      29,    30},  // 6 = two intra neighbours
+};
+
+static const vp9_prob default_switchable_interp_prob[SWITCHABLE_FILTER_CONTEXTS][SWITCHABLE_FILTERS - 1] = {
+    { 235, 162, },
+    { 36, 255, },
+    { 34, 3, },
+    { 149, 144, },
+};
+
+static const vp9_prob default_intra_inter_p[INTRA_INTER_CONTEXTS] = {
+  9, 102, 187, 225
+};
+
+static const vp9_prob default_comp_inter_p[COMP_INTER_CONTEXTS] = {
+  239, 183, 119,  96,  41
+};
+
+static const vp9_prob default_single_ref_p[REF_CONTEXTS][2] = {
+  {  33,  16 },
+  {  77,  74 },
+  { 142, 142 },
+  { 172, 170 },
+  { 238, 247 }
+};
+
+static const vp9_prob default_comp_ref_p[REF_CONTEXTS] = {
+  50, 126, 123, 221, 226
+};
+
+const vp9_prob vp9_kf_uv_mode_prob[INTRA_MODES][INTRA_MODES - 1] = {
+  { 144,  11,  54, 157, 195, 130,  46,  58, 108 },  // y = dc
+  { 118,  15, 123, 148, 131, 101,  44,  93, 131 },  // y = v
+  { 113,  12,  23, 188, 226, 142,  26,  32, 125 },  // y = h
+  { 120,  11,  50, 123, 163, 135,  64,  77, 103 },  // y = d45
+  { 113,   9,  36, 155, 111, 157,  32,  44, 161 },  // y = d135
+  { 116,   9,  55, 176,  76,  96,  37,  61, 149 },  // y = d117
+  { 115,   9,  28, 141, 161, 167,  21,  25, 193 },  // y = d153
+  { 120,  12,  32, 145, 195, 142,  32,  38,  86 },  // y = d207
+  { 116,  12,  64, 120, 140, 125,  49, 115, 121 },  // y = d63
+  { 102,  19,  66, 162, 182, 122,  35,  59, 128 }   // y = tm
+};
+
+static const vp9_prob default_if_y_probs[BLOCK_SIZE_GROUPS][INTRA_MODES - 1] = {
+  {  65,  32,  18, 144, 162, 194,  41,  51,  98 },  // block_size < 8x8
+  { 132,  68,  18, 165, 217, 196,  45,  40,  78 },  // block_size < 16x16
+  { 173,  80,  19, 176, 240, 193,  64,  35,  46 },  // block_size < 32x32
+  { 221, 135,  38, 194, 248, 121,  96,  85,  29 }   // block_size >= 32x32
+};
+
+static const vp9_prob default_if_uv_probs[INTRA_MODES][INTRA_MODES - 1] = {
+  { 120,   7,  76, 176, 208, 126,  28,  54, 103 },  // y = dc
+  {  48,  12, 154, 155, 139,  90,  34, 117, 119 },  // y = v
+  {  67,   6,  25, 204, 243, 158,  13,  21,  96 },  // y = h
+  {  97,   5,  44, 131, 176, 139,  48,  68,  97 },  // y = d45
+  {  83,   5,  42, 156, 111, 152,  26,  49, 152 },  // y = d135
+  {  80,   5,  58, 178,  74,  83,  33,  62, 145 },  // y = d117
+  {  86,   5,  32, 154, 192, 168,  14,  22, 163 },  // y = d153
+  {  85,   5,  32, 156, 216, 148,  19,  29,  73 },  // y = d207
+  {  77,   7,  64, 116, 132, 122,  37, 126, 120 },  // y = d63
+  { 101,  21, 107, 181, 192, 103,  19,  67, 125 }   // y = tm
+};
+
+static const vp9_prob default_seg_tree_probs[SEG_TREE_PROBS] = {
+    255, 255, 255, 255, 255, 255, 255
+};
+
+static const vp9_prob default_seg_pred_probs[PREDICTION_PROBS] = {
+    255, 255, 255
+};
+
+const vp9_prob vp9_kf_partition_probs[PARTITION_CONTEXTS]
+                                     [PARTITION_TYPES - 1] = {
+  // 8x8 -> 4x4
+  { 158,  97,  94 },  // a/l both not split
+  {  93,  24,  99 },  // a split, l not split
+  {  85, 119,  44 },  // l split, a not split
+  {  62,  59,  67 },  // a/l both split
+  // 16x16 -> 8x8
+  { 149,  53,  53 },  // a/l both not split
+  {  94,  20,  48 },  // a split, l not split
+  {  83,  53,  24 },  // l split, a not split
+  {  52,  18,  18 },  // a/l both split
+  // 32x32 -> 16x16
+  { 150,  40,  39 },  // a/l both not split
+  {  78,  12,  26 },  // a split, l not split
+  {  67,  33,  11 },  // l split, a not split
+  {  24,   7,   5 },  // a/l both split
+  // 64x64 -> 32x32
+  { 174,  35,  49 },  // a/l both not split
+  {  68,  11,  27 },  // a split, l not split
+  {  57,  15,   9 },  // l split, a not split
+  {  12,   3,   3 },  // a/l both split
+};
+
+static const vp9_prob default_partition_probs[PARTITION_CONTEXTS]
+                                             [PARTITION_TYPES - 1] = {
+  // 8x8 -> 4x4
+  { 199, 122, 141 },  // a/l both not split
+  { 147,  63, 159 },  // a split, l not split
+  { 148, 133, 118 },  // l split, a not split
+  { 121, 104, 114 },  // a/l both split
+  // 16x16 -> 8x8
+  { 174,  73,  87 },  // a/l both not split
+  {  92,  41,  83 },  // a split, l not split
+  {  82,  99,  50 },  // l split, a not split
+  {  53,  39,  39 },  // a/l both split
+  // 32x32 -> 16x16
+  { 177,  58,  59 },  // a/l both not split
+  {  68,  26,  63 },  // a split, l not split
+  {  52,  79,  25 },  // l split, a not split
+  {  17,  14,  12 },  // a/l both split
+  // 64x64 -> 32x32
+  { 222,  34,  30 },  // a/l both not split
+  {  72,  16,  44 },  // a split, l not split
+  {  58,  32,  12 },  // l split, a not split
+  {  10,   7,   6 },  // a/l both split
+};
+
+//Rearranged the values for better usage
+static const nmv_context default_nmv_context = {
+  {32, 64, 96},
+  {
+    { // Vertical component
+      128,                                                  // sign
+      {224, 144, 192, 168, 192, 176, 192, 198, 198, 245},   // class
+      {216},                                                // class0
+      {136, 140, 148, 160, 176, 192, 224, 234, 234, 240},   // bits
+    },
+    { // Horizontal component
+      128,                                                  // sign
+      {216, 128, 176, 160, 176, 176, 192, 198, 198, 208},   // class
+      {208},                                                // class0
+      {136, 140, 148, 160, 176, 192, 224, 234, 234, 240},   // bits
+    }
+  },
+  {{128, 128, 64}, {96, 112, 64}},                      // class0_fp0
+  {64, 96, 64},                                         // fp0
+  {{128, 128, 64}, {96, 112, 64}},                      // class0_fp1
+  {64, 96, 64},                                         // fp1
+  {160, 128},                                           // class0_hp bit
+  {160, 128}                                            // hp
+
+};
+
+//Rearranged the coeff probs for better usage
+static const vp9_prob default_coef_probs_4x4[COEFF_PROB_SIZE][COEFF_PROB_NUM] = {
+    // Y plane - Intra
+    // Band 0
+    { 195,  29, 183 }, {  84,  49, 136 }, {   8,  42,  71 },
+    // Band 1
+    {  31, 107, 169 }, {  35,  99, 159 }, {  17,  82, 140 },
+    {   8,  66, 114 }, {   2,  44,  76 }, {   1,  19,  32 },
+    // Band 2
+    {  40, 132, 201 }, {  29, 114, 187 }, {  13,  91, 157 },
+    {   7,  75, 127 }, {   3,  58,  95 }, {   1,  28,  47 },
+    // Band 3
+    {  69, 142, 221 }, {  42, 122, 201 }, {  15,  91, 159 },
+    {   6,  67, 121 }, {   1,  42,  77 }, {   1,  17,  31 },
+    // Band 4
+    { 102, 148, 228 }, {  67, 117, 204 }, {  17,  82, 154 },
+    {   6,  59, 114 }, {   2,  39,  75 }, {   1,  15,  29 },
+    // Band 5
+    { 156,  57, 233 }, { 119,  57, 212 }, {  58,  48, 163 },
+    {  29,  40, 124 }, {  12,  30,  81 }, {   3,  12,  31 },
+
+    // Y plane - Inter
+    // Band 0
+    { 191, 107, 226 }, { 124, 117, 204 }, {  25,  99, 155 },
+    // Band 1
+    {  29, 148, 210 }, {  37, 126, 194 }, {   8,  93, 157 },
+    {   2,  68, 118 }, {   1,  39,  69 }, {   1,  17,  33 },
+    // Band 2
+    {  41, 151, 213 }, {  27, 123, 193 }, {   3,  82, 144 },
+    {   1,  58, 105 }, {   1,  32,  60 }, {   1,  13,  26 },
+    // Band 3
+    {  59, 159, 220 }, {  23, 126, 198 }, {   4,  88, 151 },
+    {   1,  66, 114 }, {   1,  38,  71 }, {   1,  18,  34 },
+    // Band 4
+    { 114, 136, 232 }, {  51, 114, 207 }, {  11,  83, 155 },
+    {   3,  56, 105 }, {   1,  33,  65 }, {   1,  17,  34 },
+    // Band 5
+    { 149,  65, 234 }, { 121,  57, 215 }, {  61,  49, 166 },
+    {  28,  36, 114 }, {  12,  25,  76 }, {   3,  16,  42 },
+
+    // UV plane - Intra
+    // Band 0
+    { 214,  49, 220 }, { 132,  63, 188 }, {  42,  65, 137 },
+    // Band 1
+    {  85, 137, 221 }, { 104, 131, 216 }, {  49, 111, 192 },
+    {  21,  87, 155 }, {   2,  49,  87 }, {   1,  16,  28 },
+    // Band 2
+    {  89, 163, 230 }, {  90, 137, 220 }, {  29, 100, 183 },
+    {  10,  70, 135 }, {   2,  42,  81 }, {   1,  17,  33 },
+    // Band 3
+    { 108, 167, 237 }, {  55, 133, 222 }, {  15,  97, 179 },
+    {   4,  72, 135 }, {   1,  45,  85 }, {   1,  19,  38 },
+    // Band 4
+    { 124, 146, 240 }, {  66, 124, 224 }, {  17,  88, 175 },
+    {   4,  58, 122 }, {   1,  36,  75 }, {   1,  18,  37 },
+    //  Band 5
+    { 141,  79, 241 }, { 126,  70, 227 }, {  66,  58, 182 },
+    {  30,  44, 136 }, {  12,  34,  96 }, {   2,  20,  47 },
+
+    // UV plane - Inter
+    // Band 0
+    { 229,  99, 249 }, { 143, 111, 235 }, {  46, 109, 192 },
+    // Band 1
+    {  82, 158, 236 }, {  94, 146, 224 }, {  25, 117, 191 },
+    {   9,  87, 149 }, {   3,  56,  99 }, {   1,  33,  57 },
+    // Band 2
+    {  83, 167, 237 }, {  68, 145, 222 }, {  10, 103, 177 },
+    {   2,  72, 131 }, {   1,  41,  79 }, {   1,  20,  39 },
+    // Band 3
+    {  99, 167, 239 }, {  47, 141, 224 }, {  10, 104, 178 },
+    {   2,  73, 133 }, {   1,  44,  85 }, {   1,  22,  47 },
+    // Band 4
+    { 127, 145, 243 }, {  71, 129, 228 }, {  17,  93, 177 },
+    {   3,  61, 124 }, {   1,  41,  84 }, {   1,  21,  52 },
+    // Band 5
+    { 157,  78, 244 }, { 140,  72, 231 }, {  69,  58, 184 },
+    {  31,  44, 137 }, {  14,  38, 105 }, {   8,  23,  61 }
+};
+
+static const vp9_prob default_coef_probs_8x8[COEFF_PROB_SIZE][COEFF_PROB_NUM] = {
+    // Y plane - Intra
+    // Band 0
+    { 125,  34, 187 }, {  52,  41, 133 }, {   6,  31,  56 },
+    // Band 1
+    {  37, 109, 153 }, {  51, 102, 147 }, {  23,  87, 128 },
+    {   8,  67, 101 }, {   1,  41,  63 }, {   1,  19,  29 },
+    // Band 2
+    {  31, 154, 185 }, {  17, 127, 175 }, {   6,  96, 145 },
+    {   2,  73, 114 }, {   1,  51,  82 }, {   1,  28,  45 },
+    // Band 3
+    {  23, 163, 200 }, {  10, 131, 185 }, {   2,  93, 148 },
+    {   1,  67, 111 }, {   1,  41,  69 }, {   1,  14,  24 },
+    // Band 4
+    {  29, 176, 217 }, {  12, 145, 201 }, {   3, 101, 156 },
+    {   1,  69, 111 }, {   1,  39,  63 }, {   1,  14,  23 },
+    // Band 5
+    {  57, 192, 233 }, {  25, 154, 215 }, {   6, 109, 167 },
+    {   3,  78, 118 }, {   1,  48,  69 }, {   1,  21,  29 },
+
+    // Y plane - Inter
+    // Band 0
+    { 202, 105, 245 }, { 108, 106, 216 }, {  18,  90, 144 },
+    // Band 1
+    {  33, 172, 219 }, {  64, 149, 206 }, {  14, 117, 177 },
+    {   5,  90, 141 }, {   2,  61,  95 }, {   1,  37,  57 },
+    // Band 2
+    {  33, 179, 220 }, {  11, 140, 198 }, {   1,  89, 148 },
+    {   1,  60, 104 }, {   1,  33,  57 }, {   1,  12,  21 },
+    // Band 3
+    {  30, 181, 221 }, {   8, 141, 198 }, {   1,  87, 145 },
+    {   1,  58, 100 }, {   1,  31,  55 }, {   1,  12,  20 },
+    // Band 4
+    {  32, 186, 224 }, {   7, 142, 198 }, {   1,  86, 143 },
+    {   1,  58, 100 }, {   1,  31,  55 }, {   1,  12,  22 },
+    // Band 5
+    {  57, 192, 227 }, {  20, 143, 204 }, {   3,  96, 154 },
+    {   1,  68, 112 }, {   1,  42,  69 }, {   1,  19,  32 },
+
+    // UV plane - Intra
+    // Band 0
+    { 212,  35, 215 }, { 113,  47, 169 }, {  29,  48, 105 },
+    // Band 1
+    {  74, 129, 203 }, { 106, 120, 203 }, {  49, 107, 178 },
+    {  19,  84, 144 }, {   4,  50,  84 }, {   1,  15,  25 },
+    // Band 2
+    {  71, 172, 217 }, {  44, 141, 209 }, {  15, 102, 173 },
+    {   6,  76, 133 }, {   2,  51,  89 }, {   1,  24,  42 },
+    // Band 3
+    {  64, 185, 231 }, {  31, 148, 216 }, {   8, 103, 175 },
+    {   3,  74, 131 }, {   1,  46,  81 }, {   1,  18,  30 },
+    // Band 4
+    {  65, 196, 235 }, {  25, 157, 221 }, {   5, 105, 174 },
+    {   1,  67, 120 }, {   1,  38,  69 }, {   1,  15,  30 },
+    // Band 5
+    {  65, 204, 238 }, {  30, 156, 224 }, {   7, 107, 177 },
+    {   2,  70, 124 }, {   1,  42,  73 }, {   1,  18,  34 },
+
+    // UV Plane - Inter
+    // Band 0
+    { 225,  86, 251 }, { 144, 104, 235 }, {  42,  99, 181 },
+    // Band 1
+    {  85, 175, 239 }, { 112, 165, 229 }, {  29, 136, 200 },
+    {  12, 103, 162 }, {   6,  77, 123 }, {   2,  53,  84 },
+    // Band 2
+    {  75, 183, 239 }, {  30, 155, 221 }, {   3, 106, 171 },
+    {   1,  74, 128 }, {   1,  44,  76 }, {   1,  17,  28 },
+    // Band 3
+    {  73, 185, 240 }, {  27, 159, 222 }, {   2, 107, 172 },
+    {   1,  75, 127 }, {   1,  42,  73 }, {   1,  17,  29 },
+    // Band 4
+    {  62, 190, 238 }, {  21, 159, 222 }, {   2, 107, 172 },
+    {   1,  72, 122 }, {   1,  40,  71 }, {   1,  18,  32 },
+    // Band 5
+    {  61, 199, 240 }, {  27, 161, 226 }, {   4, 113, 180 },
+    {   1,  76, 129 }, {   1,  46,  80 }, {   1,  23,  41 }
+};
+
+static const vp9_prob default_coef_probs_16x16[COEFF_PROB_SIZE][COEFF_PROB_NUM] = {
+    // Y plane - Intra
+    // Band 0
+    {   7,  27, 153 }, {   5,  30,  95 }, {   1,  16,  30 },
+    // Band 1
+    {  50,  75, 127 }, {  57,  75, 124 }, {  27,  67, 108 },
+    {  10,  54,  86 }, {   1,  33,  52 }, {   1,  12,  18 },
+    // Band 2
+    {  43, 125, 151 }, {  26, 108, 148 }, {   7,  83, 122 },
+    {   2,  59,  89 }, {   1,  38,  60 }, {   1,  17,  27 },
+    // Band 3
+    {  23, 144, 163 }, {  13, 112, 154 }, {   2,  75, 117 },
+    {   1,  50,  81 }, {   1,  31,  51 }, {   1,  14,  23 },
+    // Band 4
+    {  18, 162, 185 }, {   6, 123, 171 }, {   1,  78, 125 },
+    {   1,  51,  86 }, {   1,  31,  54 }, {   1,  14,  23 },
+    // Band 5
+    {  15, 199, 227 }, {   3, 150, 204 }, {   1,  91, 146 },
+    {   1,  55,  95 }, {   1,  30,  53 }, {   1,  11,  20 },
+
+    // Y plane - Inter
+    // Band 0
+    {  19,  55, 240 }, {  19,  59, 196 }, {   3,  52, 105 },
+    // Band 1
+    {  41, 166, 207 }, { 104, 153, 199 }, {  31, 123, 181 },
+    {  14, 101, 152 }, {   5,  72, 106 }, {   1,  36,  52 },
+    // Band 2
+    {  35, 176, 211 }, {  12, 131, 190 }, {   2,  88, 144 },
+    {   1,  60, 101 }, {   1,  36,  60 }, {   1,  16,  28 },
+    // Band 3
+    {  28, 183, 213 }, {   8, 134, 191 }, {   1,  86, 142 },
+    {   1,  56,  96 }, {   1,  30,  53 }, {   1,  12,  20 },
+    // Band 4
+    {  20, 190, 215 }, {   4, 135, 192 }, {   1,  84, 139 },
+    {   1,  53,  91 }, {   1,  28,  49 }, {   1,  11,  20 },
+    // Band 5
+    {  13, 196, 216 }, {   2, 137, 192 }, {   1,  86, 143 },
+    {   1,  57,  99 }, {   1,  32,  56 }, {   1,  13,  24 },
+
+    // UV plane - Intra
+    // Band 0
+    { 211,  29, 217 }, {  96,  47, 156 }, {  22,  43,  87 },
+    // Band 1
+    {  78, 120, 193 }, { 111, 116, 186 }, {  46, 102, 164 },
+    {  15,  80, 128 }, {   2,  49,  76 }, {   1,  18,  28 },
+    // Band 2
+    {  71, 161, 203 }, {  42, 132, 192 }, {  10,  98, 150 },
+    {   3,  69, 109 }, {   1,  44,  70 }, {   1,  18,  29 },
+    // Band 3
+    {  57, 186, 211 }, {  30, 140, 196 }, {   4,  93, 146 },
+    {   1,  62, 102 }, {   1,  38,  65 }, {   1,  16,  27 },
+    // Band 4
+    {  47, 199, 217 }, {  14, 145, 196 }, {   1,  88, 142 },
+    {   1,  57,  98 }, {   1,  36,  62 }, {   1,  15,  26 },
+    // Band 5
+    {  26, 219, 229 }, {   5, 155, 207 }, {   1,  94, 151 },
+    {   1,  60, 104 }, {   1,  36,  62 }, {   1,  16,  28 },
+
+    // UV plane - Inter
+    // Band 0
+    { 233,  29, 248 }, { 146,  47, 220 }, {  43,  52, 140 },
+    // Band 1
+    { 100, 163, 232 }, { 179, 161, 222 }, {  63, 142, 204 },
+    {  37, 113, 174 }, {  26,  89, 137 }, {  18,  68,  97 },
+    // Band 2
+    {  85, 181, 230 }, {  32, 146, 209 }, {   7, 100, 164 },
+    {   3,  71, 121 }, {   1,  45,  77 }, {   1,  18,  30 },
+    // Band 3
+    {  65, 187, 230 }, {  20, 148, 207 }, {   2,  97, 159 },
+    {   1,  68, 116 }, {   1,  40,  70 }, {   1,  14,  29 },
+    // Band 4
+    {  40, 194, 227 }, {   8, 147, 204 }, {   1,  94, 155 },
+    {   1,  65, 112 }, {   1,  39,  66 }, {   1,  14,  26 },
+    // Band 5
+    {  16, 208, 228 }, {   3, 151, 207 }, {   1,  98, 160 },
+    {   1,  67, 117 }, {   1,  41,  74 }, {   1,  17,  31 }
+};
+
+static const vp9_prob default_coef_probs_32x32[COEFF_PROB_SIZE][COEFF_PROB_NUM] = {
+    // Y plane - Intra
+    // Band 0
+    {  17,  38, 140 }, {   7,  34,  80 }, {   1,  17,  29 },
+    // Band 1
+    {  37,  75, 128 }, {  41,  76, 128 }, {  26,  66, 116 },
+    {  12,  52,  94 }, {   2,  32,  55 }, {   1,  10,  16 },
+    // Band 2
+    {  50, 127, 154 }, {  37, 109, 152 }, {  16,  82, 121 },
+    {   5,  59,  85 }, {   1,  35,  54 }, {   1,  13,  20 },
+    //Band 3
+    {  40, 142, 167 }, {  17, 110, 157 }, {   2,  71, 112 },
+    {   1,  44,  72 }, {   1,  27,  45 }, {   1,  11,  17 },
+    // Band 4
+    {  30, 175, 188 }, {   9, 124, 169 }, {   1,  74, 116 },
+    {   1,  48,  78 }, {   1,  30,  49 }, {   1,  11,  18 },
+    // Band 5
+    {  10, 222, 223 }, {   2, 150, 194 }, {   1,  83, 128 },
+    {   1,  48,  79 }, {   1,  27,  45 }, {   1,  11,  17 },
+
+    // Y plane - Inter
+    // Band 0
+    {  36,  41, 235 }, {  29,  36, 193 }, {  10,  27, 111 },
+    // Band 1
+    {  85, 165, 222 }, { 177, 162, 215 }, { 110, 135, 195 },
+    {  57, 113, 168 }, {  23,  83, 120 }, {  10,  49,  61 },
+    // Band 2
+    {  85, 190, 223 }, {  36, 139, 200 }, {   5,  90, 146 },
+    {   1,  60, 103 }, {   1,  38,  65 }, {   1,  18,  30 },
+    // Band 3
+    {  72, 202, 223 }, {  23, 141, 199 }, {   2,  86, 140 },
+    {   1,  56,  97 }, {   1,  36,  61 }, {   1,  16,  27 },
+    // Band 4
+    {  55, 218, 225 }, {  13, 145, 200 }, {   1,  86, 141 },
+    {   1,  57,  99 }, {   1,  35,  61 }, {   1,  13,  22 },
+    // Band 5
+    {  15, 235, 212 }, {   1, 132, 184 }, {   1,  84, 139 },
+    {   1,  57,  97 }, {   1,  34,  56 }, {   1,  14,  23 },
+
+    // UV plane - Intra
+    // Band 0
+    { 181,  21, 201 }, {  61,  37, 123 }, {  10,  38,  71 },
+    // Band 1
+    {  47, 106, 172 }, {  95, 104, 173 }, {  42,  93, 159 },
+    {  18,  77, 131 }, {   4,  50,  81 }, {   1,  17,  23 },
+    // Band 2
+    {  62, 147, 199 }, {  44, 130, 189 }, {  28, 102, 154 },
+    {  18,  75, 115 }, {   2,  44,  65 }, {   1,  12,  19 },
+    // Band 3
+    {  55, 153, 210 }, {  24, 130, 194 }, {   3,  93, 146 },
+    {   1,  61,  97 }, {   1,  31,  50 }, {   1,  10,  16 },
+    // Band 4
+    {  49, 186, 223 }, {  17, 148, 204 }, {   1,  96, 142 },
+    {   1,  53,  83 }, {   1,  26,  44 }, {   1,  11,  17 },
+    // Band 5
+    {  13, 217, 212 }, {   2, 136, 180 }, {   1,  78, 124 },
+    {   1,  50,  83 }, {   1,  29,  49 }, {   1,  14,  23 },
+
+    // UV plane - Inter
+    // Band 0
+    { 197,  13, 247 }, {  82,  17, 222 }, {  25,  17, 162 },
+    // Band 1
+    { 126, 186, 247 }, { 234, 191, 243 }, { 176, 177, 234 },
+    { 104, 158, 220 }, {  66, 128, 186 }, {  55,  90, 137 },
+    // Band 2
+    { 111, 197, 242 }, {  46, 158, 219 }, {   9, 104, 171 },
+    {   2,  65, 125 }, {   1,  44,  80 }, {   1,  17,  91 },
+    // Band 3
+    { 104, 208, 245 }, {  39, 168, 224 }, {   3, 109, 162 },
+    {   1,  79, 124 }, {   1,  50, 102 }, {   1,  43, 102 },
+    // Band 4
+    {  84, 220, 246 }, {  31, 177, 231 }, {   2, 115, 180 },
+    {   1,  79, 134 }, {   1,  55,  77 }, {   1,  60,  79 },
+    // Band 5
+    {  43, 243, 240 }, {   8, 180, 217 }, {   1, 115, 166 },
+    {   1,  84, 121 }, {   1,  51,  67 }, {   1,  16,   6 }
+
+};
+
+#endif /*VP9_PROBS_H */
-- 
cgit v1.2.3


From f36ab3413f814c80f4df4f4570f4ef9a1168b624 Mon Sep 17 00:00:00 2001
From: Pengfei Qu <Pengfei.Qu@intel.com>
Date: Thu, 22 Oct 2015 04:39:07 -0400
Subject: VP9 HWDec:add vp9 surface structure and related parameter

Signed-off-by: Pengfei Qu <Pengfei.Qu@intel.com>
Signed-off-by: Sirisha Muppavarapu <sirisha.muppavarapu@intel.com>
Signed-off-by: peng.chen <peng.c.chen@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
---
 src/i965_defines.h       |  9 +++++++++
 src/intel_media.h        | 11 +++++++++++
 src/intel_media_common.c | 24 ++++++++++++++++++++++++
 3 files changed, 44 insertions(+)

diff --git a/src/i965_defines.h b/src/i965_defines.h
index 65c0b11..9ea8a9f 100755
--- a/src/i965_defines.h
+++ b/src/i965_defines.h
@@ -437,6 +437,9 @@
 #define HCP_PAK_OBJECT                          HCP(0x21)
 #define HCP_INSERT_PAK_OBJECT                   HCP(0x22)
 
+#define HCP_VP9_SEGMENT_STATE                   HCP(0x32)
+#define HCP_VP9_PIC_STATE                       HCP(0x30)
+
 #define I965_DEPTHFORMAT_D32_FLOAT              1
 
 #define BASE_ADDRESS_MODIFY             (1 << 0)
@@ -906,6 +909,12 @@
 
 #define HCP_CODEC_HEVC                          0
 
+#define HCP_CODEC_VP9                           1
+#define HCP_VP9_KEY_FRAME                       0
+#define HCP_VP9_INTER_FRAME                     1
+#define HCP_VP9_PROFILE0                        0     /* 8 bit 420 only */
+#define HCP_VP9_PROFILE2                        2     /* 10 bits 420 only */
+
 #define HCP_CODEC_SELECT_DECODE                 0
 #define HCP_CODEC_SELECT_ENCODE                 1
 
diff --git a/src/intel_media.h b/src/intel_media.h
index 73a03c7..77afb5a 100644
--- a/src/intel_media.h
+++ b/src/intel_media.h
@@ -59,6 +59,17 @@ struct gen_hevc_surface
     dri_bo *motion_vector_temporal_bo;
 };
 
+typedef struct gen_vp9_surface GenVP9Surface;
+struct gen_vp9_surface
+{
+    GenCodecSurface base;
+    uint16_t frame_width;
+    uint16_t frame_height;
+    dri_bo *motion_vector_temporal_bo;
+};
+
 extern void gen_free_hevc_surface(void **data);
 
+extern void gen_free_vp9_surface(void **data);
+
 #endif /* INTEL_MEDIA_H */
diff --git a/src/intel_media_common.c b/src/intel_media_common.c
index f0e1cae..5fe9fc5 100644
--- a/src/intel_media_common.c
+++ b/src/intel_media_common.c
@@ -107,3 +107,27 @@ gen_free_hevc_surface(void **data)
 
     pthread_mutex_unlock(&free_hevc_surface_lock);
 }
+
+static pthread_mutex_t free_vp9_surface_lock = PTHREAD_MUTEX_INITIALIZER;
+
+void gen_free_vp9_surface(void **data)
+{
+    GenVP9Surface *vp9_surface;
+
+    pthread_mutex_lock(&free_vp9_surface_lock);
+
+    vp9_surface = *data;
+
+    if (!vp9_surface) {
+        pthread_mutex_unlock(&free_vp9_surface_lock);
+        return;
+    }
+
+    dri_bo_unreference(vp9_surface->motion_vector_temporal_bo);
+    vp9_surface->motion_vector_temporal_bo = NULL;
+
+    free(vp9_surface);
+    *data = NULL;
+
+    pthread_mutex_unlock(&free_vp9_surface_lock);
+}
-- 
cgit v1.2.3


From 833fa7715d28b89af4bd661e3f2cac72345c9a27 Mon Sep 17 00:00:00 2001
From: Pengfei Qu <Pengfei.Qu@intel.com>
Date: Thu, 22 Oct 2015 04:40:51 -0400
Subject: VP9 HWDec:add vp9 parameter check function before decoding

Signed-off-by: Pengfei Qu <Pengfei.Qu@intel.com>
Signed-off-by: Sirisha Muppavarapu <sirisha.muppavarapu@intel.com>
Signed-off-by: peng.chen <peng.c.chen@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
---
 src/i965_decoder_utils.c | 149 +++++++++++++++++++++++++++++++++++++++++++++++
 src/i965_decoder_utils.h |  13 +++++
 2 files changed, 162 insertions(+)

diff --git a/src/i965_decoder_utils.c b/src/i965_decoder_utils.c
index 53a5aa1..835d3fd 100644
--- a/src/i965_decoder_utils.c
+++ b/src/i965_decoder_utils.c
@@ -880,6 +880,66 @@ intel_update_vp8_frame_store_index(VADriverContextP ctx,
 
 }
 
+//Obtain the reference frames from the decode state and store them in frame store.
+void
+intel_update_vp9_frame_store_index(VADriverContextP ctx,
+                                   struct decode_state *decode_state,
+                                   VADecPictureParameterBufferVP9 *pic_param,
+                                   GenFrameStore frame_store[MAX_GEN_REFERENCE_FRAMES])
+{
+    struct object_surface *obj_surface;
+    int i=0, index=0;
+
+    //Check for the validity of the last reference frame
+    obj_surface = decode_state->reference_objects[0];
+
+    index = pic_param->pic_fields.bits.last_ref_frame;
+    if (pic_param->reference_frames[index] == VA_INVALID_ID ||
+        !obj_surface ||
+        !obj_surface->bo) {
+        frame_store[0].surface_id = VA_INVALID_ID;
+        frame_store[0].obj_surface = NULL;
+    } else {
+        frame_store[0].surface_id = pic_param->reference_frames[index];
+        frame_store[0].obj_surface = obj_surface;
+    }
+
+    //Check for the validity of the golden reference frame
+    obj_surface = decode_state->reference_objects[1];
+
+    index = pic_param->pic_fields.bits.golden_ref_frame;
+    if (pic_param->reference_frames[index] == VA_INVALID_ID ||
+        !obj_surface ||
+        !obj_surface->bo) {
+        frame_store[1].surface_id = frame_store[0].surface_id;
+        frame_store[1].obj_surface = frame_store[0].obj_surface;
+    } else {
+        frame_store[1].surface_id = pic_param->reference_frames[index];
+        frame_store[1].obj_surface = obj_surface;
+    }
+
+    //Check for the validity of the altref reference frame
+    obj_surface = decode_state->reference_objects[2];
+
+    index = pic_param->pic_fields.bits.alt_ref_frame;
+    if (pic_param->reference_frames[index] == VA_INVALID_ID ||
+        !obj_surface ||
+        !obj_surface->bo) {
+        frame_store[2].surface_id = frame_store[0].surface_id;
+        frame_store[2].obj_surface = frame_store[0].obj_surface;
+    } else {
+        frame_store[2].surface_id = pic_param->reference_frames[index];
+        frame_store[2].obj_surface = obj_surface;
+    }
+
+    //Set the remaining framestores to either last/golden/altref
+    for (i = 3; i < MAX_GEN_REFERENCE_FRAMES; i++) {
+        frame_store[i].surface_id = frame_store[i % 2].surface_id;
+        frame_store[i].obj_surface = frame_store[i % 2].obj_surface;
+    }
+
+}
+
 static VAStatus
 intel_decoder_check_avc_parameter(VADriverContextP ctx,
                                   VAProfile h264_profile,
@@ -1155,6 +1215,33 @@ hevc_ensure_surface_bo(
     return va_status;
 }
 
+//Ensure there is a tiled render surface in NV12 format. If not, create one.
+VAStatus
+vp9_ensure_surface_bo(
+    VADriverContextP                    ctx,
+    struct decode_state                *decode_state,
+    struct object_surface              *obj_surface,
+    const VADecPictureParameterBufferVP9 *pic_param
+)
+{
+    VAStatus va_status = VA_STATUS_SUCCESS;
+
+    /* (Re-)allocate the underlying surface buffer store, if necessary */
+    if (!obj_surface->bo || obj_surface->fourcc != VA_FOURCC_NV12) {
+        struct i965_driver_data * const i965 = i965_driver_data(ctx);
+
+        i965_destroy_surface_storage(obj_surface);
+
+        va_status = i965_check_alloc_surface_bo(ctx,
+                                                obj_surface,
+                                                i965->codec_info->has_tiled_surface,
+                                                VA_FOURCC_NV12,
+                                                SUBSAMPLE_YUV420);
+    }
+
+    return va_status;
+}
+
 static VAStatus
 intel_decoder_check_hevc_parameter(VADriverContextP ctx,
                                    struct decode_state *decode_state)
@@ -1222,6 +1309,64 @@ error:
     return va_status;
 }
 
+//Obtains reference frames from the picture parameter and
+//then sets the reference frames in the decode_state
+static VAStatus
+intel_decoder_check_vp9_parameter(VADriverContextP ctx,
+                                   struct decode_state *decode_state)
+{
+    struct i965_driver_data *i965 = i965_driver_data(ctx);
+    VADecPictureParameterBufferVP9 *pic_param = (VADecPictureParameterBufferVP9 *)decode_state->pic_param->buffer;
+    VAStatus va_status = VA_STATUS_ERROR_INVALID_PARAMETER;
+    struct object_surface *obj_surface;
+    int i=0, index=0;
+
+    //Max support upto 4k for BXT
+    if ((pic_param->frame_width-1 < 7) || (pic_param->frame_width-1 > 4095))
+        return va_status;
+
+    if ((pic_param->frame_height-1 < 7) || (pic_param->frame_height-1 > 4095))
+        return va_status;
+
+    //Set the reference object in decode state for last reference
+    index = pic_param->pic_fields.bits.last_ref_frame;
+    if (pic_param->reference_frames[index] != VA_INVALID_SURFACE) {
+        obj_surface = SURFACE(pic_param->reference_frames[index]);
+
+        if (obj_surface && obj_surface->bo)
+            decode_state->reference_objects[i++] = obj_surface;
+        else
+            decode_state->reference_objects[i++] = NULL;
+    }
+
+    //Set the reference object in decode state for golden reference
+    index = pic_param->pic_fields.bits.golden_ref_frame;
+    if (pic_param->reference_frames[index] != VA_INVALID_SURFACE) {
+        obj_surface = SURFACE(pic_param->reference_frames[index]);
+
+        if (obj_surface && obj_surface->bo)
+            decode_state->reference_objects[i++] = obj_surface;
+        else
+            decode_state->reference_objects[i++] = NULL;
+    }
+
+    //Set the reference object in decode state for altref reference
+    index = pic_param->pic_fields.bits.alt_ref_frame;
+    if (pic_param->reference_frames[index] != VA_INVALID_SURFACE) {
+        obj_surface = SURFACE(pic_param->reference_frames[index]);
+
+        if (obj_surface && obj_surface->bo)
+            decode_state->reference_objects[i++] = obj_surface;
+        else
+            decode_state->reference_objects[i++] = NULL;
+    }
+
+    for ( ; i < 16; i++)
+        decode_state->reference_objects[i] = NULL;
+
+    return VA_STATUS_SUCCESS;
+}
+
 VAStatus
 intel_decoder_sanity_check_input(VADriverContextP ctx,
                                  VAProfile profile,
@@ -1274,6 +1419,10 @@ intel_decoder_sanity_check_input(VADriverContextP ctx,
         vaStatus = intel_decoder_check_hevc_parameter(ctx, decode_state);
         break;
 
+    case VAProfileVP9Profile0:
+        vaStatus = intel_decoder_check_vp9_parameter(ctx, decode_state);
+        break;
+
     default:
         vaStatus = VA_STATUS_ERROR_INVALID_PARAMETER;
         break;
diff --git a/src/i965_decoder_utils.h b/src/i965_decoder_utils.h
index 3618034..5889158 100644
--- a/src/i965_decoder_utils.h
+++ b/src/i965_decoder_utils.h
@@ -159,6 +159,12 @@ intel_update_vp8_frame_store_index(VADriverContextP ctx,
                                    VAPictureParameterBufferVP8 *pic_param,
                                    GenFrameStore frame_store[MAX_GEN_REFERENCE_FRAMES]);
 
+void
+intel_update_vp9_frame_store_index(VADriverContextP ctx,
+                                   struct decode_state *decode_state,
+                                   VADecPictureParameterBufferVP9 *pic_param,
+                                   GenFrameStore frame_store[MAX_GEN_REFERENCE_FRAMES]);
+
 bool
 intel_ensure_vp8_segmentation_buffer(VADriverContextP ctx, GenBuffer *buf,
     unsigned int mb_width, unsigned int mb_height);
@@ -174,4 +180,11 @@ hevc_ensure_surface_bo(
     const VAPictureParameterBufferHEVC *pic_param
 );
 
+VAStatus
+vp9_ensure_surface_bo(
+    VADriverContextP                    ctx,
+    struct decode_state                *decode_state,
+    struct object_surface              *obj_surface,
+    const VADecPictureParameterBufferVP9 *pic_param
+);
 #endif /* I965_DECODER_UTILS_H */
-- 
cgit v1.2.3


From 8f1e1015a4cc8c08dd685f80829ca1555ae1cab1 Mon Sep 17 00:00:00 2001
From: Pengfei Qu <Pengfei.Qu@intel.com>
Date: Thu, 22 Oct 2015 04:51:38 -0400
Subject: VP9 HWDec: add VP9 HW decoding pipeline

v2: fix sengment feature in inter frame

v3: update the prob buffer logic

v4: fix intra-only feature issue

Signed-off-by: Pengfei Qu <Pengfei.Qu@intel.com>
Signed-off-by: Sirisha Muppavarapu <sirisha.muppavarapu@intel.com>
Signed-off-by: peng.chen <peng.c.chen@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
---
 src/gen9_mfd.c | 944 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
 src/gen9_mfd.h |  26 ++
 2 files changed, 968 insertions(+), 2 deletions(-)

diff --git a/src/gen9_mfd.c b/src/gen9_mfd.c
index dab4213..d9ca3be 100644
--- a/src/gen9_mfd.c
+++ b/src/gen9_mfd.c
@@ -39,6 +39,7 @@
 
 #include "gen9_mfd.h"
 #include "intel_media.h"
+#include "vp9_probs.h"
 
 #define OUT_BUFFER(buf_bo, is_target, ma)  do {                         \
         if (buf_bo) {                                                   \
@@ -190,7 +191,7 @@ gen9_hcpd_pipe_mode_select(VADriverContextP ctx,
 {
     struct intel_batchbuffer *batch = gen9_hcpd_context->base.batch;
 
-    assert(codec == HCP_CODEC_HEVC);
+    assert((codec == HCP_CODEC_HEVC) || (codec == HCP_CODEC_VP9));
 
     BEGIN_BCS_BATCH(batch, 4);
 
@@ -955,6 +956,915 @@ out:
     return vaStatus;
 }
 
+/*********************************************************/
+/*                  VP9 Code                             */
+/*********************************************************/
+
+
+#define VP9_PROB_BUFFER_FIRST_PART_SIZE 2010
+#define VP9_PROB_BUFFER_SECOND_PART_SIZE 10
+#define VP9_PROB_BUFFER_KEY_INTER_OFFSET 1667
+#define VP9_PROB_BUFFER_KEY_INTER_SIZE   343
+
+#define VP9_PROB_BUFFER_UPDATE_NO   0
+#define VP9_PROB_BUFFER_UPDATE_SECNE_1    1
+#define VP9_PROB_BUFFER_UPDATE_SECNE_2    2
+#define VP9_PROB_BUFFER_UPDATE_SECNE_3    3
+#define VP9_PROB_BUFFER_UPDATE_SECNE_4    4
+#define VP9_PROB_BUFFER_UPDATE_SECNE_5    5
+
+#define VP9_PROB_BUFFER_SAVED_NO   0
+#define VP9_PROB_BUFFER_SAVED_SECNE_1    1
+#define VP9_PROB_BUFFER_SAVED_SECNE_2    2
+
+#define VP9_PROB_BUFFER_RESTORED_NO   0
+#define VP9_PROB_BUFFER_RESTORED_SECNE_1    1
+#define VP9_PROB_BUFFER_RESTORED_SECNE_2    2
+#define VP9_PROB_BUFFER_RESTORED_SECNE_MAX    (VP9_PROB_BUFFER_RESTORED_SECNE_2 + 1)
+
+static void vp9_update_segmentId_buffer(VADriverContextP ctx,
+                          struct decode_state *decode_state,
+                          struct gen9_hcpd_context *gen9_hcpd_context, uint8_t isScaling)
+{
+    VADecPictureParameterBufferVP9 *pic_param;
+
+    assert(decode_state->pic_param && decode_state->pic_param->buffer);
+    pic_param = (VADecPictureParameterBufferVP9 *)decode_state->pic_param->buffer;
+
+    int size = 0;
+
+    if((pic_param->pic_fields.bits.frame_type == HCP_VP9_KEY_FRAME) ||
+        pic_param->pic_fields.bits.error_resilient_mode ||
+        pic_param->pic_fields.bits.intra_only || isScaling) {
+
+        size = (gen9_hcpd_context->picture_width_in_min_cb_minus1+2)*(gen9_hcpd_context->picture_height_in_min_cb_minus1 + 2) * 1;
+        size<<=6;
+        //VP9 Segment ID buffer needs to be zero
+        dri_bo_map(gen9_hcpd_context->vp9_segment_id_buffer.bo,1);
+        memset((unsigned char *)gen9_hcpd_context->vp9_segment_id_buffer.bo->virtual,0, size);
+        dri_bo_unmap(gen9_hcpd_context->vp9_segment_id_buffer.bo);
+    }
+}
+
+static void
+vp9_gen_default_probabilities(VADriverContextP ctx, struct gen9_hcpd_context *gen9_hcpd_context)
+{
+    int i = 0;
+    uint32_t size = 0;
+
+    size = sizeof(FRAME_CONTEXT);
+    memset(&gen9_hcpd_context->vp9_fc_key_default,0,size);
+    memset(&gen9_hcpd_context->vp9_fc_inter_default,0,size);
+    memset(&gen9_hcpd_context->vp9_frame_ctx,0,size*FRAME_CONTEXTS);
+    //more code to come here below
+
+    //1. key default
+    gen9_hcpd_context->vp9_fc_key_default.tx_probs = default_tx_probs;
+    //dummy 52
+    vp9_copy(gen9_hcpd_context->vp9_fc_key_default.coeff_probs4x4, default_coef_probs_4x4);
+    vp9_copy(gen9_hcpd_context->vp9_fc_key_default.coeff_probs8x8, default_coef_probs_8x8);
+    vp9_copy(gen9_hcpd_context->vp9_fc_key_default.coeff_probs16x16, default_coef_probs_16x16);
+    vp9_copy(gen9_hcpd_context->vp9_fc_key_default.coeff_probs32x32, default_coef_probs_32x32);
+    //dummy 16
+    vp9_copy(gen9_hcpd_context->vp9_fc_key_default.skip_probs, default_skip_probs);
+    vp9_copy(gen9_hcpd_context->vp9_fc_key_default.partition_prob, vp9_kf_partition_probs);
+    //dummy 47
+    vp9_copy(gen9_hcpd_context->vp9_fc_key_default.uv_mode_prob, vp9_kf_uv_mode_prob);
+    vp9_copy(gen9_hcpd_context->vp9_fc_key_default.seg_tree_probs, default_seg_tree_probs);
+    vp9_copy(gen9_hcpd_context->vp9_fc_key_default.seg_pred_probs, default_seg_pred_probs);
+
+    //2. inter default
+    gen9_hcpd_context->vp9_fc_inter_default.tx_probs = default_tx_probs;
+    //dummy 52
+    vp9_copy(gen9_hcpd_context->vp9_fc_inter_default.coeff_probs4x4, default_coef_probs_4x4);
+    vp9_copy(gen9_hcpd_context->vp9_fc_inter_default.coeff_probs8x8, default_coef_probs_8x8);
+    vp9_copy(gen9_hcpd_context->vp9_fc_inter_default.coeff_probs16x16, default_coef_probs_16x16);
+    vp9_copy(gen9_hcpd_context->vp9_fc_inter_default.coeff_probs32x32, default_coef_probs_32x32);
+    //dummy 16
+    vp9_copy(gen9_hcpd_context->vp9_fc_inter_default.skip_probs, default_skip_probs);
+    vp9_copy(gen9_hcpd_context->vp9_fc_inter_default.inter_mode_probs, default_inter_mode_probs);
+    vp9_copy(gen9_hcpd_context->vp9_fc_inter_default.switchable_interp_prob, default_switchable_interp_prob);
+    vp9_copy(gen9_hcpd_context->vp9_fc_inter_default.intra_inter_prob, default_intra_inter_p);
+    vp9_copy(gen9_hcpd_context->vp9_fc_inter_default.comp_inter_prob, default_comp_inter_p);
+    vp9_copy(gen9_hcpd_context->vp9_fc_inter_default.single_ref_prob, default_single_ref_p);
+    vp9_copy(gen9_hcpd_context->vp9_fc_inter_default.comp_ref_prob, default_comp_ref_p);
+    vp9_copy(gen9_hcpd_context->vp9_fc_inter_default.y_mode_prob, default_if_y_probs);
+    vp9_copy(gen9_hcpd_context->vp9_fc_inter_default.partition_prob, default_partition_probs);
+    gen9_hcpd_context->vp9_fc_inter_default.nmvc = default_nmv_context;
+    //dummy 47
+    vp9_copy(gen9_hcpd_context->vp9_fc_inter_default.uv_mode_prob, default_if_uv_probs);
+    vp9_copy(gen9_hcpd_context->vp9_fc_inter_default.seg_tree_probs, default_seg_tree_probs);
+    vp9_copy(gen9_hcpd_context->vp9_fc_inter_default.seg_pred_probs, default_seg_pred_probs);
+
+    for(i = 0; i < FRAME_CONTEXTS; i++)
+    {
+        gen9_hcpd_context->vp9_frame_ctx[i] = gen9_hcpd_context->vp9_fc_inter_default;
+    }
+    gen9_hcpd_context->vp9_fc = gen9_hcpd_context->vp9_fc_inter_default;
+
+}
+
+static void
+vp9_update_probabilities(VADriverContextP ctx,
+                          struct decode_state *decode_state,
+                          struct gen9_hcpd_context *gen9_hcpd_context)
+{
+    VADecPictureParameterBufferVP9 *pic_param;
+    int i = 0;
+    uint8_t is_saved = VP9_PROB_BUFFER_SAVED_NO;
+    uint8_t is_restored = VP9_PROB_BUFFER_RESTORED_NO;
+
+    uint8_t last_frame_type = gen9_hcpd_context->last_frame.frame_type;
+    uint8_t temp_frame_ctx_id;
+
+    assert(decode_state->pic_param && decode_state->pic_param->buffer);
+    pic_param = (VADecPictureParameterBufferVP9 *)decode_state->pic_param->buffer;
+    temp_frame_ctx_id = pic_param->pic_fields.bits.frame_context_idx;
+
+    if(pic_param->pic_fields.bits.frame_type == HCP_VP9_KEY_FRAME)
+    {
+        gen9_hcpd_context->vp9_fc = gen9_hcpd_context->vp9_fc_key_default;
+        gen9_hcpd_context->last_frame.prob_buffer_saved_flag = VP9_PROB_BUFFER_SAVED_NO;
+        gen9_hcpd_context->last_frame.prob_buffer_restored_flag = VP9_PROB_BUFFER_RESTORED_NO;
+
+    }else
+    {
+        gen9_hcpd_context->vp9_fc = gen9_hcpd_context->vp9_fc_inter_default;
+    }
+
+    // restore?
+    if(gen9_hcpd_context->last_frame.prob_buffer_saved_flag == VP9_PROB_BUFFER_SAVED_SECNE_1)
+    {
+        if((pic_param->pic_fields.bits.frame_type == HCP_VP9_INTER_FRAME))
+        {
+            //save the inter frame values for the 343 bytes
+            //Update the 343 bytes of the buffer with Intra values
+            is_restored = VP9_PROB_BUFFER_RESTORED_SECNE_1;
+        }
+    }else if(gen9_hcpd_context->last_frame.prob_buffer_saved_flag == VP9_PROB_BUFFER_SAVED_SECNE_2)
+    {
+        if((pic_param->pic_fields.bits.frame_type == HCP_VP9_KEY_FRAME) ||pic_param->pic_fields.bits.intra_only|pic_param->pic_fields.bits.error_resilient_mode)
+        {
+            temp_frame_ctx_id = 0;
+        }
+
+        if((pic_param->pic_fields.bits.frame_type == HCP_VP9_INTER_FRAME) &&
+            (temp_frame_ctx_id == 0))
+        {
+
+            is_restored = VP9_PROB_BUFFER_RESTORED_SECNE_2;
+        }
+    }
+
+    if(is_restored > VP9_PROB_BUFFER_RESTORED_NO && is_restored < VP9_PROB_BUFFER_RESTORED_SECNE_MAX)
+    {
+        memcpy(gen9_hcpd_context->vp9_frame_ctx[gen9_hcpd_context->last_frame.frame_context_idx].inter_mode_probs,gen9_hcpd_context->vp9_saved_fc.inter_mode_probs,VP9_PROB_BUFFER_KEY_INTER_SIZE);
+    }
+
+    if((gen9_hcpd_context->last_frame.prob_buffer_restored_flag == VP9_PROB_BUFFER_RESTORED_SECNE_MAX) ||
+        (gen9_hcpd_context->last_frame.refresh_frame_context && last_frame_type == HCP_VP9_KEY_FRAME && (pic_param->pic_fields.bits.frame_type == HCP_VP9_INTER_FRAME)))
+    {
+        if(pic_param->pic_fields.bits.frame_type == HCP_VP9_INTER_FRAME)
+        {
+            memcpy(gen9_hcpd_context->vp9_frame_ctx[gen9_hcpd_context->last_frame.frame_context_idx].inter_mode_probs,gen9_hcpd_context->vp9_fc_inter_default.inter_mode_probs,VP9_PROB_BUFFER_KEY_INTER_SIZE);
+        }
+    }
+    //first part buffer update: Case 1)Reset all 4 probablity buffers
+   if((pic_param->pic_fields.bits.frame_type == HCP_VP9_KEY_FRAME) ||pic_param->pic_fields.bits.intra_only|pic_param->pic_fields.bits.error_resilient_mode)
+    {
+        if((pic_param->pic_fields.bits.frame_type == HCP_VP9_KEY_FRAME) ||
+            (pic_param->pic_fields.bits.reset_frame_context == 3)||
+            pic_param->pic_fields.bits.error_resilient_mode)
+        {
+            //perform full buffer update
+            for(i = 0; i < FRAME_CONTEXTS; i++)
+            {
+                memcpy(&gen9_hcpd_context->vp9_frame_ctx[i],&gen9_hcpd_context->vp9_fc_inter_default,VP9_PROB_BUFFER_FIRST_PART_SIZE);
+            }
+        }else if(pic_param->pic_fields.bits.reset_frame_context == 2&&pic_param->pic_fields.bits.intra_only)
+        {
+            memcpy(&gen9_hcpd_context->vp9_frame_ctx[pic_param->pic_fields.bits.frame_context_idx],&gen9_hcpd_context->vp9_fc_inter_default,VP9_PROB_BUFFER_FIRST_PART_SIZE);
+        }
+        pic_param->pic_fields.bits.frame_context_idx = 0;
+    }
+
+    //Full buffer update: Case 2.2)Reset only segmentation prob buffer
+    if(pic_param->pic_fields.bits.segmentation_enabled &&
+        pic_param->pic_fields.bits.segmentation_update_map)
+    {
+        for(i = 0; i < FRAME_CONTEXTS; i++)
+        {
+            //Reset only the segementation probability buffers
+            vp9_copy(gen9_hcpd_context->vp9_frame_ctx[i].seg_tree_probs, default_seg_tree_probs);
+            vp9_copy(gen9_hcpd_context->vp9_frame_ctx[i].seg_pred_probs, default_seg_pred_probs);
+        }
+    }
+
+    //update vp9_fc according to frame_context_id
+    {
+        gen9_hcpd_context->vp9_fc = gen9_hcpd_context->vp9_frame_ctx[pic_param->pic_fields.bits.frame_context_idx];
+    }
+    //Partial Buffer Update
+    //Case 1) Update top 3 probabilities only
+    if(pic_param->pic_fields.bits.frame_type == HCP_VP9_KEY_FRAME)
+    {
+        memcpy(gen9_hcpd_context->vp9_fc.inter_mode_probs,gen9_hcpd_context->vp9_fc_key_default.inter_mode_probs,VP9_PROB_BUFFER_KEY_INTER_SIZE);
+        if((!pic_param->pic_fields.bits.segmentation_enabled ||
+            !pic_param->pic_fields.bits.segmentation_update_map)) {
+            //Update with key frame default probability values for only
+            //tx_probs, coef_probs, and the next 343 bytes
+            memcpy(&gen9_hcpd_context->vp9_fc,&gen9_hcpd_context->vp9_fc_key_default,VP9_PROB_BUFFER_FIRST_PART_SIZE);
+        }
+    }
+    //Case 2) Update 343 bytes for first inter following key frame
+    if( last_frame_type == HCP_VP9_KEY_FRAME &&
+        (pic_param->pic_fields.bits.frame_type == HCP_VP9_INTER_FRAME)) {
+        //Update with inter frame default values for the 343 bytes
+        memcpy(gen9_hcpd_context->vp9_fc.inter_mode_probs,gen9_hcpd_context->vp9_fc_inter_default.inter_mode_probs,VP9_PROB_BUFFER_KEY_INTER_SIZE);
+    }
+    //Case 2.1) Update 343 bytes for first intra-inly frame following key frame
+    if( last_frame_type == HCP_VP9_KEY_FRAME &&
+        pic_param->pic_fields.bits.intra_only) {
+        //Update with inter frame default values for the 343 bytes
+        memcpy(gen9_hcpd_context->vp9_fc.inter_mode_probs,gen9_hcpd_context->vp9_fc_key_default.inter_mode_probs,VP9_PROB_BUFFER_KEY_INTER_SIZE);
+    }
+    //Case 3) Update only segment probabilities
+    if((pic_param->pic_fields.bits.segmentation_enabled &&
+        pic_param->pic_fields.bits.segmentation_update_map))
+    {
+        //Update seg_tree_probs and seg_pred_probs accordingly
+        for (i=0; i<SEG_TREE_PROBS; i++)
+        {
+            gen9_hcpd_context->vp9_fc.seg_tree_probs[i] = pic_param->mb_segment_tree_probs[i];
+        }
+        for (i=0; i<PREDICTION_PROBS; i++)
+        {
+            gen9_hcpd_context->vp9_fc.seg_pred_probs[i] = pic_param->segment_pred_probs[i];
+        }
+    }
+
+    //Case 4) Considering Intra only frame in the middle of Inter frames
+    if((pic_param->pic_fields.bits.intra_only &&
+        (pic_param->pic_fields.bits.frame_type == HCP_VP9_INTER_FRAME)&&
+        (pic_param->pic_fields.bits.reset_frame_context==0  ||
+        pic_param->pic_fields.bits.reset_frame_context==1||
+        pic_param->pic_fields.bits.reset_frame_context==2||
+        pic_param->pic_fields.bits.reset_frame_context==3)) &&
+        (last_frame_type == HCP_VP9_INTER_FRAME))
+    {
+        //save the inter frame values for the 343 bytes
+        //Update the 343 bytes of the buffer with Intra values
+        is_saved = VP9_PROB_BUFFER_SAVED_SECNE_1;
+    }
+    //Case 5) Considering Intra only frame among 3 Inter frames
+    if((pic_param->pic_fields.bits.intra_only &&
+        (pic_param->pic_fields.bits.frame_type == HCP_VP9_INTER_FRAME)&&
+        (pic_param->pic_fields.bits.reset_frame_context==2 ||
+        pic_param->pic_fields.bits.frame_context_idx==1)) &&
+        ((last_frame_type == HCP_VP9_INTER_FRAME) &&
+        (gen9_hcpd_context->last_frame.frame_context_idx==0)))
+    {
+        //save the inter frame values for the 343 bytes
+        //Update the 343 bytes of the buffer with Intra values
+        is_saved = VP9_PROB_BUFFER_SAVED_SECNE_2;
+    }
+
+    if(is_saved > VP9_PROB_BUFFER_SAVED_NO)
+    {
+        gen9_hcpd_context->vp9_saved_fc = gen9_hcpd_context->vp9_fc;
+        memcpy(gen9_hcpd_context->vp9_fc.inter_mode_probs,gen9_hcpd_context->vp9_fc_key_default.inter_mode_probs,VP9_PROB_BUFFER_KEY_INTER_SIZE);
+    }else if(pic_param->pic_fields.bits.intra_only)
+    {
+        is_restored = VP9_PROB_BUFFER_RESTORED_SECNE_MAX;
+
+    }
+
+    // update after the restored
+    if(gen9_hcpd_context->last_frame.prob_buffer_restored_flag == VP9_PROB_BUFFER_RESTORED_SECNE_2)
+    {
+        if((pic_param->pic_fields.bits.frame_type == HCP_VP9_INTER_FRAME) &&
+            pic_param->pic_fields.bits.frame_context_idx==1)
+        {
+            memcpy(&gen9_hcpd_context->vp9_fc,&gen9_hcpd_context->vp9_fc_inter_default,VP9_PROB_BUFFER_FIRST_PART_SIZE);
+        }
+    }
+
+    {
+        dri_bo_map(gen9_hcpd_context->vp9_probability_buffer.bo,1);
+        memcpy((unsigned char *)gen9_hcpd_context->vp9_probability_buffer.bo->virtual,&gen9_hcpd_context->vp9_fc,2048);
+        dri_bo_unmap(gen9_hcpd_context->vp9_probability_buffer.bo);
+    }
+    // save the flag in order to restore or update prob buffer
+    gen9_hcpd_context->last_frame.prob_buffer_saved_flag = is_saved;
+    gen9_hcpd_context->last_frame.prob_buffer_restored_flag = is_restored;
+}
+
+static void
+gen9_hcpd_init_vp9_surface(VADriverContextP ctx,
+                            VADecPictureParameterBufferVP9 *pic_param,
+                            struct object_surface *obj_surface,
+                            struct gen9_hcpd_context *gen9_hcpd_context)
+{
+    struct i965_driver_data *i965 = i965_driver_data(ctx);
+    GenVP9Surface *gen9_vp9_surface;
+    uint32_t size=0;
+
+    if (!obj_surface)
+        return;
+
+    obj_surface->free_private_data = gen_free_vp9_surface;
+    gen9_vp9_surface = obj_surface->private_data;
+
+    if (!gen9_vp9_surface) {
+        gen9_vp9_surface = calloc(sizeof(GenVP9Surface), 1);
+        gen9_vp9_surface->base.frame_store_id = -1;
+        obj_surface->private_data = gen9_vp9_surface;
+    }
+
+    //Super block size in VP9 is 64x64, size in SBs
+    size = gen9_hcpd_context->picture_width_in_ctbs * gen9_hcpd_context->picture_height_in_ctbs * 9 ;
+    size<<=6; //CL aligned
+
+    if (gen9_vp9_surface->motion_vector_temporal_bo == NULL) {
+        gen9_vp9_surface->motion_vector_temporal_bo = dri_bo_alloc(i965->intel.bufmgr,
+                                                                   "current motion vector temporal buffer",
+                                                                    size,
+                                                                    0x1000);
+    }
+    gen9_vp9_surface->frame_width  = pic_param->frame_width;
+    gen9_vp9_surface->frame_height = pic_param->frame_height;
+
+}
+
+static VAStatus
+gen9_hcpd_vp9_decode_init(VADriverContextP ctx,
+                           struct decode_state *decode_state,
+                           struct gen9_hcpd_context *gen9_hcpd_context)
+{
+    struct i965_driver_data *i965 = i965_driver_data(ctx);
+    VADecPictureParameterBufferVP9 *pic_param;
+    struct object_surface *obj_surface;
+    uint32_t size;
+    int width_in_mbs=0, height_in_mbs=0;
+
+    assert(decode_state->pic_param && decode_state->pic_param->buffer);
+    pic_param = (VADecPictureParameterBufferVP9 *)decode_state->pic_param->buffer;
+
+    width_in_mbs = (pic_param->frame_width + 15) / 16;
+    height_in_mbs = (pic_param->frame_height + 15) / 16;
+
+    //For BXT, we support only till 4K
+    assert(width_in_mbs > 0 && width_in_mbs <= 256); /* 4K */
+    assert(height_in_mbs > 0 && height_in_mbs <= 256);
+
+    //Update the frame store buffers with the reference frames information
+    intel_update_vp9_frame_store_index(ctx,
+                                        decode_state,
+                                        pic_param,
+                                        gen9_hcpd_context->reference_surfaces);
+
+    /* Current decoded picture */
+    obj_surface = decode_state->render_object;
+    //Ensure there is a tiled render surface in NV12 format. If not, create one.
+    vp9_ensure_surface_bo(ctx, decode_state, obj_surface, pic_param);
+
+
+    //Super block in VP9 is 64x64
+    gen9_hcpd_context->ctb_size = 64;
+    gen9_hcpd_context->min_cb_size = 8; //Min block size is 4 or 8?
+
+    //If picture width/height is not multiple of 64, needs to upsize it to the next 64 pixels
+    //before calculation below.
+    gen9_hcpd_context->picture_width_in_ctbs  = ALIGN(pic_param->frame_width, gen9_hcpd_context->ctb_size) / gen9_hcpd_context->ctb_size;
+    gen9_hcpd_context->picture_height_in_ctbs = ALIGN(pic_param->frame_height, gen9_hcpd_context->ctb_size) / gen9_hcpd_context->ctb_size;
+
+    gen9_hcpd_context->picture_width_in_min_cb_minus1  = ALIGN(pic_param->frame_width, gen9_hcpd_context->min_cb_size) / gen9_hcpd_context->min_cb_size - 1;
+    gen9_hcpd_context->picture_height_in_min_cb_minus1 = ALIGN(pic_param->frame_height, gen9_hcpd_context->min_cb_size) / gen9_hcpd_context->min_cb_size - 1;
+
+    gen9_hcpd_context->picture_width_in_pixels  = (gen9_hcpd_context->picture_width_in_min_cb_minus1  + 1) * gen9_hcpd_context->min_cb_size ;
+    gen9_hcpd_context->picture_height_in_pixels = (gen9_hcpd_context->picture_height_in_min_cb_minus1 + 1) * gen9_hcpd_context->min_cb_size ;
+
+    gen9_hcpd_init_vp9_surface(ctx, pic_param, obj_surface, gen9_hcpd_context);
+
+    size = gen9_hcpd_context->picture_width_in_ctbs*18; //num_width_in_SB * 18
+    size<<=6;
+    ALLOC_GEN_BUFFER((&gen9_hcpd_context->deblocking_filter_line_buffer), "line buffer", size);
+    ALLOC_GEN_BUFFER((&gen9_hcpd_context->deblocking_filter_tile_line_buffer), "tile line buffer", size);
+
+    size = gen9_hcpd_context->picture_height_in_ctbs*17; //num_height_in_SB * 17
+    size<<=6;
+    ALLOC_GEN_BUFFER((&gen9_hcpd_context->deblocking_filter_tile_column_buffer), "tile column buffer", size);
+
+    size = gen9_hcpd_context->picture_width_in_ctbs*5; //num_width_in_SB * 5
+    size<<=6;
+    ALLOC_GEN_BUFFER((&gen9_hcpd_context->metadata_line_buffer), "metadata line buffer", size);
+    ALLOC_GEN_BUFFER((&gen9_hcpd_context->metadata_tile_line_buffer), "metadata tile line buffer", size);
+
+    size = gen9_hcpd_context->picture_height_in_ctbs*5; //num_height_in_SB * 5
+    size<<=6;
+    ALLOC_GEN_BUFFER((&gen9_hcpd_context->metadata_tile_column_buffer), "metadata tile column buffer", size);
+
+    size =gen9_hcpd_context->picture_width_in_ctbs*1; //num_width_in_SB * 1
+    size<<=6;
+    ALLOC_GEN_BUFFER((&gen9_hcpd_context->hvd_line_rowstore_buffer), "hvd line rowstore buffer", size);
+    ALLOC_GEN_BUFFER((&gen9_hcpd_context->hvd_tile_rowstore_buffer), "hvd tile rowstore buffer", size);
+
+    size = 32;
+    size<<=6;
+    ALLOC_GEN_BUFFER((&gen9_hcpd_context->vp9_probability_buffer), "vp9 probability buffer", size);
+
+    size = (gen9_hcpd_context->picture_width_in_min_cb_minus1+2)*(gen9_hcpd_context->picture_height_in_min_cb_minus1 + 2) * 1;
+    size<<=6;
+    ALLOC_GEN_BUFFER((&gen9_hcpd_context->vp9_segment_id_buffer), "vp9 segment id buffer", size);
+
+    gen9_hcpd_context->first_inter_slice_collocated_ref_idx = 0;
+    gen9_hcpd_context->first_inter_slice_collocated_from_l0_flag = 0;
+    gen9_hcpd_context->first_inter_slice_valid = 0;
+
+    return VA_STATUS_SUCCESS;
+}
+
+static void
+gen9_hcpd_vp9_surface_state(VADriverContextP ctx,
+                        struct decode_state *decode_state,
+                        struct gen9_hcpd_context *gen9_hcpd_context)
+{
+    struct intel_batchbuffer *batch = gen9_hcpd_context->base.batch;
+    struct object_surface *obj_surface = decode_state->render_object;
+    struct object_surface *tmp_obj_surface = NULL;
+    unsigned int y_cb_offset;
+    int i = 0;
+
+    assert(obj_surface);
+
+    y_cb_offset = obj_surface->y_cb_offset;
+
+    BEGIN_BCS_BATCH(batch, 3);
+
+    OUT_BCS_BATCH(batch, HCP_SURFACE_STATE | (3 - 2));
+    OUT_BCS_BATCH(batch,
+                  (0 << 28) |                   /* surface id */
+                  (obj_surface->width - 1));    /* pitch - 1 */
+    OUT_BCS_BATCH(batch,
+                  (SURFACE_FORMAT_PLANAR_420_8 << 28) |
+                  y_cb_offset);
+    ADVANCE_BCS_BATCH(batch);
+
+    tmp_obj_surface = obj_surface;
+
+    for(i = 0; i < 3; i++)
+    {
+        obj_surface = gen9_hcpd_context->reference_surfaces[i].obj_surface;
+        if (obj_surface && obj_surface->private_data)
+        {
+            BEGIN_BCS_BATCH(batch, 3);
+
+            OUT_BCS_BATCH(batch, HCP_SURFACE_STATE | (3 - 2));
+            OUT_BCS_BATCH(batch,
+                ((i + 2) << 28) |                   /* surface id */
+                (obj_surface->width - 1));    /* pitch - 1 */
+            OUT_BCS_BATCH(batch,
+                (SURFACE_FORMAT_PLANAR_420_8 << 28) |
+                obj_surface->y_cb_offset);
+            ADVANCE_BCS_BATCH(batch);
+        }else
+        {
+            BEGIN_BCS_BATCH(batch, 3);
+
+            OUT_BCS_BATCH(batch, HCP_SURFACE_STATE | (3 - 2));
+            OUT_BCS_BATCH(batch,
+                ((i + 2) << 28) |                   /* surface id */
+                (tmp_obj_surface->width - 1));    /* pitch - 1 */
+            OUT_BCS_BATCH(batch,
+                (SURFACE_FORMAT_PLANAR_420_8 << 28) |
+                tmp_obj_surface->y_cb_offset);
+            ADVANCE_BCS_BATCH(batch);
+        }
+    }
+}
+
+static void
+gen9_hcpd_vp9_pipe_buf_addr_state(VADriverContextP ctx,
+                              struct decode_state *decode_state,
+                              struct gen9_hcpd_context *gen9_hcpd_context)
+{
+    struct intel_batchbuffer *batch = gen9_hcpd_context->base.batch;
+    struct object_surface *obj_surface;
+    GenVP9Surface *gen9_vp9_surface;
+    int i=0;
+
+    BEGIN_BCS_BATCH(batch, 95);
+
+    OUT_BCS_BATCH(batch, HCP_PIPE_BUF_ADDR_STATE | (95 - 2));
+
+    obj_surface = decode_state->render_object;
+    assert(obj_surface && obj_surface->bo);
+    gen9_vp9_surface = obj_surface->private_data;
+    assert(gen9_vp9_surface && gen9_vp9_surface->motion_vector_temporal_bo);
+
+    OUT_BUFFER_MA_TARGET(obj_surface->bo); /* DW 1..3 */
+    OUT_BUFFER_MA_TARGET(gen9_hcpd_context->deblocking_filter_line_buffer.bo);/* DW 4..6 */
+    OUT_BUFFER_MA_TARGET(gen9_hcpd_context->deblocking_filter_tile_line_buffer.bo); /* DW 7..9 */
+    OUT_BUFFER_MA_TARGET(gen9_hcpd_context->deblocking_filter_tile_column_buffer.bo); /* DW 10..12 */
+    OUT_BUFFER_MA_TARGET(gen9_hcpd_context->metadata_line_buffer.bo);         /* DW 13..15 */
+    OUT_BUFFER_MA_TARGET(gen9_hcpd_context->metadata_tile_line_buffer.bo);    /* DW 16..18 */
+    OUT_BUFFER_MA_TARGET(gen9_hcpd_context->metadata_tile_column_buffer.bo);  /* DW 19..21 */
+    OUT_BUFFER_MA_TARGET(NULL);    /* DW 22..24, ignore for VP9 */
+    OUT_BUFFER_MA_TARGET(NULL);    /* DW 25..27, ignore for VP9 */
+    OUT_BUFFER_MA_TARGET(NULL);    /* DW 28..30, ignore for VP9 */
+    OUT_BUFFER_MA_TARGET(gen9_vp9_surface->motion_vector_temporal_bo); /* DW 31..33 */
+
+    OUT_BUFFER_MA_TARGET(NULL); /* DW 34..36, reserved */
+
+    /* DW 37..52 - Reference picture address */
+    for (i = 0; i < 3; i++)
+    {
+        obj_surface = gen9_hcpd_context->reference_surfaces[i].obj_surface;
+
+        if (obj_surface)
+        {
+            OUT_BUFFER_NMA_REFERENCE(obj_surface->bo);
+        }
+        else
+            OUT_BUFFER_NMA_REFERENCE(NULL);
+    }
+    for (; i < ARRAY_ELEMS(gen9_hcpd_context->reference_surfaces); i++)
+    {
+       OUT_BUFFER_NMA_REFERENCE(NULL);
+    }
+    OUT_BCS_BATCH(batch, 0);    /* DW 53, memory address attributes */
+
+    OUT_BUFFER_MA_REFERENCE(NULL); /* DW 54..56, ignore for decoding mode */
+    OUT_BUFFER_MA_TARGET(NULL); /* DW 57..59, StreamOutEnable - used for transcoding */
+    OUT_BUFFER_MA_TARGET(NULL); /* DW 60..62, DecodedPictureStatusError, ignored */
+    OUT_BUFFER_MA_TARGET(NULL); /* DW 63..65, Ignored */
+
+    /* DW 66..81 - for 8 Collocated motion vectors */
+    for (i = 0; i < 1; i++)
+    {
+        OUT_BUFFER_NMA_REFERENCE(gen9_hcpd_context->last_frame.mv_temporal_buffer_bo);
+    }
+    for (; i < ARRAY_ELEMS(gen9_hcpd_context->reference_surfaces); i++)
+    {
+        OUT_BUFFER_NMA_REFERENCE(NULL);
+    }
+
+    OUT_BCS_BATCH(batch, 0);    /* DW 82, memory address attributes */
+
+    OUT_BUFFER_MA_TARGET(gen9_hcpd_context->vp9_probability_buffer.bo); /* DW 83..85, VP9 Probability bufffer */
+    OUT_BUFFER_MA_TARGET(gen9_hcpd_context->vp9_segment_id_buffer.bo);  /* DW 86..88, VP9 Segment ID buffer */
+    OUT_BUFFER_MA_TARGET(gen9_hcpd_context->hvd_line_rowstore_buffer.bo);/* DW 89..91, VP9 HVD Line Rowstore buffer */
+    OUT_BUFFER_MA_TARGET(gen9_hcpd_context->hvd_tile_rowstore_buffer.bo);/* DW 92..94, VP9 HVD Tile Rowstore buffer */
+
+    ADVANCE_BCS_BATCH(batch);
+    gen9_hcpd_context->last_frame.mv_temporal_buffer_bo = gen9_vp9_surface->motion_vector_temporal_bo;
+}
+
+static inline int
+gen9_hcpd_vp9_valid_ref_frame_size(int ref_width, int ref_height,
+                                   int cur_width, int cur_height) {
+  return 2 * cur_width >= ref_width &&
+         2 * cur_height >= ref_height &&
+         cur_width <= 16 * ref_width &&
+         cur_height <= 16 * ref_height;
+}
+static void
+gen9_hcpd_vp9_pic_state(VADriverContextP ctx,
+                       struct decode_state *decode_state,
+                       struct gen9_hcpd_context *gen9_hcpd_context)
+{
+    struct intel_batchbuffer *batch = gen9_hcpd_context->base.batch;
+    VADecPictureParameterBufferVP9 *pic_param;
+    struct object_surface *obj_surface;
+    GenVP9Surface *gen9_vp9_surface;
+    uint16_t scale_h = 0;
+    uint16_t scale_w = 0;
+    uint16_t frame_width_in_pixel = 0;
+    uint16_t frame_height_in_pixel = 0;
+    uint16_t fwidth = 64;
+    uint16_t fheight = 64;
+    int i;
+#define LEN_COMMAND_OWN 12
+    assert(decode_state->pic_param && decode_state->pic_param->buffer);
+    pic_param = (VADecPictureParameterBufferVP9 *)decode_state->pic_param->buffer;
+
+    uint8_t segmentIDStreamInEnable = 0;
+    uint8_t segmentIDStreamOutEnable = (pic_param->pic_fields.bits.segmentation_enabled && pic_param->pic_fields.bits.segmentation_update_map);
+
+    // For KEY_FRAME or INTRA_ONLY frame, this bit should be set to "0".
+    uint8_t segmentation_temporal_update =
+    ((pic_param->pic_fields.bits.frame_type == HCP_VP9_KEY_FRAME) || (pic_param->pic_fields.bits.intra_only)) ? 0 : pic_param->pic_fields.bits.segmentation_temporal_update;
+
+
+    if(pic_param->pic_fields.bits.intra_only || (pic_param->pic_fields.bits.frame_type == HCP_VP9_KEY_FRAME))
+    {
+        segmentIDStreamInEnable = 1;
+    }else if(pic_param->pic_fields.bits.segmentation_enabled)
+    {
+        if(!pic_param->pic_fields.bits.segmentation_update_map)
+        {
+            segmentIDStreamInEnable = 1;
+
+        }else if( pic_param->pic_fields.bits.segmentation_temporal_update)
+        {
+            segmentIDStreamInEnable = 1;
+        }
+    }
+
+    if(pic_param->pic_fields.bits.error_resilient_mode)
+    {
+        segmentIDStreamInEnable = 1;
+    }
+
+    //frame type of previous frame (Key or Non-Key Frame).
+    uint8_t last_frame_type = gen9_hcpd_context->last_frame.frame_type;
+
+    uint8_t use_pre_frame_mvs = 0;
+    use_pre_frame_mvs = !((pic_param->pic_fields.bits.error_resilient_mode) ||
+                                (pic_param->frame_width != gen9_hcpd_context->last_frame.frame_width) ||
+                                (pic_param->frame_height != gen9_hcpd_context->last_frame.frame_height) ||
+                                (pic_param->pic_fields.bits.intra_only) ||
+                                (pic_param->pic_fields.bits.frame_type == HCP_VP9_KEY_FRAME)||
+                                (gen9_hcpd_context->last_frame.intra_only)||
+                                (last_frame_type == HCP_VP9_KEY_FRAME) ||
+                                (!gen9_hcpd_context->last_frame.show_frame));
+
+    uint8_t adapt_probabilities_flag = 0;
+    if((pic_param->pic_fields.bits.error_resilient_mode || pic_param->pic_fields.bits.frame_parallel_decoding_mode))
+        adapt_probabilities_flag = 0; //0: Do not adapt (error resilient or frame_parallel_mode are set)
+    else if(!(pic_param->pic_fields.bits.error_resilient_mode) && !(pic_param->pic_fields.bits.frame_parallel_decoding_mode))
+        adapt_probabilities_flag = 1; //1: Adapt (not error resilient and not frame_ parallel_mode)
+
+    frame_width_in_pixel  = (gen9_hcpd_context->picture_width_in_min_cb_minus1  + 1) * gen9_hcpd_context->min_cb_size ;
+    frame_height_in_pixel = (gen9_hcpd_context->picture_height_in_min_cb_minus1 + 1) * gen9_hcpd_context->min_cb_size ;
+
+    fwidth = (fwidth > frame_width_in_pixel)?frame_width_in_pixel:fwidth;
+    fheight = (fheight > frame_height_in_pixel)?frame_height_in_pixel:fheight;
+
+    BEGIN_BCS_BATCH(batch, LEN_COMMAND_OWN);
+
+    OUT_BCS_BATCH(batch, HCP_VP9_PIC_STATE | (LEN_COMMAND_OWN - 2));
+
+    OUT_BCS_BATCH(batch,
+                  (frame_height_in_pixel - 1) << 16 |
+                  (frame_width_in_pixel - 1));         /* DW 1 */
+    OUT_BCS_BATCH(batch,
+                  segmentIDStreamInEnable << 31 |
+                  segmentIDStreamOutEnable << 30 |
+                  pic_param->pic_fields.bits.lossless_flag << 29 |
+                  segmentation_temporal_update << 28 |
+                  pic_param->pic_fields.bits.segmentation_update_map << 27 |
+                  pic_param->pic_fields.bits.segmentation_enabled << 26   |
+                  pic_param->sharpness_level << 23 |
+                  pic_param->filter_level << 17 |
+                  pic_param->pic_fields.bits.frame_parallel_decoding_mode << 16 |
+                  pic_param->pic_fields.bits.error_resilient_mode << 15 |
+                  pic_param->pic_fields.bits.refresh_frame_context << 14 |
+                  last_frame_type << 13 |
+                  0 << 12 |   /* tx select mode */
+                  0 << 11 |   /* Hybrid Prediction Mode */
+                  use_pre_frame_mvs << 10 |
+                  pic_param->pic_fields.bits.alt_ref_frame_sign_bias << 9 |
+                  pic_param->pic_fields.bits.golden_ref_frame_sign_bias << 8 |
+                  pic_param->pic_fields.bits.last_ref_frame_sign_bias << 7 |
+                  pic_param->pic_fields.bits.mcomp_filter_type << 4 |
+                  pic_param->pic_fields.bits.allow_high_precision_mv << 3 |
+                  pic_param->pic_fields.bits.intra_only <<2 |
+                  adapt_probabilities_flag << 1 |
+                  pic_param->pic_fields.bits.frame_type <<0);               /* DW 2 */
+    OUT_BCS_BATCH(batch,
+        HCP_VP9_PROFILE0 << 28 |  /* Profile 0 only supports 8 bit 420 only */
+        pic_param->log2_tile_rows << 8 |
+        pic_param->log2_tile_columns <<0);                       /* DW 3 */
+    // resolution change case
+
+    // DW4-DW6
+    for(i = 0; i < 3; i++)
+    {
+        obj_surface = gen9_hcpd_context->reference_surfaces[i].obj_surface;
+        gen9_vp9_surface = NULL;
+        scale_w = 0;
+        scale_h = 0;
+        if (obj_surface && obj_surface->private_data)
+        {
+            gen9_vp9_surface = obj_surface->private_data;
+            if(!gen9_hcpd_vp9_valid_ref_frame_size(gen9_vp9_surface->frame_width,gen9_vp9_surface->frame_height,pic_param->frame_width,pic_param->frame_height))
+            {
+                scale_w = -1;
+                scale_h = -1;
+            }else
+            {
+                scale_w = (gen9_vp9_surface->frame_width  << 14) /pic_param->frame_width ;
+                scale_h = (gen9_vp9_surface->frame_height << 14) /pic_param->frame_height ;
+            }
+            OUT_BCS_BATCH(batch,
+                scale_w<<16 |
+                scale_h);
+        }else
+        {
+            OUT_BCS_BATCH(batch, 0);
+        }
+    }
+
+    // DW7-DW9
+    for(i = 0; i < 3; i++)
+    {
+        obj_surface = gen9_hcpd_context->reference_surfaces[i].obj_surface;
+        gen9_vp9_surface = NULL;
+
+        if (obj_surface && obj_surface->private_data)
+        {
+            gen9_vp9_surface = obj_surface->private_data;
+            OUT_BCS_BATCH(batch,
+                ((gen9_vp9_surface->frame_height- 1)&0x3fff)<<16 |
+                ((gen9_vp9_surface->frame_width - 1)&0x3fff));
+        }else
+        {
+            OUT_BCS_BATCH(batch, 0);
+        }
+    }
+
+    OUT_BCS_BATCH(batch,
+                  pic_param->first_partition_size << 16 |
+                  pic_param->frame_header_length_in_bytes <<0); /* DW 10 */
+    OUT_BCS_BATCH(batch,
+                  (0 << 3) |
+                  (0 << 2) |
+                  (1 << 1) |
+                  (0 << 0)); /* DW 11, ignored */
+    //Rest of the DWs are not valid for BXT
+    for(i = 12; i < LEN_COMMAND_OWN; i++)
+    {
+        OUT_BCS_BATCH(batch, 0);
+    }
+
+    ADVANCE_BCS_BATCH(batch);
+
+}
+
+static void
+gen9_hcpd_vp9_segment_state(VADriverContextP ctx,
+                            VADecPictureParameterBufferVP9 *pic_param,
+                            VASegmentParameterVP9 *seg_param, uint8_t seg_id,
+                            struct gen9_hcpd_context *gen9_hcpd_context)
+{
+    struct intel_batchbuffer *batch = gen9_hcpd_context->base.batch;
+
+    BEGIN_BCS_BATCH(batch, 7);
+
+    OUT_BCS_BATCH(batch, HCP_VP9_SEGMENT_STATE | (7 - 2));
+    OUT_BCS_BATCH(batch, seg_id << 0); /* DW 1 - SegmentID */
+    OUT_BCS_BATCH(batch,
+                  seg_param->segment_flags.fields.segment_reference_enabled << 3 |
+                  seg_param->segment_flags.fields.segment_reference << 1 |
+                  seg_param->segment_flags.fields.segment_reference_skipped <<0 ); /* DW 2 */
+    OUT_BCS_BATCH(batch,
+                  seg_param->filter_level[1][1] << 24    | //FilterLevelRef1Mode1
+                  seg_param->filter_level[1][0] << 16    | //FilterLevelRef1Mode0
+                  seg_param->filter_level[0][1] << 8     | //FilterLevelRef0Mode1
+                  seg_param->filter_level[0][0] << 0 );     //FilterLevelRef0Mode0 /* DW 3 */
+    OUT_BCS_BATCH(batch,
+                  seg_param->filter_level[3][1] << 24    | //FilterLevelRef3Mode1
+                  seg_param->filter_level[3][0] << 16    | //FilterLevelRef3Mode0
+                  seg_param->filter_level[2][1] << 8     | //FilterLevelRef2Mode1
+                  seg_param->filter_level[2][0] << 0 );    //FilterLevelRef2Mode0 /* DW 4 */
+    OUT_BCS_BATCH(batch,
+                  seg_param->luma_ac_quant_scale << 16   |
+                  seg_param->luma_dc_quant_scale << 0 );    /* DW 5 */
+    OUT_BCS_BATCH(batch,
+                  seg_param->chroma_ac_quant_scale << 16 |
+                  seg_param->chroma_dc_quant_scale << 0 );  /* DW 6 */
+
+    ADVANCE_BCS_BATCH(batch);
+
+}
+
+static void
+gen9_hcpd_vp9_bsd_object(VADriverContextP ctx,
+                     VADecPictureParameterBufferVP9 *pic_param,
+                     VASliceParameterBufferVP9 *slice_param,
+                     struct gen9_hcpd_context *gen9_hcpd_context)
+{
+    struct intel_batchbuffer *batch = gen9_hcpd_context->base.batch;
+    int slice_data_size   = slice_param->slice_data_size - pic_param->frame_header_length_in_bytes;
+    int slice_data_offset = slice_param->slice_data_offset + pic_param->frame_header_length_in_bytes;
+
+    BEGIN_BCS_BATCH(batch, 3);
+
+    OUT_BCS_BATCH(batch, HCP_BSD_OBJECT | (3 - 2));
+
+    OUT_BCS_BATCH(batch, slice_data_size );
+    OUT_BCS_BATCH(batch, slice_data_offset);
+
+    ADVANCE_BCS_BATCH(batch);
+
+}
+
+static VAStatus
+gen9_hcpd_vp9_decode_picture(VADriverContextP ctx,
+                              struct decode_state *decode_state,
+                              struct gen9_hcpd_context *gen9_hcpd_context)
+{
+    VAStatus vaStatus;
+    struct i965_driver_data *i965 = i965_driver_data(ctx);
+    struct intel_batchbuffer *batch = gen9_hcpd_context->base.batch;
+    VADecPictureParameterBufferVP9 *pic_param;
+    VASliceParameterBufferVP9 *slice_param;
+    dri_bo *slice_data_bo;
+    int i = 0, num_segments=0, isScaling=0;
+    struct object_surface *obj_surface;
+    GenVP9Surface *gen9_vp9_surface;
+    vaStatus = gen9_hcpd_vp9_decode_init(ctx, decode_state, gen9_hcpd_context);
+
+    if (vaStatus != VA_STATUS_SUCCESS)
+        goto out;
+
+    assert(decode_state->pic_param && decode_state->pic_param->buffer);
+    pic_param = (VADecPictureParameterBufferVP9 *)decode_state->pic_param->buffer;
+
+    //****And set the isScaling value accordingly******
+    isScaling = 0;
+    for(i = 0; i < 3; i++)
+    {
+        obj_surface = gen9_hcpd_context->reference_surfaces[i].obj_surface;
+        gen9_vp9_surface = NULL;
+        if (obj_surface && obj_surface->private_data)
+        {
+            gen9_vp9_surface = obj_surface->private_data;
+            isScaling |= (gen9_vp9_surface->frame_width == pic_param->frame_width &&
+                gen9_vp9_surface->frame_height == pic_param->frame_height)? 0:1;
+        }
+    }
+
+    //Update segment id buffer if needed
+    vp9_update_segmentId_buffer(ctx, decode_state, gen9_hcpd_context, isScaling);
+    //Update probability buffer if needed
+    vp9_update_probabilities(ctx, decode_state, gen9_hcpd_context);
+
+    if (i965->intel.has_bsd2)
+        intel_batchbuffer_start_atomic_bcs_override(batch, 0x1000, BSD_RING0);
+    else
+        intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
+    intel_batchbuffer_emit_mi_flush(batch);
+
+    gen9_hcpd_pipe_mode_select(ctx, decode_state, HCP_CODEC_VP9, gen9_hcpd_context);
+    //Not sure what the surface id value should be: Gold? ALtRef? PrevRef? or Just RefPic?
+    gen9_hcpd_vp9_surface_state(ctx, decode_state, gen9_hcpd_context);
+
+    //Only one VASliceParameterBufferVP9 should be sent per frame
+    assert(decode_state->slice_params && decode_state->slice_params[0]->buffer);
+    slice_param = (VASliceParameterBufferVP9 *)decode_state->slice_params[0]->buffer;
+    slice_data_bo = decode_state->slice_datas[0]->bo;
+
+    gen9_hcpd_ind_obj_base_addr_state(ctx, slice_data_bo, gen9_hcpd_context);
+
+    gen9_hcpd_vp9_pipe_buf_addr_state(ctx, decode_state, gen9_hcpd_context);
+    //If segmentation is disabled, only SegParam[0] is valid,
+    //all others should be populated with 0
+    if(!pic_param->pic_fields.bits.segmentation_enabled)
+        num_segments = 1;
+    else  //If segmentation is enabled, all 8 entries should be valid.
+        num_segments = 8;
+
+    for(i=0; i<num_segments; i++) {
+        VASegmentParameterVP9 seg_param = slice_param->seg_param[i];
+        gen9_hcpd_vp9_segment_state(ctx, pic_param, &seg_param, i, gen9_hcpd_context);
+    }
+
+    gen9_hcpd_vp9_pic_state(ctx, decode_state, gen9_hcpd_context);
+
+    gen9_hcpd_vp9_bsd_object(ctx, pic_param, slice_param, gen9_hcpd_context);
+
+    // keep track of the last frame status
+    gen9_hcpd_context->last_frame.frame_width = pic_param->frame_width;
+    gen9_hcpd_context->last_frame.frame_height = pic_param->frame_height;
+    gen9_hcpd_context->last_frame.show_frame = pic_param->pic_fields.bits.show_frame;
+    gen9_hcpd_context->last_frame.frame_type = pic_param->pic_fields.bits.frame_type;
+    gen9_hcpd_context->last_frame.refresh_frame_context = pic_param->pic_fields.bits.refresh_frame_context;
+    gen9_hcpd_context->last_frame.frame_context_idx = pic_param->pic_fields.bits.frame_context_idx;
+    gen9_hcpd_context->last_frame.intra_only = pic_param->pic_fields.bits.intra_only;
+
+    // update prob buffer to vp9_fc;
+
+    intel_batchbuffer_end_atomic(batch);
+    intel_batchbuffer_flush(batch);
+
+    //update vp9_frame_ctx according to frame_context_id
+    if (pic_param->pic_fields.bits.refresh_frame_context)
+    {
+        //update vp9_fc to frame_context
+        dri_bo_map(gen9_hcpd_context->vp9_probability_buffer.bo,1);
+        memcpy(&gen9_hcpd_context->vp9_fc,(unsigned char *)gen9_hcpd_context->vp9_probability_buffer.bo->virtual,2048);
+        dri_bo_unmap(gen9_hcpd_context->vp9_probability_buffer.bo);
+        gen9_hcpd_context->vp9_frame_ctx[pic_param->pic_fields.bits.frame_context_idx] = gen9_hcpd_context->vp9_fc;
+
+    }
+
+out:
+    return vaStatus;
+}
+
+
 static VAStatus
 gen9_hcpd_decode_picture(VADriverContextP ctx,
                          VAProfile profile,
@@ -977,6 +1887,9 @@ gen9_hcpd_decode_picture(VADriverContextP ctx,
     case VAProfileHEVCMain10:
         vaStatus = gen9_hcpd_hevc_decode_picture(ctx, decode_state, gen9_hcpd_context);
         break;
+    case VAProfileVP9Profile0:
+        vaStatus = gen9_hcpd_vp9_decode_picture(ctx, decode_state, gen9_hcpd_context);
+        break;
 
     default:
         /* should never get here 1!! */
@@ -1002,6 +1915,10 @@ gen9_hcpd_context_destroy(void *hw_context)
     FREE_GEN_BUFFER((&gen9_hcpd_context->sao_line_buffer));
     FREE_GEN_BUFFER((&gen9_hcpd_context->sao_tile_line_buffer));
     FREE_GEN_BUFFER((&gen9_hcpd_context->sao_tile_column_buffer));
+    FREE_GEN_BUFFER((&gen9_hcpd_context->hvd_line_rowstore_buffer));
+    FREE_GEN_BUFFER((&gen9_hcpd_context->hvd_tile_rowstore_buffer));
+    FREE_GEN_BUFFER((&gen9_hcpd_context->vp9_probability_buffer));
+    FREE_GEN_BUFFER((&gen9_hcpd_context->vp9_segment_id_buffer));
 
     intel_batchbuffer_free(gen9_hcpd_context->base.batch);
     free(gen9_hcpd_context);
@@ -1014,6 +1931,25 @@ gen9_hcpd_hevc_context_init(VADriverContextP ctx,
     hevc_gen_default_iq_matrix(&gen9_hcpd_context->iq_matrix_hevc);
 }
 
+static void
+gen9_hcpd_vp9_context_init(VADriverContextP ctx,
+                            struct gen9_hcpd_context *gen9_hcpd_context)
+{
+    int default_value = 255;
+
+    gen9_hcpd_context->last_frame.frame_height  = 0;
+    gen9_hcpd_context->last_frame.show_frame    = 0;
+    gen9_hcpd_context->last_frame.frame_type    = 0;
+    gen9_hcpd_context->last_frame.refresh_frame_context = default_value;
+    gen9_hcpd_context->last_frame.frame_context_idx = default_value;
+    gen9_hcpd_context->last_frame.intra_only = 0;
+    gen9_hcpd_context->last_frame.prob_buffer_saved_flag = 0;
+    gen9_hcpd_context->last_frame.prob_buffer_restored_flag = 0;
+    gen9_hcpd_context->last_frame.mv_temporal_buffer_bo = NULL;
+
+    vp9_gen_default_probabilities(ctx, gen9_hcpd_context);
+}
+
 static struct hw_context *
 gen9_hcpd_context_init(VADriverContextP ctx, struct object_config *object_config)
 {
@@ -1039,6 +1975,9 @@ gen9_hcpd_context_init(VADriverContextP ctx, struct object_config *object_config
     case VAProfileHEVCMain10:
         gen9_hcpd_hevc_context_init(ctx, gen9_hcpd_context);
         break;
+    case VAProfileVP9Profile0:
+        gen9_hcpd_vp9_context_init(ctx, gen9_hcpd_context);
+        break;
 
     default:
         break;
@@ -1051,7 +1990,8 @@ struct hw_context *
 gen9_dec_hw_context_init(VADriverContextP ctx, struct object_config *obj_config)
 {
     if (obj_config->profile == VAProfileHEVCMain ||
-        obj_config->profile == VAProfileHEVCMain10) {
+        obj_config->profile == VAProfileHEVCMain10 ||
+        obj_config->profile == VAProfileVP9Profile0) {
         return gen9_hcpd_context_init(ctx, obj_config);
     } else {
         return gen8_dec_hw_context_init(ctx, obj_config);
diff --git a/src/gen9_mfd.h b/src/gen9_mfd.h
index 6e9fa5d..c266dd4 100644
--- a/src/gen9_mfd.h
+++ b/src/gen9_mfd.h
@@ -34,9 +34,24 @@
 #include <i915_drm.h>
 #include <intel_bufmgr.h>
 #include "i965_decoder.h"
+#include "vp9_probs.h"
 
 struct hw_context;
 
+typedef struct vp9_frame_status
+{
+    uint16_t frame_width;
+    uint16_t frame_height;
+    uint8_t frame_type;
+    uint8_t show_frame;
+    uint8_t refresh_frame_context;
+    uint8_t frame_context_idx;
+    uint8_t intra_only;
+    uint8_t prob_buffer_saved_flag;
+    uint8_t prob_buffer_restored_flag;
+    dri_bo * mv_temporal_buffer_bo;
+}vp9_last_frame_status;
+
 struct gen9_hcpd_context
 {
     struct hw_context base;
@@ -65,10 +80,21 @@ struct gen9_hcpd_context
     GenBuffer sao_line_buffer;
     GenBuffer sao_tile_line_buffer;
     GenBuffer sao_tile_column_buffer;
+    GenBuffer hvd_line_rowstore_buffer;
+    GenBuffer hvd_tile_rowstore_buffer;
+    GenBuffer vp9_probability_buffer;
+    GenBuffer vp9_segment_id_buffer;
 
     unsigned short first_inter_slice_collocated_ref_idx;
     unsigned short first_inter_slice_collocated_from_l0_flag;
     int first_inter_slice_valid;
+
+    vp9_last_frame_status last_frame;
+    FRAME_CONTEXT vp9_frame_ctx[FRAME_CONTEXTS];
+    FRAME_CONTEXT vp9_fc_inter_default;
+    FRAME_CONTEXT vp9_fc_key_default;
+    FRAME_CONTEXT vp9_fc;
+    FRAME_CONTEXT vp9_saved_fc;
 };
 
 #endif /* GEN9_MFD_H */
-- 
cgit v1.2.3


From 6859ab7a51650cbcfa8159a37cf8d1485d162ad4 Mon Sep 17 00:00:00 2001
From: Pengfei Qu <Pengfei.Qu@intel.com>
Date: Thu, 22 Oct 2015 04:55:04 -0400
Subject: VP9 HWDec:change the name vp8_xxx to vpx_xxx and share it with VP9

Signed-off-by: Pengfei Qu <Pengfei.Qu@intel.com>
Signed-off-by: Sirisha Muppavarapu <sirisha.muppavarapu@intel.com>
Signed-off-by: peng.chen <peng.c.chen@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
---
 src/vp8_probs.AUTHORS | 100 --------------------------------------------------
 src/vp8_probs.LICENSE |  31 ----------------
 src/vp8_probs.PATENTS |  22 -----------
 src/vpx_probs.AUTHORS |   0
 src/vpx_probs.LICENSE |   0
 src/vpx_probs.PATENTS |   0
 6 files changed, 153 deletions(-)
 delete mode 100644 src/vp8_probs.AUTHORS
 delete mode 100644 src/vp8_probs.LICENSE
 delete mode 100644 src/vp8_probs.PATENTS
 create mode 100644 src/vpx_probs.AUTHORS
 create mode 100644 src/vpx_probs.LICENSE
 create mode 100644 src/vpx_probs.PATENTS

diff --git a/src/vp8_probs.AUTHORS b/src/vp8_probs.AUTHORS
deleted file mode 100644
index a9aa481..0000000
--- a/src/vp8_probs.AUTHORS
+++ /dev/null
@@ -1,100 +0,0 @@
-# This file is automatically generated from the git commit history
-# by tools/gen_authors.sh.
-
-Aaron Watry <awatry@gmail.com>
-Abo Talib Mahfoodh <ab.mahfoodh@gmail.com>
-Adrian Grange <agrange@google.com>
-Ahmad Sharif <asharif@google.com>
-Alexander Voronov <avoronov@graphics.cs.msu.ru>
-Alex Converse <alex.converse@gmail.com>
-Alexis Ballier <aballier@gentoo.org>
-Alok Ahuja <waveletcoeff@gmail.com>
-Alpha Lam <hclam@google.com>
-A.Mahfoodh <ab.mahfoodh@gmail.com>
-Ami Fischman <fischman@chromium.org>
-Andoni Morales Alastruey <ylatuya@gmail.com>
-Andres Mejia <mcitadel@gmail.com>
-Aron Rosenberg <arosenberg@logitech.com>
-Attila Nagy <attilanagy@google.com>
-changjun.yang <changjun.yang@intel.com>
-chm <chm@rock-chips.com>
-Christian Duvivier <cduvivier@google.com>
-Daniel Kang <ddkang@google.com>
-Deb Mukherjee <debargha@google.com>
-Dmitry Kovalev <dkovalev@google.com>
-Dragan Mrdjan <dmrdjan@mips.com>
-Erik Niemeyer <erik.a.niemeyer@gmail.com>
-Fabio Pedretti <fabio.ped@libero.it>
-Frank Galligan <fgalligan@google.com>
-Fredrik Söderquist <fs@opera.com>
-Fritz Koenig <frkoenig@google.com>
-Gaute Strokkenes <gaute.strokkenes@broadcom.com>
-Giuseppe Scrivano <gscrivano@gnu.org>
-Guillaume Martres <gmartres@google.com>
-Guillermo Ballester Valor <gbvalor@gmail.com>
-Hangyu Kuang <hkuang@google.com>
-Henrik Lundin <hlundin@google.com>
-Hui Su <huisu@google.com>
-Ivan Maltz <ivanmaltz@google.com>
-James Berry <jamesberry@google.com>
-James Zern <jzern@google.com>
-Jan Kratochvil <jan.kratochvil@redhat.com>
-Janne Salonen <jsalonen@google.com>
-Jeff Faust <jfaust@google.com>
-Jeff Muizelaar <jmuizelaar@mozilla.com>
-Jeff Petkau <jpet@chromium.org>
-Jim Bankoski <jimbankoski@google.com>
-Jingning Han <jingning@google.com>
-Johann Koenig <johannkoenig@google.com>
-John Koleszar <jkoleszar@google.com>
-Joshua Bleecher Snyder <josh@treelinelabs.com>
-Joshua Litt <joshualitt@google.com>
-Justin Clift <justin@salasaga.org>
-Justin Lebar <justin.lebar@gmail.com>
-KO Myung-Hun <komh@chollian.net>
-Lou Quillio <louquillio@google.com>
-Luca Barbato <lu_zero@gentoo.org>
-Makoto Kato <makoto.kt@gmail.com>
-Mans Rullgard <mans@mansr.com>
-Marco Paniconi <marpan@google.com>
-Mark Mentovai <mark@chromium.org>
-Martin Ettl <ettl.martin78@googlemail.com>
-Martin Storsjo <martin@martin.st>
-Matthew Heaney <matthewjheaney@chromium.org>
-Michael Kohler <michaelkohler@live.com>
-Mike Frysinger <vapier@chromium.org>
-Mike Hommey <mhommey@mozilla.com>
-Mikhal Shemer <mikhal@google.com>
-Morton Jonuschat <yabawock@gmail.com>
-Parag Salasakar <img.mips1@gmail.com>
-Pascal Massimino <pascal.massimino@gmail.com>
-Patrik Westin <patrik.westin@gmail.com>
-Paul Wilkins <paulwilkins@google.com>
-Pavol Rusnak <stick@gk2.sk>
-Paweł Hajdan <phajdan@google.com>
-Philip Jägenstedt <philipj@opera.com>
-Priit Laes <plaes@plaes.org>
-Rafael Ávila de Espíndola <rafael.espindola@gmail.com>
-Rafaël Carré <funman@videolan.org>
-Ralph Giles <giles@xiph.org>
-Rob Bradford <rob@linux.intel.com>
-Ronald S. Bultje <rbultje@google.com>
-Sami Pietilä <samipietila@google.com>
-Scott Graham <scottmg@chromium.org>
-Scott LaVarnway <slavarnway@google.com>
-Shimon Doodkin <helpmepro1@gmail.com>
-Stefan Holmer <holmer@google.com>
-Suman Sunkara <sunkaras@google.com>
-Taekhyun Kim <takim@nvidia.com>
-Takanori MATSUURA <t.matsuu@gmail.com>
-Tamar Levy <tamar.levy@intel.com>
-Tero Rintaluoma <teror@google.com>
-Thijs Vermeir <thijsvermeir@gmail.com>
-Timothy B. Terriberry <tterribe@xiph.org>
-Tom Finegan <tomfinegan@google.com>
-Vignesh Venkatasubramanian <vigneshv@google.com>
-Yaowu Xu <yaowu@google.com>
-Yunqing Wang <yunqingwang@google.com>
-Google Inc.
-The Mozilla Foundation
-The Xiph.Org Foundation
diff --git a/src/vp8_probs.LICENSE b/src/vp8_probs.LICENSE
deleted file mode 100644
index 1ce4434..0000000
--- a/src/vp8_probs.LICENSE
+++ /dev/null
@@ -1,31 +0,0 @@
-Copyright (c) 2010, The WebM Project authors. All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are
-met:
-
-  * Redistributions of source code must retain the above copyright
-    notice, this list of conditions and the following disclaimer.
-
-  * Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions and the following disclaimer in
-    the documentation and/or other materials provided with the
-    distribution.
-
-  * Neither the name of Google, nor the WebM Project, nor the names
-    of its contributors may be used to endorse or promote products
-    derived from this software without specific prior written
-    permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
diff --git a/src/vp8_probs.PATENTS b/src/vp8_probs.PATENTS
deleted file mode 100644
index 4414d83..0000000
--- a/src/vp8_probs.PATENTS
+++ /dev/null
@@ -1,22 +0,0 @@
-Additional IP Rights Grant (Patents)
-
-"This implementation" means the copyrightable works distributed by
-Google as part of the WebM Project.
-
-Google hereby grants to you a perpetual, worldwide, non-exclusive,
-no-charge, royalty-free, irrevocable (except as stated in this section)
-patent license to make, have made, use, offer to sell, sell, import,
-transfer, and otherwise run, modify and propagate the contents of this
-implementation of VP8, where such license applies only to those patent
-claims, both currently owned by Google and acquired in the future,
-licensable by Google that are necessarily infringed by this
-implementation of VP8. This grant does not include claims that would be
-infringed only as a consequence of further modification of this
-implementation. If you or your agent or exclusive licensee institute or
-order or agree to the institution of patent litigation against any
-entity (including a cross-claim or counterclaim in a lawsuit) alleging
-that this implementation of VP8 or any code incorporated within this
-implementation of VP8 constitutes direct or contributory patent
-infringement, or inducement of patent infringement, then any patent
-rights granted to you under this License for this implementation of VP8
-shall terminate as of the date such litigation is filed.
diff --git a/src/vpx_probs.AUTHORS b/src/vpx_probs.AUTHORS
new file mode 100644
index 0000000..e69de29
diff --git a/src/vpx_probs.LICENSE b/src/vpx_probs.LICENSE
new file mode 100644
index 0000000..e69de29
diff --git a/src/vpx_probs.PATENTS b/src/vpx_probs.PATENTS
new file mode 100644
index 0000000..e69de29
-- 
cgit v1.2.3


From e16f923193a10f78f5462db7efa4e89e242fca93 Mon Sep 17 00:00:00 2001
From: Sirisha Muppavarapu <sirisha.muppavarapu@intel.com>
Date: Fri, 30 Oct 2015 03:43:21 +0800
Subject: Export VP9 decoding on BXT

Signed-off-by: Sirisha Muppavarapu <sirisha.muppavarapu@intel.com>
Signed-off-by: peng.chen <peng.c.chen@intel.com>
---
 src/i965_device_info.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/i965_device_info.c b/src/i965_device_info.c
index db904ae..4921922 100644
--- a/src/i965_device_info.c
+++ b/src/i965_device_info.c
@@ -400,6 +400,7 @@ static struct hw_codec_info bxt_hw_codec_info = {
     .has_hevc_decoding = 1,
     .has_hevc_encoding = 1,
     .has_hevc10_decoding = 1,
+    .has_vp9_decoding = 1,
 
     .num_filters = 5,
     .filters = {
-- 
cgit v1.2.3


From 9ce333f193fa0f56ec09b9f5b2f4823461f48776 Mon Sep 17 00:00:00 2001
From: "Xiang, Haihao" <haihao.xiang@intel.com>
Date: Mon, 7 Dec 2015 13:13:26 +0800
Subject: Keep backward compatibility with VA API 0.38.0

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
---
 src/va_backend_compat.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/va_backend_compat.h b/src/va_backend_compat.h
index 8767153..7f0a607 100644
--- a/src/va_backend_compat.h
+++ b/src/va_backend_compat.h
@@ -50,4 +50,12 @@
 # define VAProfileH264StereoHigh        16
 #endif
 
+#if !VA_CHECK_VERSION(0,38,1)
+
+# define VA_RT_FORMAT_YUV420_10BPP      0x00000100
+# define VA_FOURCC_P010                 0x30313050
+# define VA_FOURCC_P016                 0x36313050
+
+#endif
+
 #endif /* VA_BACKEND_COMPAT_H */
-- 
cgit v1.2.3


From e8197f18c517fa7d122a8392fb5f5af84fe1f440 Mon Sep 17 00:00:00 2001
From: "Xiang, Haihao" <haihao.xiang@intel.com>
Date: Mon, 14 Dec 2015 01:18:57 +0800
Subject: 1.6.3.pre1 for development

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
---
 configure.ac | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configure.ac b/configure.ac
index 8064cae..a8d017b 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1,7 +1,7 @@
 # intel-driver package version number
 m4_define([intel_driver_major_version], [1])
 m4_define([intel_driver_minor_version], [6])
-m4_define([intel_driver_micro_version], [2])
+m4_define([intel_driver_micro_version], [3])
 m4_define([intel_driver_pre_version],   [1])
 m4_define([intel_driver_version],
           [intel_driver_major_version.intel_driver_minor_version.intel_driver_micro_version])
-- 
cgit v1.2.3


From a7803c0642a8f2923ce3c51a0a717688fe2c5459 Mon Sep 17 00:00:00 2001
From: Lim Siew Hoon <siew.hoon.lim@intel.com>
Date: Thu, 10 Dec 2015 16:07:47 +0800
Subject: Add assert checking for allocated gen9_vp9_surface

Signed-off-by: Lim Siew Hoon <siew.hoon.lim@intel.com>
---
 src/gen9_mfd.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/gen9_mfd.c b/src/gen9_mfd.c
index d9ca3be..2d8ed7d 100644
--- a/src/gen9_mfd.c
+++ b/src/gen9_mfd.c
@@ -1277,6 +1277,7 @@ gen9_hcpd_init_vp9_surface(VADriverContextP ctx,
 
     if (!gen9_vp9_surface) {
         gen9_vp9_surface = calloc(sizeof(GenVP9Surface), 1);
+        assert(gen9_vp9_surface);
         gen9_vp9_surface->base.frame_store_id = -1;
         obj_surface->private_data = gen9_vp9_surface;
     }
-- 
cgit v1.2.3


From e13af2d393f1a120e93c5134af393bd3a78399b0 Mon Sep 17 00:00:00 2001
From: Pengfei Qu <Pengfei.Qu@intel.com>
Date: Tue, 29 Dec 2015 16:09:24 +0800
Subject: VP9HWDEC:fix vp9 hw decoder issue

v2:
codes change according to haihao's comments

v1:
1. fix one segmentent fault issue
2. change and optimize the mv bufffer update the logic
3. fix one segment feature issue
4. fix one issue when loopfilter level is zero.

Signed-off-by: Pengfei Qu <Pengfei.Qu@intel.com>
---
 src/gen9_mfd.c           | 186 +++++++++++++++++++++++++++++------------------
 src/gen9_mfd.h           |  10 ++-
 src/intel_media_common.c |   3 -
 3 files changed, 126 insertions(+), 73 deletions(-)

diff --git a/src/gen9_mfd.c b/src/gen9_mfd.c
index 2d8ed7d..e9afb22 100644
--- a/src/gen9_mfd.c
+++ b/src/gen9_mfd.c
@@ -982,23 +982,44 @@ out:
 #define VP9_PROB_BUFFER_RESTORED_SECNE_2    2
 #define VP9_PROB_BUFFER_RESTORED_SECNE_MAX    (VP9_PROB_BUFFER_RESTORED_SECNE_2 + 1)
 
-static void vp9_update_segmentId_buffer(VADriverContextP ctx,
+#define ALLOC_MV_BUFFER(gen_buffer, string, size,width,height)  \
+    do {                                                        \
+        dri_bo_unreference(gen_buffer->bo);                     \
+        gen_buffer->bo = dri_bo_alloc(i965->intel.bufmgr,       \
+                                      string,                   \
+                                      size,                     \
+                                      0x1000);                  \
+        assert(gen_buffer->bo);                                 \
+        gen_buffer->frame_width  = width ;                      \
+        gen_buffer->frame_height = height;                      \
+    } while (0)
+
+static void
+vp9_update_segmentId_buffer(VADriverContextP ctx,
                           struct decode_state *decode_state,
-                          struct gen9_hcpd_context *gen9_hcpd_context, uint8_t isScaling)
+                          struct gen9_hcpd_context *gen9_hcpd_context)
 {
+    struct i965_driver_data *i965 = i965_driver_data(ctx);
     VADecPictureParameterBufferVP9 *pic_param;
 
+    int size = 0;
+    int is_scaling = 0;
     assert(decode_state->pic_param && decode_state->pic_param->buffer);
     pic_param = (VADecPictureParameterBufferVP9 *)decode_state->pic_param->buffer;
 
-    int size = 0;
+    size = gen9_hcpd_context->picture_width_in_ctbs * gen9_hcpd_context->picture_height_in_ctbs * 1 ;
+    size <<= 6;
+    if (gen9_hcpd_context->vp9_segment_id_buffer.bo == NULL || pic_param->frame_width > gen9_hcpd_context->last_frame.frame_width || pic_param->frame_height > gen9_hcpd_context->last_frame.frame_height)
+    {
+        ALLOC_GEN_BUFFER((&gen9_hcpd_context->vp9_segment_id_buffer), "vp9 segment id buffer", size);
+    }
+
+    is_scaling = (pic_param->frame_width != gen9_hcpd_context->last_frame.frame_width) || (pic_param->frame_height != gen9_hcpd_context->last_frame.frame_height);
 
     if((pic_param->pic_fields.bits.frame_type == HCP_VP9_KEY_FRAME) ||
         pic_param->pic_fields.bits.error_resilient_mode ||
-        pic_param->pic_fields.bits.intra_only || isScaling) {
+        pic_param->pic_fields.bits.intra_only || is_scaling) {
 
-        size = (gen9_hcpd_context->picture_width_in_min_cb_minus1+2)*(gen9_hcpd_context->picture_height_in_min_cb_minus1 + 2) * 1;
-        size<<=6;
         //VP9 Segment ID buffer needs to be zero
         dri_bo_map(gen9_hcpd_context->vp9_segment_id_buffer.bo,1);
         memset((unsigned char *)gen9_hcpd_context->vp9_segment_id_buffer.bo->virtual,0, size);
@@ -1006,6 +1027,31 @@ static void vp9_update_segmentId_buffer(VADriverContextP ctx,
     }
 }
 
+static void
+vp9_update_mv_temporal_buffer(VADriverContextP ctx,
+                          struct decode_state *decode_state,
+                          struct gen9_hcpd_context *gen9_hcpd_context)
+{
+    struct i965_driver_data *i965 = i965_driver_data(ctx);
+    VADecPictureParameterBufferVP9 *pic_param;
+    int size = 0;
+
+    assert(decode_state->pic_param && decode_state->pic_param->buffer);
+    pic_param = (VADecPictureParameterBufferVP9 *)decode_state->pic_param->buffer;
+
+    size = gen9_hcpd_context->picture_width_in_ctbs * gen9_hcpd_context->picture_height_in_ctbs * 9 ;
+    size <<= 6; //CL aligned
+    if (gen9_hcpd_context->vp9_mv_temporal_buffer_curr.bo == NULL || pic_param->frame_width > gen9_hcpd_context->vp9_mv_temporal_buffer_curr.frame_width || pic_param->frame_height > gen9_hcpd_context->vp9_mv_temporal_buffer_curr.frame_height)
+    {
+        ALLOC_MV_BUFFER((&gen9_hcpd_context->vp9_mv_temporal_buffer_curr), "vp9 curr mv temporal buffer", size,pic_param->frame_width,pic_param->frame_height);
+    }
+    if (gen9_hcpd_context->vp9_mv_temporal_buffer_last.bo == NULL)
+    {
+        ALLOC_MV_BUFFER((&gen9_hcpd_context->vp9_mv_temporal_buffer_last), "vp9 last mv temporal buffer", size,pic_param->frame_width,pic_param->frame_height);
+    }
+
+}
+
 static void
 vp9_gen_default_probabilities(VADriverContextP ctx, struct gen9_hcpd_context *gen9_hcpd_context)
 {
@@ -1103,7 +1149,7 @@ vp9_update_probabilities(VADriverContextP ctx,
         }
     }else if(gen9_hcpd_context->last_frame.prob_buffer_saved_flag == VP9_PROB_BUFFER_SAVED_SECNE_2)
     {
-        if((pic_param->pic_fields.bits.frame_type == HCP_VP9_KEY_FRAME) ||pic_param->pic_fields.bits.intra_only|pic_param->pic_fields.bits.error_resilient_mode)
+        if((pic_param->pic_fields.bits.frame_type == HCP_VP9_KEY_FRAME) ||pic_param->pic_fields.bits.intra_only||pic_param->pic_fields.bits.error_resilient_mode)
         {
             temp_frame_ctx_id = 0;
         }
@@ -1130,7 +1176,7 @@ vp9_update_probabilities(VADriverContextP ctx,
         }
     }
     //first part buffer update: Case 1)Reset all 4 probablity buffers
-   if((pic_param->pic_fields.bits.frame_type == HCP_VP9_KEY_FRAME) ||pic_param->pic_fields.bits.intra_only|pic_param->pic_fields.bits.error_resilient_mode)
+   if((pic_param->pic_fields.bits.frame_type == HCP_VP9_KEY_FRAME) ||pic_param->pic_fields.bits.intra_only||pic_param->pic_fields.bits.error_resilient_mode)
     {
         if((pic_param->pic_fields.bits.frame_type == HCP_VP9_KEY_FRAME) ||
             (pic_param->pic_fields.bits.reset_frame_context == 3)||
@@ -1265,9 +1311,7 @@ gen9_hcpd_init_vp9_surface(VADriverContextP ctx,
                             struct object_surface *obj_surface,
                             struct gen9_hcpd_context *gen9_hcpd_context)
 {
-    struct i965_driver_data *i965 = i965_driver_data(ctx);
     GenVP9Surface *gen9_vp9_surface;
-    uint32_t size=0;
 
     if (!obj_surface)
         return;
@@ -1282,16 +1326,6 @@ gen9_hcpd_init_vp9_surface(VADriverContextP ctx,
         obj_surface->private_data = gen9_vp9_surface;
     }
 
-    //Super block size in VP9 is 64x64, size in SBs
-    size = gen9_hcpd_context->picture_width_in_ctbs * gen9_hcpd_context->picture_height_in_ctbs * 9 ;
-    size<<=6; //CL aligned
-
-    if (gen9_vp9_surface->motion_vector_temporal_bo == NULL) {
-        gen9_vp9_surface->motion_vector_temporal_bo = dri_bo_alloc(i965->intel.bufmgr,
-                                                                   "current motion vector temporal buffer",
-                                                                    size,
-                                                                    0x1000);
-    }
     gen9_vp9_surface->frame_width  = pic_param->frame_width;
     gen9_vp9_surface->frame_height = pic_param->frame_height;
 
@@ -1374,10 +1408,6 @@ gen9_hcpd_vp9_decode_init(VADriverContextP ctx,
     size<<=6;
     ALLOC_GEN_BUFFER((&gen9_hcpd_context->vp9_probability_buffer), "vp9 probability buffer", size);
 
-    size = (gen9_hcpd_context->picture_width_in_min_cb_minus1+2)*(gen9_hcpd_context->picture_height_in_min_cb_minus1 + 2) * 1;
-    size<<=6;
-    ALLOC_GEN_BUFFER((&gen9_hcpd_context->vp9_segment_id_buffer), "vp9 segment id buffer", size);
-
     gen9_hcpd_context->first_inter_slice_collocated_ref_idx = 0;
     gen9_hcpd_context->first_inter_slice_collocated_from_l0_flag = 0;
     gen9_hcpd_context->first_inter_slice_valid = 0;
@@ -1451,7 +1481,6 @@ gen9_hcpd_vp9_pipe_buf_addr_state(VADriverContextP ctx,
 {
     struct intel_batchbuffer *batch = gen9_hcpd_context->base.batch;
     struct object_surface *obj_surface;
-    GenVP9Surface *gen9_vp9_surface;
     int i=0;
 
     BEGIN_BCS_BATCH(batch, 95);
@@ -1460,8 +1489,6 @@ gen9_hcpd_vp9_pipe_buf_addr_state(VADriverContextP ctx,
 
     obj_surface = decode_state->render_object;
     assert(obj_surface && obj_surface->bo);
-    gen9_vp9_surface = obj_surface->private_data;
-    assert(gen9_vp9_surface && gen9_vp9_surface->motion_vector_temporal_bo);
 
     OUT_BUFFER_MA_TARGET(obj_surface->bo); /* DW 1..3 */
     OUT_BUFFER_MA_TARGET(gen9_hcpd_context->deblocking_filter_line_buffer.bo);/* DW 4..6 */
@@ -1473,7 +1500,7 @@ gen9_hcpd_vp9_pipe_buf_addr_state(VADriverContextP ctx,
     OUT_BUFFER_MA_TARGET(NULL);    /* DW 22..24, ignore for VP9 */
     OUT_BUFFER_MA_TARGET(NULL);    /* DW 25..27, ignore for VP9 */
     OUT_BUFFER_MA_TARGET(NULL);    /* DW 28..30, ignore for VP9 */
-    OUT_BUFFER_MA_TARGET(gen9_vp9_surface->motion_vector_temporal_bo); /* DW 31..33 */
+    OUT_BUFFER_MA_TARGET(gen9_hcpd_context->vp9_mv_temporal_buffer_curr.bo); /* DW 31..33 */
 
     OUT_BUFFER_MA_TARGET(NULL); /* DW 34..36, reserved */
 
@@ -1503,7 +1530,7 @@ gen9_hcpd_vp9_pipe_buf_addr_state(VADriverContextP ctx,
     /* DW 66..81 - for 8 Collocated motion vectors */
     for (i = 0; i < 1; i++)
     {
-        OUT_BUFFER_NMA_REFERENCE(gen9_hcpd_context->last_frame.mv_temporal_buffer_bo);
+        OUT_BUFFER_NMA_REFERENCE(gen9_hcpd_context->vp9_mv_temporal_buffer_last.bo);
     }
     for (; i < ARRAY_ELEMS(gen9_hcpd_context->reference_surfaces); i++)
     {
@@ -1518,7 +1545,6 @@ gen9_hcpd_vp9_pipe_buf_addr_state(VADriverContextP ctx,
     OUT_BUFFER_MA_TARGET(gen9_hcpd_context->hvd_tile_rowstore_buffer.bo);/* DW 92..94, VP9 HVD Tile Rowstore buffer */
 
     ADVANCE_BCS_BATCH(batch);
-    gen9_hcpd_context->last_frame.mv_temporal_buffer_bo = gen9_vp9_surface->motion_vector_temporal_bo;
 }
 
 static inline int
@@ -1719,16 +1745,25 @@ gen9_hcpd_vp9_segment_state(VADriverContextP ctx,
                   seg_param->segment_flags.fields.segment_reference_enabled << 3 |
                   seg_param->segment_flags.fields.segment_reference << 1 |
                   seg_param->segment_flags.fields.segment_reference_skipped <<0 ); /* DW 2 */
-    OUT_BCS_BATCH(batch,
-                  seg_param->filter_level[1][1] << 24    | //FilterLevelRef1Mode1
-                  seg_param->filter_level[1][0] << 16    | //FilterLevelRef1Mode0
-                  seg_param->filter_level[0][1] << 8     | //FilterLevelRef0Mode1
-                  seg_param->filter_level[0][0] << 0 );     //FilterLevelRef0Mode0 /* DW 3 */
-    OUT_BCS_BATCH(batch,
-                  seg_param->filter_level[3][1] << 24    | //FilterLevelRef3Mode1
-                  seg_param->filter_level[3][0] << 16    | //FilterLevelRef3Mode0
-                  seg_param->filter_level[2][1] << 8     | //FilterLevelRef2Mode1
-                  seg_param->filter_level[2][0] << 0 );    //FilterLevelRef2Mode0 /* DW 4 */
+    if(pic_param->filter_level)
+    {
+        OUT_BCS_BATCH(batch,
+            seg_param->filter_level[1][1] << 24    | //FilterLevelRef1Mode1
+            seg_param->filter_level[1][0] << 16    | //FilterLevelRef1Mode0
+            seg_param->filter_level[0][1] << 8     | //FilterLevelRef0Mode1
+            seg_param->filter_level[0][0] << 0 );     //FilterLevelRef0Mode0 /* DW 3 */
+        OUT_BCS_BATCH(batch,
+            seg_param->filter_level[3][1] << 24    | //FilterLevelRef3Mode1
+            seg_param->filter_level[3][0] << 16    | //FilterLevelRef3Mode0
+            seg_param->filter_level[2][1] << 8     | //FilterLevelRef2Mode1
+            seg_param->filter_level[2][0] << 0 );    //FilterLevelRef2Mode0 /* DW 4 */
+    }else
+    {
+        OUT_BCS_BATCH(batch,
+            0 );      /* DW 3 */
+        OUT_BCS_BATCH(batch,
+            0 );      /* DW 4 */
+    }
     OUT_BCS_BATCH(batch,
                   seg_param->luma_ac_quant_scale << 16   |
                   seg_param->luma_dc_quant_scale << 0 );    /* DW 5 */
@@ -1766,39 +1801,35 @@ gen9_hcpd_vp9_decode_picture(VADriverContextP ctx,
                               struct decode_state *decode_state,
                               struct gen9_hcpd_context *gen9_hcpd_context)
 {
-    VAStatus vaStatus;
+    VAStatus vaStatus = VA_STATUS_SUCCESS;
     struct i965_driver_data *i965 = i965_driver_data(ctx);
     struct intel_batchbuffer *batch = gen9_hcpd_context->base.batch;
     VADecPictureParameterBufferVP9 *pic_param;
     VASliceParameterBufferVP9 *slice_param;
     dri_bo *slice_data_bo;
-    int i = 0, num_segments=0, isScaling=0;
-    struct object_surface *obj_surface;
-    GenVP9Surface *gen9_vp9_surface;
-    vaStatus = gen9_hcpd_vp9_decode_init(ctx, decode_state, gen9_hcpd_context);
-
-    if (vaStatus != VA_STATUS_SUCCESS)
-        goto out;
+    dri_bo *tmp_bo;
+    uint16_t tmp;
+    int i = 0, num_segments=0;
 
     assert(decode_state->pic_param && decode_state->pic_param->buffer);
+    assert(decode_state->slice_params && decode_state->slice_params[0]->buffer);
+    slice_param = (VASliceParameterBufferVP9 *)decode_state->slice_params[0]->buffer;
     pic_param = (VADecPictureParameterBufferVP9 *)decode_state->pic_param->buffer;
 
-    //****And set the isScaling value accordingly******
-    isScaling = 0;
-    for(i = 0; i < 3; i++)
+    if(slice_param->slice_data_size == 1)
     {
-        obj_surface = gen9_hcpd_context->reference_surfaces[i].obj_surface;
-        gen9_vp9_surface = NULL;
-        if (obj_surface && obj_surface->private_data)
-        {
-            gen9_vp9_surface = obj_surface->private_data;
-            isScaling |= (gen9_vp9_surface->frame_width == pic_param->frame_width &&
-                gen9_vp9_surface->frame_height == pic_param->frame_height)? 0:1;
-        }
+        goto out;
     }
 
+    vaStatus = gen9_hcpd_vp9_decode_init(ctx, decode_state, gen9_hcpd_context);
+
+    if (vaStatus != VA_STATUS_SUCCESS)
+        goto out;
+
     //Update segment id buffer if needed
-    vp9_update_segmentId_buffer(ctx, decode_state, gen9_hcpd_context, isScaling);
+    vp9_update_segmentId_buffer(ctx, decode_state, gen9_hcpd_context);
+    //Update mv buffer if needed
+    vp9_update_mv_temporal_buffer(ctx, decode_state, gen9_hcpd_context);
     //Update probability buffer if needed
     vp9_update_probabilities(ctx, decode_state, gen9_hcpd_context);
 
@@ -1813,8 +1844,6 @@ gen9_hcpd_vp9_decode_picture(VADriverContextP ctx,
     gen9_hcpd_vp9_surface_state(ctx, decode_state, gen9_hcpd_context);
 
     //Only one VASliceParameterBufferVP9 should be sent per frame
-    assert(decode_state->slice_params && decode_state->slice_params[0]->buffer);
-    slice_param = (VASliceParameterBufferVP9 *)decode_state->slice_params[0]->buffer;
     slice_data_bo = decode_state->slice_datas[0]->bo;
 
     gen9_hcpd_ind_obj_base_addr_state(ctx, slice_data_bo, gen9_hcpd_context);
@@ -1836,6 +1865,9 @@ gen9_hcpd_vp9_decode_picture(VADriverContextP ctx,
 
     gen9_hcpd_vp9_bsd_object(ctx, pic_param, slice_param, gen9_hcpd_context);
 
+    intel_batchbuffer_end_atomic(batch);
+    intel_batchbuffer_flush(batch);
+
     // keep track of the last frame status
     gen9_hcpd_context->last_frame.frame_width = pic_param->frame_width;
     gen9_hcpd_context->last_frame.frame_height = pic_param->frame_height;
@@ -1845,11 +1877,23 @@ gen9_hcpd_vp9_decode_picture(VADriverContextP ctx,
     gen9_hcpd_context->last_frame.frame_context_idx = pic_param->pic_fields.bits.frame_context_idx;
     gen9_hcpd_context->last_frame.intra_only = pic_param->pic_fields.bits.intra_only;
 
-    // update prob buffer to vp9_fc;
+    // switch mv buffer
+    if(pic_param->pic_fields.bits.frame_type != HCP_VP9_KEY_FRAME)
+    {
+        tmp_bo = gen9_hcpd_context->vp9_mv_temporal_buffer_last.bo;
+        gen9_hcpd_context->vp9_mv_temporal_buffer_last.bo = gen9_hcpd_context->vp9_mv_temporal_buffer_curr.bo;
+        gen9_hcpd_context->vp9_mv_temporal_buffer_curr.bo = tmp_bo;
 
-    intel_batchbuffer_end_atomic(batch);
-    intel_batchbuffer_flush(batch);
+        tmp = gen9_hcpd_context->vp9_mv_temporal_buffer_last.frame_width;
+        gen9_hcpd_context->vp9_mv_temporal_buffer_last.frame_width = gen9_hcpd_context->vp9_mv_temporal_buffer_curr.frame_width;
+        gen9_hcpd_context->vp9_mv_temporal_buffer_curr.frame_width = tmp;
+
+        tmp = gen9_hcpd_context->vp9_mv_temporal_buffer_last.frame_height;
+        gen9_hcpd_context->vp9_mv_temporal_buffer_last.frame_height = gen9_hcpd_context->vp9_mv_temporal_buffer_curr.frame_height;
+        gen9_hcpd_context->vp9_mv_temporal_buffer_curr.frame_height = tmp;
 
+
+    }
     //update vp9_frame_ctx according to frame_context_id
     if (pic_param->pic_fields.bits.refresh_frame_context)
     {
@@ -1920,6 +1964,8 @@ gen9_hcpd_context_destroy(void *hw_context)
     FREE_GEN_BUFFER((&gen9_hcpd_context->hvd_tile_rowstore_buffer));
     FREE_GEN_BUFFER((&gen9_hcpd_context->vp9_probability_buffer));
     FREE_GEN_BUFFER((&gen9_hcpd_context->vp9_segment_id_buffer));
+    dri_bo_unreference(gen9_hcpd_context->vp9_mv_temporal_buffer_curr.bo);
+    dri_bo_unreference(gen9_hcpd_context->vp9_mv_temporal_buffer_last.bo);
 
     intel_batchbuffer_free(gen9_hcpd_context->base.batch);
     free(gen9_hcpd_context);
@@ -1936,17 +1982,19 @@ static void
 gen9_hcpd_vp9_context_init(VADriverContextP ctx,
                             struct gen9_hcpd_context *gen9_hcpd_context)
 {
-    int default_value = 255;
 
     gen9_hcpd_context->last_frame.frame_height  = 0;
     gen9_hcpd_context->last_frame.show_frame    = 0;
     gen9_hcpd_context->last_frame.frame_type    = 0;
-    gen9_hcpd_context->last_frame.refresh_frame_context = default_value;
-    gen9_hcpd_context->last_frame.frame_context_idx = default_value;
+    gen9_hcpd_context->last_frame.refresh_frame_context = 0;
+    gen9_hcpd_context->last_frame.frame_context_idx = 0;
     gen9_hcpd_context->last_frame.intra_only = 0;
     gen9_hcpd_context->last_frame.prob_buffer_saved_flag = 0;
     gen9_hcpd_context->last_frame.prob_buffer_restored_flag = 0;
-    gen9_hcpd_context->last_frame.mv_temporal_buffer_bo = NULL;
+
+    //Super block in VP9 is 64x64
+    gen9_hcpd_context->ctb_size = 64;
+    gen9_hcpd_context->min_cb_size = 8; //Min block size is 8
 
     vp9_gen_default_probabilities(ctx, gen9_hcpd_context);
 }
diff --git a/src/gen9_mfd.h b/src/gen9_mfd.h
index c266dd4..a91a84a 100644
--- a/src/gen9_mfd.h
+++ b/src/gen9_mfd.h
@@ -49,9 +49,15 @@ typedef struct vp9_frame_status
     uint8_t intra_only;
     uint8_t prob_buffer_saved_flag;
     uint8_t prob_buffer_restored_flag;
-    dri_bo * mv_temporal_buffer_bo;
 }vp9_last_frame_status;
 
+typedef struct vp9_mv_temporal_buffer
+{
+    dri_bo *bo;
+    uint16_t frame_width;
+    uint16_t frame_height;
+}VP9_MV_BUFFER;
+
 struct gen9_hcpd_context
 {
     struct hw_context base;
@@ -84,6 +90,8 @@ struct gen9_hcpd_context
     GenBuffer hvd_tile_rowstore_buffer;
     GenBuffer vp9_probability_buffer;
     GenBuffer vp9_segment_id_buffer;
+    VP9_MV_BUFFER vp9_mv_temporal_buffer_curr;
+    VP9_MV_BUFFER vp9_mv_temporal_buffer_last;
 
     unsigned short first_inter_slice_collocated_ref_idx;
     unsigned short first_inter_slice_collocated_from_l0_flag;
diff --git a/src/intel_media_common.c b/src/intel_media_common.c
index 5fe9fc5..d6771c8 100644
--- a/src/intel_media_common.c
+++ b/src/intel_media_common.c
@@ -123,9 +123,6 @@ void gen_free_vp9_surface(void **data)
         return;
     }
 
-    dri_bo_unreference(vp9_surface->motion_vector_temporal_bo);
-    vp9_surface->motion_vector_temporal_bo = NULL;
-
     free(vp9_surface);
     *data = NULL;
 
-- 
cgit v1.2.3


From 10c4cdd103f730a9e07ffcf0f940e8f63ee5738d Mon Sep 17 00:00:00 2001
From: "peng.chen" <peng.c.chen@intel.com>
Date: Thu, 7 Jan 2016 08:54:34 +0800
Subject: only re-caculate surface width&height for tiled surface

fix Bug 93499 - daf8f6c762874 introduced display corruption on i3 330M
https://bugs.freedesktop.org/show_bug.cgi?id=93499

Signed-off-by: peng.chen <peng.c.chen@intel.com>
---
 src/i965_drv_video.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/src/i965_drv_video.c b/src/i965_drv_video.c
index 7b7bdf6..db82b27 100644
--- a/src/i965_drv_video.c
+++ b/src/i965_drv_video.c
@@ -3819,22 +3819,22 @@ i965_check_alloc_surface_bo(VADriverContextP ctx,
 
     int bpp_1stplane = bpp_1stplane_by_fourcc(fourcc);
 
-    if (obj_surface->user_h_stride_set) {
-        ASSERT_RET(IS_ALIGNED(obj_surface->width, 128), VA_STATUS_ERROR_INVALID_PARAMETER);
-    } else
-        obj_surface->width = ALIGN(obj_surface->orig_width * bpp_1stplane, 128);
-
-    if (obj_surface->user_v_stride_set) {
-        ASSERT_RET(IS_ALIGNED(obj_surface->height, 32), VA_STATUS_ERROR_INVALID_PARAMETER);
-    } else
-        obj_surface->height = ALIGN(obj_surface->orig_height, 32);
-
     if ((tiled && !obj_surface->user_disable_tiling)) {
         ASSERT_RET(fourcc != VA_FOURCC_I420 &&
                fourcc != VA_FOURCC_IYUV &&
                fourcc != VA_FOURCC_YV12,
                VA_STATUS_ERROR_UNSUPPORTED_RT_FORMAT);
 
+        if (obj_surface->user_h_stride_set) {
+           ASSERT_RET(IS_ALIGNED(obj_surface->width, 128), VA_STATUS_ERROR_INVALID_PARAMETER);
+        } else
+          obj_surface->width = ALIGN(obj_surface->orig_width * bpp_1stplane, 128);
+
+        if (obj_surface->user_v_stride_set) {
+          ASSERT_RET(IS_ALIGNED(obj_surface->height, 32), VA_STATUS_ERROR_INVALID_PARAMETER);
+        }else
+          obj_surface->height = ALIGN(obj_surface->orig_height, 32);
+
         region_height = obj_surface->height;
 
         switch (fourcc) {
-- 
cgit v1.2.3


From d9eb6b2063418226242e4e76aa7929fa63030bc6 Mon Sep 17 00:00:00 2001
From: "peng.chen" <peng.c.chen@intel.com>
Date: Wed, 13 Jan 2016 15:31:37 +0800
Subject: VPP P010(10bits) enabling

v2:
1, remove VPP P016 related code
2, optimize NV12->P010
3, enable IECP if all DI&DN are disabled

v1:
initial

Signed-off-by: peng.chen <peng.c.chen@intel.com>
---
 src/gen75_picture_process.c | 266 +++++++++++++++++++++++++++++++++++---------
 src/gen75_vpp_vebox.c       |  21 +++-
 src/i965_device_info.c      |   2 +-
 src/i965_drv_video.c        |  17 +++
 src/i965_drv_video.h        |   1 +
 5 files changed, 251 insertions(+), 56 deletions(-)

diff --git a/src/gen75_picture_process.c b/src/gen75_picture_process.c
index ed50532..802452b 100644
--- a/src/gen75_picture_process.c
+++ b/src/gen75_picture_process.c
@@ -28,6 +28,7 @@
 #include <stdio.h>
 #include <stdlib.h>
 #include <assert.h>
+#include <string.h>
 
 #include "intel_batchbuffer.h"
 #include "intel_driver.h"
@@ -123,6 +124,15 @@ gen75_proc_picture(VADriverContextP ctx,
              (VAProcPipelineParameterBuffer *)proc_st->pipeline_param->buffer;
     struct object_surface *obj_dst_surf = NULL;
     struct object_surface *obj_src_surf = NULL;
+
+    VAProcPipelineParameterBuffer pipeline_param2;
+    struct object_surface *stage1_dst_surf = NULL;
+    struct object_surface *stage2_dst_surf = NULL;
+    VARectangle src_rect, dst_rect;
+    VASurfaceID tmp_surfaces[2];
+    VASurfaceID out_surface_id1 = VA_INVALID_ID, out_surface_id2 = VA_INVALID_ID;
+    int num_tmp_surfaces = 0;
+
     VAStatus status;
 
     proc_ctx->pipeline_param = pipeline_param;
@@ -168,69 +178,221 @@ gen75_proc_picture(VADriverContextP ctx,
     proc_ctx->surface_pipeline_input_object = obj_src_surf;
     assert(pipeline_param->num_filters <= 4);
 
+    int vpp_stage1 = 0, vpp_stage2 = 1, vpp_stage3 = 0;
+
+    if (pipeline_param->surface_region) {
+        src_rect.x = pipeline_param->surface_region->x;
+        src_rect.y = pipeline_param->surface_region->y;
+        src_rect.width = pipeline_param->surface_region->width;
+        src_rect.height = pipeline_param->surface_region->height;
+    } else {
+        src_rect.x = 0;
+        src_rect.y = 0;
+        src_rect.width = obj_src_surf->orig_width;
+        src_rect.height = obj_src_surf->orig_height;
+    }
+
+    if (pipeline_param->output_region) {
+        dst_rect.x = pipeline_param->output_region->x;
+        dst_rect.y = pipeline_param->output_region->y;
+        dst_rect.width = pipeline_param->output_region->width;
+        dst_rect.height = pipeline_param->output_region->height;
+    } else {
+        dst_rect.x = 0;
+        dst_rect.y = 0;
+        dst_rect.width = obj_dst_surf->orig_width;
+        dst_rect.height = obj_dst_surf->orig_height;
+    }
+
+    if(obj_src_surf->fourcc == VA_FOURCC_P010) {
+        vpp_stage1 = 1;
+        vpp_stage2 = 0;
+        vpp_stage3 = 0;
+        if(pipeline_param->num_filters == 0 || pipeline_param->filters == NULL) {
+            if(src_rect.x != dst_rect.x ||
+                src_rect.y != dst_rect.y ||
+                src_rect.width != dst_rect.width ||
+                src_rect.height != dst_rect.height)
+              vpp_stage2 = 1;
+
+            if(obj_dst_surf->fourcc != VA_FOURCC_NV12 &&
+                obj_dst_surf->fourcc != VA_FOURCC_P010)
+              vpp_stage2 = 1;
+        }
+        else
+          vpp_stage2 = 1;
+
+        if(vpp_stage2 == 1) {
+          if(obj_dst_surf->fourcc == VA_FOURCC_P010)
+            vpp_stage3 = 1;
+        }
+    }
+    else if(obj_dst_surf->fourcc == VA_FOURCC_P010) {
+        vpp_stage2 = 1;
+        vpp_stage3 = 1;
+
+        if((obj_src_surf->fourcc == VA_FOURCC_NV12) &&
+            (pipeline_param->num_filters == 0 || pipeline_param->filters == NULL)) {
+            if((src_rect.x == dst_rect.x) &&
+                (src_rect.y == dst_rect.y) &&
+                (src_rect.width == dst_rect.width) &&
+                (src_rect.height == dst_rect.height))
+                vpp_stage2 = 0;
+        }
+    }
+
+    if(vpp_stage1 == 1){
+        memset((void *)&pipeline_param2, 0, sizeof(pipeline_param2));
+        pipeline_param2.surface = pipeline_param->surface;
+        pipeline_param2.surface_region = &src_rect;
+        pipeline_param2.output_region = &src_rect;
+        pipeline_param2.filter_flags = 0;
+        pipeline_param2.num_filters  = 0;
+
+        proc_ctx->pipeline_param = &pipeline_param2;
+
+        if(vpp_stage2 == 1) {
+            status = i965_CreateSurfaces(ctx,
+                                         obj_src_surf->orig_width,
+                                         obj_src_surf->orig_height,
+                                         VA_RT_FORMAT_YUV420,
+                                         1,
+                                         &out_surface_id1);
+            assert(status == VA_STATUS_SUCCESS);
+            tmp_surfaces[num_tmp_surfaces++] = out_surface_id1;
+            stage1_dst_surf = SURFACE(out_surface_id1);
+            assert(stage1_dst_surf);
+            i965_check_alloc_surface_bo(ctx, stage1_dst_surf, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
+
+            proc_ctx->surface_render_output_object = stage1_dst_surf;
+        }
+
+        gen75_vpp_vebox(ctx, proc_ctx);
+    }
+
+    if((vpp_stage3 == 1) && (vpp_stage2 == 1)) {
+        status = i965_CreateSurfaces(ctx,
+                                     obj_dst_surf->orig_width,
+                                     obj_dst_surf->orig_height,
+                                     VA_RT_FORMAT_YUV420,
+                                     1,
+                                     &out_surface_id2);
+        assert(status == VA_STATUS_SUCCESS);
+        tmp_surfaces[num_tmp_surfaces++] = out_surface_id2;
+        stage2_dst_surf = SURFACE(out_surface_id2);
+        assert(stage2_dst_surf);
+        i965_check_alloc_surface_bo(ctx, stage2_dst_surf, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
+    }
+
     VABufferID *filter_id = (VABufferID*) pipeline_param->filters;
- 
-    if(pipeline_param->num_filters == 0 || pipeline_param->filters == NULL ){
-        /* implicity surface format coversion and scaling */
-        gen75_vpp_fmt_cvt(ctx, profile, codec_state, hw_context);
-    }else if(pipeline_param->num_filters == 1) {
-       struct object_buffer * obj_buf = BUFFER((*filter_id) + 0);
-
-       assert(obj_buf && obj_buf->buffer_store && obj_buf->buffer_store->buffer);
-       
-       if (!obj_buf ||
-           !obj_buf->buffer_store ||
-           !obj_buf->buffer_store->buffer) {
-           status = VA_STATUS_ERROR_INVALID_FILTER_CHAIN;
-           goto error;
-       }
-
-       VAProcFilterParameterBuffer* filter =
-           (VAProcFilterParameterBuffer*)obj_buf-> buffer_store->buffer;
-
-       if (filter->type == VAProcFilterNoiseReduction         ||
-           filter->type == VAProcFilterDeinterlacing          ||
-           filter->type == VAProcFilterSkinToneEnhancement    ||
-           filter->type == VAProcFilterColorBalance){
-           gen75_vpp_vebox(ctx, proc_ctx);
-       }else if(filter->type == VAProcFilterSharpening){
-           if (obj_src_surf->fourcc != VA_FOURCC_NV12 ||
-               obj_dst_surf->fourcc != VA_FOURCC_NV12) {
-               status = VA_STATUS_ERROR_UNIMPLEMENTED;
+
+    if(vpp_stage2 == 1) {
+        if(stage1_dst_surf != NULL) {
+            proc_ctx->surface_pipeline_input_object = stage1_dst_surf;
+            proc_ctx->surface_render_output_object = obj_dst_surf;
+
+            pipeline_param->surface = out_surface_id1;
+        }
+
+        if(stage2_dst_surf != NULL) {
+            proc_ctx->surface_render_output_object = stage2_dst_surf;
+
+            proc_st->current_render_target = out_surface_id2;
+        }
+
+        proc_ctx->pipeline_param = pipeline_param;
+
+        if(pipeline_param->num_filters == 0 || pipeline_param->filters == NULL ){
+            /* implicity surface format coversion and scaling */
+
+            gen75_vpp_fmt_cvt(ctx, profile, codec_state, hw_context);
+        }else if(pipeline_param->num_filters == 1) {
+           struct object_buffer * obj_buf = BUFFER((*filter_id) + 0);
+
+           assert(obj_buf && obj_buf->buffer_store && obj_buf->buffer_store->buffer);
+
+           if (!obj_buf ||
+               !obj_buf->buffer_store ||
+               !obj_buf->buffer_store->buffer) {
+               status = VA_STATUS_ERROR_INVALID_FILTER_CHAIN;
                goto error;
            }
 
-           gen75_vpp_gpe(ctx, proc_ctx);
-       } 
-    }else if (pipeline_param->num_filters >= 2) {
-         unsigned int i = 0;
-         for (i = 0; i < pipeline_param->num_filters; i++){
-             struct object_buffer * obj_buf = BUFFER(pipeline_param->filters[i]);
-
-             if (!obj_buf ||
-                 !obj_buf->buffer_store ||
-                 !obj_buf->buffer_store->buffer) {
-                 status = VA_STATUS_ERROR_INVALID_FILTER_CHAIN;
-                 goto error;
+           VAProcFilterParameterBuffer* filter =
+               (VAProcFilterParameterBuffer*)obj_buf-> buffer_store->buffer;
+
+           if (filter->type == VAProcFilterNoiseReduction         ||
+               filter->type == VAProcFilterDeinterlacing          ||
+               filter->type == VAProcFilterSkinToneEnhancement    ||
+               filter->type == VAProcFilterColorBalance){
+               gen75_vpp_vebox(ctx, proc_ctx);
+           }else if(filter->type == VAProcFilterSharpening){
+               if (proc_ctx->surface_pipeline_input_object->fourcc != VA_FOURCC_NV12 ||
+                   proc_ctx->surface_render_output_object->fourcc != VA_FOURCC_NV12) {
+                   status = VA_STATUS_ERROR_UNIMPLEMENTED;
+                   goto error;
+               }
+
+               gen75_vpp_gpe(ctx, proc_ctx);
+           }
+        }else if (pipeline_param->num_filters >= 2) {
+             unsigned int i = 0;
+             for (i = 0; i < pipeline_param->num_filters; i++){
+                 struct object_buffer * obj_buf = BUFFER(pipeline_param->filters[i]);
+
+                 if (!obj_buf ||
+                     !obj_buf->buffer_store ||
+                     !obj_buf->buffer_store->buffer) {
+                     status = VA_STATUS_ERROR_INVALID_FILTER_CHAIN;
+                     goto error;
+                 }
+
+                 VAProcFilterParameterBuffer* filter =
+                     (VAProcFilterParameterBuffer*)obj_buf-> buffer_store->buffer;
+
+                 if (filter->type != VAProcFilterNoiseReduction       &&
+                     filter->type != VAProcFilterDeinterlacing        &&
+                     filter->type != VAProcFilterSkinToneEnhancement  &&
+                     filter->type != VAProcFilterColorBalance) {
+                     fprintf(stderr, "Do not support multiply filters outside vebox pipeline \n");
+                     assert(0);
+                 }
              }
+             gen75_vpp_vebox(ctx, proc_ctx);
+        }
+    }
 
-             VAProcFilterParameterBuffer* filter =
-                 (VAProcFilterParameterBuffer*)obj_buf-> buffer_store->buffer;
+    if(vpp_stage3 == 1)
+    {
+        if(vpp_stage2 == 1) {
+            memset(&pipeline_param2, 0, sizeof(pipeline_param2));
+            pipeline_param2.surface = out_surface_id2;
+            pipeline_param2.surface_region = &dst_rect;
+            pipeline_param2.output_region = &dst_rect;
+            pipeline_param2.filter_flags = 0;
+            pipeline_param2.num_filters  = 0;
+
+            proc_ctx->pipeline_param = &pipeline_param2;
+            proc_ctx->surface_pipeline_input_object = proc_ctx->surface_render_output_object;
+            proc_ctx->surface_render_output_object = obj_dst_surf;
+        }
+
+        gen75_vpp_vebox(ctx, proc_ctx);
+    }
 
-             if (filter->type != VAProcFilterNoiseReduction       &&
-                 filter->type != VAProcFilterDeinterlacing        &&
-                 filter->type != VAProcFilterSkinToneEnhancement  &&
-                 filter->type != VAProcFilterColorBalance) {
-                 fprintf(stderr, "Do not support multiply filters outside vebox pipeline \n");
-                 assert(0);
-             }
-         }
-         gen75_vpp_vebox(ctx, proc_ctx);
-    }     
+    if (num_tmp_surfaces)
+        i965_DestroySurfaces(ctx,
+                             tmp_surfaces,
+                             num_tmp_surfaces);
 
     return VA_STATUS_SUCCESS;
 
 error:
+    if (num_tmp_surfaces)
+        i965_DestroySurfaces(ctx,
+                             tmp_surfaces,
+                             num_tmp_surfaces);
+
     return status;
 }
 
diff --git a/src/gen75_vpp_vebox.c b/src/gen75_vpp_vebox.c
index 06c27f8..1b4232d 100644
--- a/src/gen75_vpp_vebox.c
+++ b/src/gen75_vpp_vebox.c
@@ -1408,7 +1408,9 @@ int hsw_veb_pre_format_convert(VADriverContextP ctx,
 
       } else if(obj_surf_input->fourcc ==  VA_FOURCC_AYUV ||
                 obj_surf_input->fourcc ==  VA_FOURCC_YUY2 ||
-                obj_surf_input->fourcc ==  VA_FOURCC_NV12){
+                obj_surf_input->fourcc ==  VA_FOURCC_NV12 ||
+                obj_surf_input->fourcc ==  VA_FOURCC_P010){
+
                 // nothing to do here
      } else {
            /* not support other format as input */ 
@@ -1447,7 +1449,9 @@ int hsw_veb_pre_format_convert(VADriverContextP ctx,
         proc_ctx->format_convert_flags |= POST_FORMAT_CONVERT;
     } else if(obj_surf_output->fourcc ==  VA_FOURCC_AYUV ||
               obj_surf_output->fourcc ==  VA_FOURCC_YUY2 ||
-              obj_surf_output->fourcc ==  VA_FOURCC_NV12){
+                obj_surf_input->fourcc ==  VA_FOURCC_NV12 ||
+                obj_surf_input->fourcc ==  VA_FOURCC_P010){
+
               /* Nothing to do here */
      } else {
            /* not support other format as input */ 
@@ -1602,6 +1606,11 @@ gen75_vebox_init_filter_params(VADriverContextP ctx,
     proc_ctx->is_first_frame = 0;
     proc_ctx->is_second_field = 0;
 
+    if(!proc_ctx->is_di_enabled && !proc_ctx->is_dn_enabled) {
+        // MUST enable IECP if all DI&DN are disabled
+        proc_ctx->is_iecp_enabled = 1;
+    }
+
     /* Check whether we are deinterlacing the second field */
     if (proc_ctx->is_di_enabled) {
         const VAProcFilterParameterBufferDeinterlacing * const deint_params =
@@ -2290,7 +2299,8 @@ void skl_veb_surface_state(VADriverContextP ctx, struct intel_vebox_context *pro
     assert(obj_surf->fourcc == VA_FOURCC_NV12 ||
            obj_surf->fourcc == VA_FOURCC_YUY2 ||
            obj_surf->fourcc == VA_FOURCC_AYUV ||
-           obj_surf->fourcc == VA_FOURCC_RGBA);
+           obj_surf->fourcc == VA_FOURCC_RGBA ||
+           obj_surf->fourcc == VA_FOURCC_P010);
 
     if (obj_surf->fourcc == VA_FOURCC_NV12) {
         surface_format = PLANAR_420_8;
@@ -2312,6 +2322,11 @@ void skl_veb_surface_state(VADriverContextP ctx, struct intel_vebox_context *pro
         surface_pitch = obj_surf->width * 4;
         is_uv_interleaved = 0;
         half_pitch_chroma = 0;
+    } else if (obj_surf->fourcc == VA_FOURCC_P010) {
+        surface_format = PLANAR_420_16;
+        surface_pitch = obj_surf->width;
+        is_uv_interleaved = 1;
+        half_pitch_chroma = 0;
     }
 
     derived_pitch = surface_pitch;
diff --git a/src/i965_device_info.c b/src/i965_device_info.c
index 4921922..b14fda9 100644
--- a/src/i965_device_info.c
+++ b/src/i965_device_info.c
@@ -401,6 +401,7 @@ static struct hw_codec_info bxt_hw_codec_info = {
     .has_hevc_encoding = 1,
     .has_hevc10_decoding = 1,
     .has_vp9_decoding = 1,
+    .has_vpp_p010 = 1,
 
     .num_filters = 5,
     .filters = {
@@ -412,7 +413,6 @@ static struct hw_codec_info bxt_hw_codec_info = {
     },
 };
 
-
 struct hw_codec_info *
 i965_get_codec_info(int devid)
 {
diff --git a/src/i965_drv_video.c b/src/i965_drv_video.c
index db82b27..cfdce2b 100644
--- a/src/i965_drv_video.c
+++ b/src/i965_drv_video.c
@@ -112,6 +112,9 @@
 #define HAS_HEVC10_DECODING(ctx)        ((ctx)->codec_info->has_hevc10_decoding && \
                                          (ctx)->intel.has_bsd)
 
+#define HAS_VPP_P010(ctx)        ((ctx)->codec_info->has_vpp_p010 && \
+                                         (ctx)->intel.has_bsd)
+
 static int get_sampling_from_fourcc(unsigned int fourcc);
 
 /* Check whether we are rendering to X11 (VA/X11 or VA/GLX API) */
@@ -878,6 +881,12 @@ i965_get_default_chroma_formats(VADriverContextP ctx, VAProfile profile,
         if (HAS_HEVC10_DECODING(i965) && entrypoint == VAEntrypointVLD)
             chroma_formats |= i965->codec_info->hevc_dec_chroma_formats;
         break;
+
+    case VAProfileNone:
+	if(HAS_VPP_P010(i965))
+            chroma_formats |= VA_RT_FORMAT_YUV420_10BPP;
+        break;
+
     default:
         break;
     }
@@ -5688,6 +5697,14 @@ i965_QuerySurfaceAttributes(VADriverContextP ctx,
                 attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE;
                 attribs[i].value.value.i = VA_FOURCC_YV16;
                 i++;
+
+                if(HAS_VPP_P010(i965)) {
+                  attribs[i].type = VASurfaceAttribPixelFormat;
+                  attribs[i].value.type = VAGenericValueTypeInteger;
+                  attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE;
+                  attribs[i].value.value.i = VA_FOURCC_P010;
+                  i++;
+                }
             }
         }
     }
diff --git a/src/i965_drv_video.h b/src/i965_drv_video.h
index bdb7512..36a9039 100644
--- a/src/i965_drv_video.h
+++ b/src/i965_drv_video.h
@@ -388,6 +388,7 @@ struct hw_codec_info
     unsigned int has_hevc_encoding:1;
     unsigned int has_hevc10_decoding:1;
     unsigned int has_vp9_decoding:1;
+    unsigned int has_vpp_p010:1;
 
     unsigned int num_filters;
     struct i965_filter filters[VAProcFilterCount];
-- 
cgit v1.2.3


From 2110b3a0bca6cecb42defd0b01d32530f5807b04 Mon Sep 17 00:00:00 2001
From: "peng.chen" <peng.c.chen@intel.com>
Date: Wed, 13 Jan 2016 15:34:11 +0800
Subject: P010(10bits) enabling in vaCreateImage(), vaGetImage(), vaPutImage()

1, don't support the conversion from NV12 or other 8bits formats to P010
2, don't support scaling for P010->P010

v2:
add GEN arch limitation for vebox_processing_simple()

v1:
initial

Signed-off-by: peng.chen <peng.c.chen@intel.com>
---
 src/gen8_post_processing.c |   7 ++
 src/i965_drv_video.c       |  10 +++
 src/i965_post_processing.c | 186 +++++++++++++++++++++++++++++++++++++++++++++
 src/i965_post_processing.h |   2 +
 4 files changed, 205 insertions(+)

diff --git a/src/gen8_post_processing.c b/src/gen8_post_processing.c
index 998e3c8..3c10960 100644
--- a/src/gen8_post_processing.c
+++ b/src/gen8_post_processing.c
@@ -42,6 +42,8 @@
 #include "i965_yuv_coefs.h"
 #include "intel_media.h"
 
+#include "gen75_picture_process.h"
+
 #define SURFACE_STATE_PADDED_SIZE               SURFACE_STATE_PADDED_SIZE_GEN8
 
 #define SURFACE_STATE_OFFSET(index)             (SURFACE_STATE_PADDED_SIZE * index)
@@ -1460,6 +1462,11 @@ static void
 gen8_post_processing_context_finalize(VADriverContextP ctx,
     struct i965_post_processing_context *pp_context)
 {
+    if(pp_context->vebox_proc_ctx){
+       gen75_vebox_context_destroy(ctx,pp_context->vebox_proc_ctx);
+       pp_context->vebox_proc_ctx = NULL;
+    }
+
     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
     pp_context->surface_state_binding_table.bo = NULL;
 
diff --git a/src/i965_drv_video.c b/src/i965_drv_video.c
index cfdce2b..cd616d7 100644
--- a/src/i965_drv_video.c
+++ b/src/i965_drv_video.c
@@ -319,6 +319,8 @@ i965_image_formats_map[I965_MAX_IMAGE_FORMATS + 1] = {
       { VA_FOURCC_RGBX, VA_LSB_FIRST, 32, 24, 0x000000ff, 0x0000ff00, 0x00ff0000 } },
     { I965_SURFACETYPE_RGBA,
       { VA_FOURCC_BGRX, VA_LSB_FIRST, 32, 24, 0x00ff0000, 0x0000ff00, 0x000000ff } },
+    { I965_SURFACETYPE_YUV,
+      { VA_FOURCC_P010, VA_LSB_FIRST, 24, } },
 };
 
 /* List of supported subpicture formats */
@@ -3768,6 +3770,14 @@ i965_CreateImage(VADriverContextP ctx,
         image->offsets[0] = 0;
         image->data_size  = size * 2;
         break;
+    case VA_FOURCC_P010:
+        image->num_planes = 2;
+        image->pitches[0] = awidth * 2;
+        image->offsets[0] = 0;
+        image->pitches[1] = awidth * 2;
+        image->offsets[1] = size * 2;
+        image->data_size  = size * 2 + 2 * size2 * 2;
+        break;
     default:
         goto error;
     }
diff --git a/src/i965_post_processing.c b/src/i965_post_processing.c
index ea35b36..969f84b 100755
--- a/src/i965_post_processing.c
+++ b/src/i965_post_processing.c
@@ -41,6 +41,8 @@
 #include "i965_yuv_coefs.h"
 #include "intel_media.h"
 
+#include "gen75_picture_process.h"
+
 extern VAStatus
 vpp_surface_convert(VADriverContextP ctx,
                     struct object_surface *src_obj_surf,
@@ -5296,6 +5298,183 @@ i965_image_pl1_processing(VADriverContextP ctx,
     return vaStatus;
 }
 
+// it only support NV12 and P010 for vebox proc ctx
+static struct object_surface *derive_surface(VADriverContextP ctx,
+                                             struct object_image *obj_image,
+                                             struct object_surface *obj_surface)
+{
+    VAImage * const image = &obj_image->image;
+
+    memset((void *)obj_surface, 0, sizeof(*obj_surface));
+    obj_surface->fourcc = image->format.fourcc;
+    obj_surface->orig_width = image->width;
+    obj_surface->orig_height = image->height;
+    obj_surface->width = image->pitches[0];
+    obj_surface->height = image->height;
+    obj_surface->y_cb_offset = image->offsets[1] / obj_surface->width;
+    obj_surface->y_cr_offset = obj_surface->y_cb_offset;
+    obj_surface->bo = obj_image->bo;
+    obj_surface->subsampling = SUBSAMPLE_YUV420;
+
+    return obj_surface;
+}
+
+static VAStatus
+vebox_processing_simple(VADriverContextP ctx,
+                        struct i965_post_processing_context *pp_context,
+                        struct object_surface *src_obj_surface,
+                        struct object_surface *dst_obj_surface,
+                        const VARectangle *rect)
+{
+    struct i965_driver_data *i965 = i965_driver_data(ctx);
+    VAProcPipelineParameterBuffer pipeline_param;
+    VAStatus status = VA_STATUS_ERROR_UNIMPLEMENTED;
+
+    if(pp_context->vebox_proc_ctx == NULL) {
+        pp_context->vebox_proc_ctx = gen75_vebox_context_init(ctx);
+    }
+
+    memset((void *)&pipeline_param, 0, sizeof(pipeline_param));
+    pipeline_param.surface_region = rect;
+    pipeline_param.output_region = rect;
+    pipeline_param.filter_flags = 0;
+    pipeline_param.num_filters  = 0;
+
+    pp_context->vebox_proc_ctx->pipeline_param = &pipeline_param;
+    pp_context->vebox_proc_ctx->surface_input_object = src_obj_surface;
+    pp_context->vebox_proc_ctx->surface_output_object = dst_obj_surface;
+
+    if (IS_GEN9(i965->intel.device_info))
+        status = gen9_vebox_process_picture(ctx, pp_context->vebox_proc_ctx);
+
+    return status;
+}
+
+static VAStatus
+i965_image_p010_processing(VADriverContextP ctx,
+                          const struct i965_surface *src_surface,
+                          const VARectangle *src_rect,
+                          struct i965_surface *dst_surface,
+                          const VARectangle *dst_rect)
+{
+#define HAS_VPP_P010(ctx)        ((ctx)->codec_info->has_vpp_p010 && \
+                                     (ctx)->intel.has_bsd)
+
+    struct i965_driver_data *i965 = i965_driver_data(ctx);
+    struct i965_post_processing_context *pp_context = i965->pp_context;
+    struct object_surface *src_obj_surface = NULL, *dst_obj_surface = NULL;
+    struct object_surface tmp_src_obj_surface, tmp_dst_obj_surface;
+    struct object_surface *tmp_surface = NULL;
+    VASurfaceID tmp_surface_id[3], out_surface_id = VA_INVALID_ID;
+    int num_tmp_surfaces = 0;
+    int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
+    VAStatus vaStatus = VA_STATUS_ERROR_UNIMPLEMENTED;
+    int vpp_post = 0;
+
+    if(HAS_VPP_P010(i965)) {
+        vpp_post = 0;
+        switch(fourcc) {
+        case VA_FOURCC_NV12:
+            if(src_rect->x != dst_rect->x ||
+                src_rect->y != dst_rect->y ||
+                src_rect->width != dst_rect->width ||
+                src_rect->height != dst_rect->height) {
+                vpp_post = 1;
+            }
+            break;
+        case VA_FOURCC_P010:
+            // don't support scaling while the fourcc of dst_surface is P010
+            if(src_rect->x != dst_rect->x ||
+                src_rect->y != dst_rect->y ||
+                src_rect->width != dst_rect->width ||
+                src_rect->height != dst_rect->height) {
+                vaStatus = VA_STATUS_ERROR_UNIMPLEMENTED;
+                goto EXIT;
+            }
+            break;
+        default:
+            vpp_post = 1;
+            break;
+        }
+
+        if(src_surface->type == I965_SURFACE_TYPE_IMAGE) {
+            src_obj_surface = derive_surface(ctx, (struct object_image *)src_surface->base,
+                                             &tmp_src_obj_surface);
+        }
+        else
+            src_obj_surface = (struct object_surface *)src_surface->base;
+
+        if(src_obj_surface == NULL) {
+            vaStatus = VA_STATUS_ERROR_ALLOCATION_FAILED;
+            goto EXIT;
+        }
+
+        if(vpp_post == 1) {
+            vaStatus = i965_CreateSurfaces(ctx,
+                                         src_obj_surface->orig_width,
+                                         src_obj_surface->orig_height,
+                                         VA_RT_FORMAT_YUV420,
+                                         1,
+                                         &out_surface_id);
+            assert(vaStatus == VA_STATUS_SUCCESS);
+            tmp_surface_id[num_tmp_surfaces++] = out_surface_id;
+            tmp_surface = SURFACE(out_surface_id);
+            assert(tmp_surface);
+            i965_check_alloc_surface_bo(ctx, tmp_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
+        }
+
+        if(tmp_surface != NULL)
+            dst_obj_surface = tmp_surface;
+        else {
+            if(dst_surface->type == I965_SURFACE_TYPE_IMAGE) {
+                dst_obj_surface = derive_surface(ctx, (struct object_image *)dst_surface->base,
+                                                 &tmp_dst_obj_surface);
+            }
+            else
+                dst_obj_surface = (struct object_surface *)dst_surface->base;
+        }
+
+        if(dst_obj_surface == NULL) {
+            vaStatus = VA_STATUS_ERROR_ALLOCATION_FAILED;
+            goto EXIT;
+        }
+
+        vaStatus = vebox_processing_simple(ctx,
+                                         pp_context,
+                                         src_obj_surface,
+                                         dst_obj_surface,
+                                         src_rect);
+        if(vaStatus != VA_STATUS_SUCCESS)
+            goto EXIT;
+
+        if(vpp_post == 1) {
+            struct i965_surface src_surface_new;
+
+            if(tmp_surface != NULL){
+                src_surface_new.base = (struct object_base *)tmp_surface;
+                src_surface_new.type = I965_SURFACE_TYPE_SURFACE;
+                src_surface_new.flags = I965_SURFACE_FLAG_FRAME;
+            }
+            else
+                memcpy((void *)&src_surface_new, (void *)src_surface, sizeof(src_surface_new));
+
+            vaStatus = i965_image_pl2_processing(ctx,
+                                               &src_surface_new,
+                                               src_rect,
+                                               dst_surface,
+                                               dst_rect);
+        }
+    }
+
+EXIT:
+    if(num_tmp_surfaces)
+        i965_DestroySurfaces(ctx,
+                             tmp_surface_id,
+                             num_tmp_surfaces);
+
+    return vaStatus;
+}
+
 VAStatus
 i965_image_processing(VADriverContextP ctx,
                       const struct i965_surface *src_surface,
@@ -5353,6 +5532,13 @@ i965_image_processing(VADriverContextP ctx,
                                                dst_surface,
                                                dst_rect);
             break;
+        case VA_FOURCC_P010:
+            status = i965_image_p010_processing(ctx,
+                                               src_surface,
+                                               src_rect,
+                                               dst_surface,
+                                               dst_rect);
+            break;
         default:
             status = VA_STATUS_ERROR_UNIMPLEMENTED;
             break;
diff --git a/src/i965_post_processing.h b/src/i965_post_processing.h
index 63e678d..a9942b2 100755
--- a/src/i965_post_processing.h
+++ b/src/i965_post_processing.h
@@ -528,6 +528,8 @@ struct i965_post_processing_context
         unsigned int curbe_allocation_size : 16;
     } vfe_gpu_state;
 
+    struct intel_vebox_context *vebox_proc_ctx;
+
     struct pp_load_save_context pp_load_save_context;
     struct pp_scaling_context pp_scaling_context;
     struct pp_avs_context pp_avs_context;
-- 
cgit v1.2.3