Age | Commit message (Collapse) | Author | Files | Lines |
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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The calloc function maybe return NULL, it will causing
memory access violation if continue using NULL C structure.
Add assert function to do checking on its.
bugzilla:
https://bugs.freedesktop.org/show_bug.cgi?id=91699
Signed-off-by: Lim Siew Hoon <siew.hoon.lim@intel.com>
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Based on the H264 spec the macroblock pair should be used to calculate
the corresponding parameters under MBAFF.(mb-adaptive frame-field).
Otherwise the wrong parameter is sent to GPU HW.
Fix the GPU hang issue in https://bugs.freedesktop.org/show_bug.cgi?id=91207
Tested-by: Lim, Siew Hoon <siew.hoon.lim@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
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It is the base of struct gen_avc_surface, and move frame_store_id
from gen_avc_surface to gen_codec_surface
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit fc7085d4930f0ceef8ced414af96a7c18cf4fe52)
Conflicts:
src/i965_decoder_utils.c
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Following haihao's suggestion, make gen6 phantom slice funcion can be
re-used by SNB+.
v1->v2: Remove an unnessary comment.
Signed-off-by: Zhong Li <zhong.li@intel.com>
Reviewed-by: Xiang Haihao <haihao.xiang@intel.com>
Gwenole Beauchesne <gwenole.beauchesne@intel.com>
(cherry picked from commit 5e30cc3093407ca2b4dbefa1da8a1262ff8ae7e9)
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In strict MVC decoding mode, when only the necessary set of inter-view
reference pictures are passed to the ReferenceFrames array for decoding
the current picture, we should not re-use a frame store id that might
be needed for decoding another view component in the same access unit.
One way to solve this problem is to track when the VA surface in a
specified frame store id was last referenced. So, a "ref_age" field
is introduced to the GenFrameStore struct and is updated whenever
the surface is being referenced.
Additionally, the list of retired refs candidates (free_refs) is kept
ordered by increasing ref_age. That way, we can immediately know what
is the oldest frame store id to recycle.
Let deltaAge = CurrAge - RefAge:
If deltaAge > 1, we know for sure that the VA surface is gone ;
If deltaAge = 1, the surface could be re-used for inter prediction ;
If deltaAge = 0, the surface could be re-used for inter-view prediction.
The ref_age in each Frame Store entry is always current, i.e. it is
the same for all reference frames that intervened in the decoding
process of all inter view components of the previous access unit. The
age tracks access units.
v2: used a more correct representation of age, instead of POC [Yakui]
v3: minor optimization for detecting changes of access unit [Haihao]
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
(cherry picked from commit 3b5eb0522fbfe1220dcd0c0bb093a93cfc25e22c)
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The optimization by which the VA surface storage is deallocated after
it is displayed and not used for reference or vaDeriveImage() purposes
cannot be implemented safely. We need to honour explicit lifetimes
defined by the upper codec layer.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
(cherry picked from commit 84926ace7a2c5b88df1ada167a1c273128469aad)
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H.264 MVC decoding support is defined as follows:
- Stereo High profile on Sandybridge and newer ;
- Multiview High profile on Haswell and newer.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
(cherry picked from commit 1f244834dedb7b46863b315a898d8649d01c5f58)
Conflicts:
src/i965_device_info.c
src/i965_drv_video.c
src/va_backend_compat.h
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Add new avc_find_picture() helper function to search for a VAPictureH264
struct based on the supplied VA surface id.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
(cherry picked from commit 3f4f9fc2893af24b7e88f44b6350a5a74d49f0c2)
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Optimize support for grayscale surfaces in two aspects: (i) space
by only allocating the luminance component ; (ii) speed by avoiding
initialization of the (now inexistent) chrominance planes.
Keep backward compatibility with older codec layers that only
supported YUV 4:2:0 and not grayscale formats properly.
v2: fix check for extra H.264 chroma formats [Haihao]
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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Add new avc_ensure_surface_bo() helper function to factor out the
allocatiion and initialization processes of the reconstructed VA
surface buffer stores.
Keep preferred native format (NV12) and initialize chroma values
to 0.0 (0x80) when needed for "fake" grayscale (Y800) surfaces
implemented on top of existing NV12.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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This is helpful to avoid the typo error when using VA_FOURCC(A, B, C, D).
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit acea969011bceee36a57fe2c0e4ee96c0c5e79c7)
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GENx doesn't support FMO/ASO, so remove the support
of Baseline profile for conformance testing. In addition, add the support
for Constrained Baseline profile.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Sometimes codec layer incorrectly fills slice parameters due to
the corrupted video
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71276
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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If the first slice does't start at 0, a phantom slice is added
before the first slice.
This fixes the GPU hang issue mentioned in https://bugs.freedesktop.org/show_bug.cgi?id=63946
(not the original issue).
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Tested-by: Krzysztof Kotlenga <pocek@users.sf.net>
(cherry picked from commit 11115e3f0427d056367c1c5946585e3f7cead662)
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Conflicts:
NEWS
configure.ac
src/Makefile.am
src/gen6_mfc.c
src/gen6_mfd.c
src/gen6_vme.c
src/gen6_vme.h
src/gen75_mfc.c
src/gen75_mfd.c
src/gen75_vme.c
src/gen75_vpp_vebox.c
src/gen75_vpp_vebox.h
src/gen7_mfd.c
src/i965_avc_bsd.c
src/i965_decoder.h
src/i965_decoder_utils.c
src/i965_defines.h
src/i965_drv_video.c
src/i965_drv_video.h
src/i965_encoder.c
src/i965_encoder.h
src/i965_output_dri.c
src/i965_post_processing.c
src/i965_post_processing.h
src/i965_render.c
src/i965_structs.h
src/intel_driver.c
src/object_heap.c
src/shaders/post_processing/Common/AYUV_Load_16x8.asm
src/shaders/post_processing/Common/AYUV_Load_16x8.inc
src/shaders/post_processing/Common/Init_All_Regs.asm
src/shaders/post_processing/Makefile.am
src/shaders/post_processing/gen5_6/Common/AYUV_Load_16x8.asm
src/shaders/post_processing/gen5_6/Common/AYUV_Load_16x8.inc
src/shaders/post_processing/gen5_6/Common/Init_All_Regs.asm
src/shaders/post_processing/gen5_6/Common/NV12_Load_8x4.asm
src/shaders/post_processing/gen5_6/Common/RGBX_Load_16x8.asm
src/shaders/post_processing/gen5_6/Common/RGBX_Load_16x8.inc
src/shaders/post_processing/gen5_6/Makefile.am
src/shaders/post_processing/gen5_6/nv12_avs_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_avs_nv12.g6b
src/shaders/post_processing/gen5_6/nv12_dn_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_dn_nv12.g6b
src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b
src/shaders/post_processing/gen5_6/nv12_load_save_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_load_save_nv12.g6b
src/shaders/post_processing/gen5_6/nv12_load_save_pa.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_load_save_pa.g6b
src/shaders/post_processing/gen5_6/nv12_load_save_pl3.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_load_save_pl3.g6b
src/shaders/post_processing/gen5_6/pa_load_save_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/pa_load_save_nv12.g6b
src/shaders/post_processing/gen5_6/pa_load_save_pl3.g4b.gen5
src/shaders/post_processing/gen5_6/pa_load_save_pl3.g6b
src/shaders/post_processing/gen5_6/pl3_load_save_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/pl3_load_save_nv12.g6b
src/shaders/post_processing/gen5_6/pl3_load_save_pa.g4b.gen5
src/shaders/post_processing/gen5_6/pl3_load_save_pa.g6b
src/shaders/post_processing/gen5_6/pl3_load_save_pl3.g4b.gen5
src/shaders/post_processing/gen5_6/pl3_load_save_pl3.g6b
src/shaders/post_processing/gen7/EOT.g4a
src/shaders/post_processing/gen7/Makefile.am
src/shaders/post_processing/gen7/PA_AVS_Buf_0.g4a
src/shaders/post_processing/gen7/PA_AVS_Buf_1.g4a
src/shaders/post_processing/gen7/PA_AVS_Buf_2.g4a
src/shaders/post_processing/gen7/PA_AVS_Buf_3.g4a
src/shaders/post_processing/gen7/PL2_AVS_Buf_0.g4a
src/shaders/post_processing/gen7/PL2_AVS_Buf_1.g4a
src/shaders/post_processing/gen7/PL2_AVS_Buf_2.g4a
src/shaders/post_processing/gen7/PL2_AVS_Buf_3.g4a
src/shaders/post_processing/gen7/PL3_AVS_Buf_0.g4a
src/shaders/post_processing/gen7/PL3_AVS_Buf_1.g4a
src/shaders/post_processing/gen7/PL3_AVS_Buf_2.g4a
src/shaders/post_processing/gen7/PL3_AVS_Buf_3.g4a
src/shaders/post_processing/gen7/Save_AVS_NV12.g4a
src/shaders/post_processing/gen7/Save_AVS_PA.g4a
src/shaders/post_processing/gen7/Save_AVS_PL3.g4a
src/shaders/post_processing/gen7/Save_AVS_RGB.g4a
src/shaders/post_processing/gen7/Set_AVS_Buf_0123_BGRA.g4a
src/shaders/post_processing/gen7/Set_AVS_Buf_0123_PL2.g4a
src/shaders/post_processing/gen7/Set_AVS_Buf_0123_PL3.g4a
src/shaders/post_processing/gen7/Set_AVS_Buf_0123_VUYA.g4a
src/shaders/post_processing/gen7/Set_AVS_Buf_0123_VYUA.g4a
src/shaders/post_processing/gen7/Set_Layer_0.g4a
src/shaders/post_processing/gen7/VP_Setup.g4a
src/shaders/vme/Makefile.am
src/shaders/vme/inter_frame_haswell.asm
src/shaders/vme/inter_frame_haswell.g75b
src/shaders/vme/intra_frame_haswell.asm
src/shaders/vme/intra_frame_haswell.g75b
src/shaders/vme/vme75.inc
src/shaders/vme/vme7_mpeg2.inc
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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In addition, uses the corresponding surface object directly.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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This is a workaround for VC1 skip picture, the corresponding
bit value in bitplane should be 1 for skip picture, but sometimes
application pass down wrong value.
Signed-off-by: Li,Xiaowei <xiaowei.a.li@intel.com>
(cherry picked from commit a76acf6441a414bb5dd601485ed8ed790218bb13)
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit e8d3f90fc18ca3726e6b34156ba56ee92c2a2524)
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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VC1_BSD_OBJECT command
A stupid error by me in the commit f750d1b
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit 88b21b9aba9be13e08109fe5d213973447f38558)
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VC1_BSD_OBJECT command
A stupid error by me in the commit f750d1b
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit 2cb319923b6ae5c1b2c643534d7a97911b9bd54e)
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Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=58448
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit 660cb88ec00a896eefc9580e691d0a07fb2870ec)
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=58448
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Li,Xiaowei <xiaowei.a.li@intel.com>
(cherry picked from commit a6dfb8f7fb601f102b414ac0c9088b5b8e88060f)
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Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=57720
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit f750d1b69e1aae65463eab224013b506481d8459)
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Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=57720
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Fix and simplify the scan for emulation_prevention_bytes, thus avoiding
a read beyond the end of the slice data buffer. Besides, if slice_header()
bytes are needed, use dri_bo_get_subdata() instead.
HW specific changes:
- SNB: make the HW skip the emulation prevention bytes itself.
- IVB: fix MFD_AVC_BSD_OBJECT to report the actual slice data buffer size.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
(cherry picked from commit 9b7863bf49dcf8bf1de9b45ce4e986dfd1cca418)
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Signed-off-by: Li,Xiaowei <xiaowei.a.li@intel.com>
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This is a workaround for VC1 skip picture, the corresponding
bit value in bitplane should be 1 for skip picture, but sometimes
application pass down wrong value.
Signed-off-by: Li,Xiaowei <xiaowei.a.li@intel.com>
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All decoded frame are considered as NV12 format in driver's,
for YUV400 format senerios, we need set the chroma component
of NV12 to a constant value(0x80), otherwise the converted ARGB
from NV12 format is not correct and cause render issue.
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
(cherry picked from commit 3ac4256d3aba3db757d086a7e7496d95cd8b0da4)
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All decoded frame are considered as NV12 format in driver's,
for YUV400 format senerios, we need set the chroma component
of NV12 to a constant value(0x80), otherwise the converted ARGB
from NV12 format is not correct and cause render issue.
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
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This fixes buffer overflow in the newly allocated Gen buffer that holds
VC-1 bitplanes.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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This is to support the 4Kx4K encoding on Haswell. Otherwise the default batch
buffer size can't hold the encoding command for 4Kx4K encoding.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
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Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
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This is to support the 4Kx4K encoding on Haswell. Otherwise the default batch
buffer size can't hold the encoding command for 4Kx4K encoding.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
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Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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Add new "sysdeps.h" file for system-dependent definitions and common
include files. This will be helpful for Android support so that to
stack every definition useful to Android that could not be auto-generated
since configure script is not built there.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
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(cherry picked from commit c7d23b1e9376808dfa88192ee66a1af5acdf3b16)
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Fix construction of reference frames list for interlaced streams.
In this case, the array is indexed by frame store ID >> 1 where
bit 0 of frame store ID represents top (0) or bottom (1) field.
Besides, current render target can also be used as a reference
while decoding the second field.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
(cherry picked from commit 14f70559b516030d141cce09db54cf49d11df9b2)
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Gen6 has specific requirements for the TFF flag, and thus has different
semantics than Gen7 (IVB). In particular, HW uses picture_structure and
TFF flag to determine the correct field to render.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
(cherry picked from commit 01c37fad8c991714026d6a995e9e35cc7865933e)
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