diff options
| author | Xiang, Haihao <haihao.xiang@intel.com> | 2015-07-23 10:05:37 +0800 |
|---|---|---|
| committer | Xiang, Haihao <haihao.xiang@intel.com> | 2015-09-06 15:13:57 +0800 |
| commit | 8e8d5487b09cd1d8f421e3147d671c4c35fdb039 (patch) | |
| tree | 537c4f39a4d33a5016dfba4a4383895fe8bc1a9e | |
| parent | 8e12b815487b117a53b16642cce95a9a7cce2620 (diff) | |
encode/hevc: fix HEVC encode on SKL GT3
GT3 has 2 BSD rings, but HEVC commands can be only dispatched to BSD ring 0.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit 611d8ea9d75dc026c203e3ebe53b434769d4587c)
| -rw-r--r-- | src/gen9_mfc_hevc.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/gen9_mfc_hevc.c b/src/gen9_mfc_hevc.c index 306abd9..e52e408 100644 --- a/src/gen9_mfc_hevc.c +++ b/src/gen9_mfc_hevc.c @@ -1783,6 +1783,7 @@ gen9_hcpe_hevc_pipeline_programing(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { + struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = encoder_context->base.batch; dri_bo *slice_batch_bo; @@ -1793,7 +1794,10 @@ gen9_hcpe_hevc_pipeline_programing(VADriverContextP ctx, #endif // begin programing - intel_batchbuffer_start_atomic_bcs(batch, 0x4000); + if (i965->intel.has_bsd2) + intel_batchbuffer_start_atomic_bcs_override(batch, 0x4000, BSD_RING0); + else + intel_batchbuffer_start_atomic_bcs(batch, 0x4000); intel_batchbuffer_emit_mi_flush(batch); // picture level programing |