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authorLuo Xionghu <xionghu.luo@intel.com>2015-10-15 09:30:31 +0800
committerYang Rong <rong.r.yang@intel.com>2015-10-20 17:15:21 +0800
commita4feb903f38635b3ff941053d45fbae612b963ff (patch)
tree9c671689f0f9c64f0d96b36751a440acc3e7330f /src
parentebc7af5c19b56cebd6fe183b669e121f1a588991 (diff)
alignment of NO TILING surface limitation shouldn't be removed.
it could cause sampler data mismatch on IVB. Signed-off-by: Luo Xionghu <xionghu.luo@intel.com> Reviewed-by: Guo, Yejun <yejun.guo@intel.com>
Diffstat (limited to 'src')
-rw-r--r--src/cl_mem.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/src/cl_mem.c b/src/cl_mem.c
index 561e0a4a..dd5078e9 100644
--- a/src/cl_mem.c
+++ b/src/cl_mem.c
@@ -847,10 +847,11 @@ _cl_mem_new_image(cl_context ctx,
/* Tiling requires to align both pitch and height */
if (tiling == CL_NO_TILE) {
aligned_pitch = w * bpp;
- if(image_type == CL_MEM_OBJECT_IMAGE1D_ARRAY || image_type == CL_MEM_OBJECT_IMAGE2D_ARRAY)
- aligned_h = ALIGN(h, cl_buffer_get_tiling_align(ctx, CL_NO_TILE, 1));
- else
+ //no need align the height if 2d image from buffer.
+ if (image_type == CL_MEM_OBJECT_IMAGE2D && buffer != NULL)
aligned_h = h;
+ else
+ aligned_h = ALIGN(h, cl_buffer_get_tiling_align(ctx, CL_NO_TILE, 1));
} else if (tiling == CL_TILE_X) {
aligned_pitch = ALIGN(w * bpp, cl_buffer_get_tiling_align(ctx, CL_TILE_X, 0));
aligned_h = ALIGN(h, cl_buffer_get_tiling_align(ctx, CL_TILE_X, 1));