diff options
author | Zhigang Gong <zhigang.gong@intel.com> | 2014-11-03 16:26:17 +0800 |
---|---|---|
committer | Zhigang Gong <zhigang.gong@intel.com> | 2014-11-06 15:16:07 +0800 |
commit | 3486c32bca5766e7d5bf7373e8ba6fa2dd6683cb (patch) | |
tree | 14ee97ea013d24fb7e6e9a9a2cc0e274a6d6c8a2 /backend | |
parent | 63c85d71062058e718dc7c1e291286be8ea3cc61 (diff) |
GBE: remove useless debug info.
This debug information is not useful now. Remove them to
avoid confusing.
Signed-off-by: Zhigang Gong <zhigang.gong@intel.com>
Reviewed-by: "Song, Ruiling" <ruiling.song@intel.com>
Diffstat (limited to 'backend')
-rw-r--r-- | backend/src/backend/gen_insn_selection.cpp | 14 |
1 files changed, 2 insertions, 12 deletions
diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp index b682d5cf..155b114a 100644 --- a/backend/src/backend/gen_insn_selection.cpp +++ b/backend/src/backend/gen_insn_selection.cpp @@ -802,13 +802,8 @@ namespace gbe } } - if (poolOffset > ctx.reservedSpillRegs) { - if (GBE_DEBUG) - std::cerr << "Instruction (#" << (uint32_t)insn.opcode - << ") src too large pooloffset " - << (uint32_t)poolOffset << std::endl; + if (poolOffset > ctx.reservedSpillRegs) return false; - } // FIXME, to support post register allocation scheduling, // put all the reserved register to the spill/unspill's destination registers. // This is not the best way. We need to refine the spill/unspill instruction to @@ -872,13 +867,8 @@ namespace gbe } } - if (poolOffset > ctx.reservedSpillRegs){ - if (GBE_DEBUG) - std::cerr << "Instruction (#" << (uint32_t)insn.opcode - << ") dst too large pooloffset " - << (uint32_t)poolOffset << std::endl; + if (poolOffset > ctx.reservedSpillRegs) return false; - } while(!regSet.empty()) { struct RegSlot regSlot = regSet.back(); regSet.pop_back(); |