diff options
author | Yang Rong <rong.r.yang@intel.com> | 2014-05-19 13:52:21 +0800 |
---|---|---|
committer | Zhigang Gong <zhigang.gong@intel.com> | 2014-05-19 12:54:16 +0800 |
commit | db86e8749b149a233611f380386ba5bf904d2ee3 (patch) | |
tree | 82b68f5633422a0a8d19c18494b622efa2b88de0 /backend/src/ir | |
parent | e7aa4146ab27d9c632233c047bb9ad0464f0ffc9 (diff) |
HSW: Workaround the slm address issue.
Each work group has it's own slm offset, and when dispatch threads,
TSG will handle it automatic in IVB. But it will fail in HSW.
After check, all work group's slm offset are 0, even the slm index is
correct in R0.0. So calc the slm offset for slm index, and add it
to the slm address.
TODO: need to find the root casue.
Signed-off-by: Yang Rong <rong.r.yang@intel.com>
Reviewed-by: Junyan He <junyan.he@inbox.com>
Diffstat (limited to 'backend/src/ir')
-rw-r--r-- | backend/src/ir/profile.cpp | 3 | ||||
-rw-r--r-- | backend/src/ir/profile.hpp | 3 |
2 files changed, 4 insertions, 2 deletions
diff --git a/backend/src/ir/profile.cpp b/backend/src/ir/profile.cpp index ddf53d1c..d583df94 100644 --- a/backend/src/ir/profile.cpp +++ b/backend/src/ir/profile.cpp @@ -41,7 +41,7 @@ namespace ir { "block_ip", "barrier_id", "thread_number", "work_dimension", "zero", "one", - "retVal" + "retVal", "slm_offset" }; #if GBE_DEBUG @@ -81,6 +81,7 @@ namespace ir { DECL_NEW_REG(FAMILY_DWORD, zero, 1); DECL_NEW_REG(FAMILY_DWORD, one, 1); DECL_NEW_REG(FAMILY_WORD, retVal, 1); + DECL_NEW_REG(FAMILY_WORD, slmoffset, 1); } #undef DECL_NEW_REG diff --git a/backend/src/ir/profile.hpp b/backend/src/ir/profile.hpp index 0652a25e..4a8062b4 100644 --- a/backend/src/ir/profile.hpp +++ b/backend/src/ir/profile.hpp @@ -68,7 +68,8 @@ namespace ir { static const Register zero = Register(24); // scalar register holds zero. static const Register one = Register(25); // scalar register holds one. static const Register retVal = Register(26); // helper register to do data flow analysis. - static const uint32_t regNum = 27; // number of special registers + static const Register slmoffset = Register(27); // Group's SLM offset in total 64K SLM + static const uint32_t regNum = 28; // number of special registers extern const char *specialRegMean[]; // special register name. } /* namespace ocl */ |