diff options
| author | Zhigang Gong <zhigang.gong@intel.com> | 2014-05-07 13:12:36 +0800 |
|---|---|---|
| committer | Zhigang Gong <zhigang.gong@intel.com> | 2014-05-13 17:18:19 +0800 |
| commit | 3142009e9eb3d6c39096909624316c6c7752e9b8 (patch) | |
| tree | f6b1c48c12b5dd2ea9cbe73f11e3128966ad580e /backend/src/ir | |
| parent | c25ec06ad7f5f99cdcc41caa4971267fdafe2210 (diff) | |
GBE: enable uniform analysis for bool data type.
v2:
refine the flag allocation implementation.
Signed-off-by: Zhigang Gong <zhigang.gong@intel.com>
Reviewed-by: Ruiling Song <ruiling.song@intel.com>
Diffstat (limited to 'backend/src/ir')
| -rw-r--r-- | backend/src/ir/liveness.cpp | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/backend/src/ir/liveness.cpp b/backend/src/ir/liveness.cpp index e36b1940..3469a208 100644 --- a/backend/src/ir/liveness.cpp +++ b/backend/src/ir/liveness.cpp @@ -76,8 +76,7 @@ namespace ir { // A destination is a killed value for (uint32_t dstID = 0; dstID < dstNum; ++dstID) { const Register reg = insn.getDst(dstID); - if ( uniform && - fn.getRegisterFamily(reg) != ir::FAMILY_BOOL && + if (uniform && fn.getRegisterFamily(reg) != ir::FAMILY_QWORD && !info.bb.definedPhiRegs.contains(reg) && insn.getOpcode() != ir::OP_ATOMIC && |