diff options
| author | Zhigang Gong <zhigang.gong@intel.com> | 2014-06-06 18:05:09 +0800 |
|---|---|---|
| committer | Zhigang Gong <zhigang.gong@intel.com> | 2014-06-09 15:14:16 +0800 |
| commit | e99f8d2da037595f8b8d9358b3c155d4e6d97229 (patch) | |
| tree | 54635a19f57c4b3dcc7fd60fbbcb0c7d4262bd29 | |
| parent | 5cf0af533e3d8e8b1db8f56297871f4f663f5050 (diff) | |
GBE: fix one illegal instruction.
When the destination is a scalar and the execution width
is 1, we should use scalar vec rather.
This patch fix the following illegal instruction:
(38 ) mov(1) g124.3<1>:F acc0<8,8,1>:F
to the correct one:
(38 ) mov(1) g124.3<1>:F acc0<0,1,0>:F
Signed-off-by: Zhigang Gong <zhigang.gong@intel.com>
Reviewed-by: "Yang, Rong R" <rong.r.yang@intel.com>
| -rw-r--r-- | backend/src/backend/gen_insn_selection.cpp | 9 | ||||
| -rw-r--r-- | backend/src/backend/gen_register.hpp | 7 |
2 files changed, 14 insertions, 2 deletions
diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp index f680265a..a90a9993 100644 --- a/backend/src/backend/gen_insn_selection.cpp +++ b/backend/src/backend/gen_insn_selection.cpp @@ -2439,8 +2439,13 @@ namespace gbe sel.curr.accWrEnable = 1; sel.MACH(GenRegister::retype(GenRegister::null(), GEN_TYPE_D), src0, src1); sel.curr.accWrEnable = 0; - sel.curr.execWidth = simdWidth != 1 ? 8 : 1;; - sel.MOV(GenRegister::retype(dst, GEN_TYPE_F), GenRegister::acc()); + if (simdWidth == 1) { + sel.curr.execWidth = 1; + sel.MOV(GenRegister::retype(dst, GEN_TYPE_F), GenRegister::vec1(GenRegister::acc())); + } else { + sel.curr.execWidth = 8; + sel.MOV(GenRegister::retype(dst, GEN_TYPE_F), GenRegister::acc()); + } // Right part of the 16-wide register now if (simdWidth == 16) { diff --git a/backend/src/backend/gen_register.hpp b/backend/src/backend/gen_register.hpp index 3967e6e8..da58c06e 100644 --- a/backend/src/backend/gen_register.hpp +++ b/backend/src/backend/gen_register.hpp @@ -687,6 +687,13 @@ namespace gbe && reg.nr == GEN_ARF_NULL); } + static INLINE GenRegister vec1(GenRegister reg) { + reg.width = GEN_WIDTH_1; + reg.hstride = GEN_HORIZONTAL_STRIDE_0; + reg.vstride = GEN_VERTICAL_STRIDE_0; + return reg; + } + static INLINE GenRegister acc(void) { return GenRegister(GEN_ARCHITECTURE_REGISTER_FILE, GEN_ARF_ACCUMULATOR, |