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| author | Zhigang Gong <zhigang.gong@intel.com> | 2014-05-13 18:29:18 +0800 |
|---|---|---|
| committer | Zhigang Gong <zhigang.gong@intel.com> | 2014-05-14 10:37:08 +0800 |
| commit | 9d93bfe2a1e7684b526a2d4ba0fee95e2a6e0b30 (patch) | |
| tree | 16b2160a0d6c1ccc0c210565956bd8081d6b7067 | |
| parent | 59449030e2fe05dfd4f8a57e4d6864797d435bd5 (diff) | |
GBE: fix one regression caused by uniform analysis.
Some instructions handle simd1 incorrectly. Disable them
currently.
v2:
add addsat into the unsupported list.
Signed-off-by: Zhigang Gong <zhigang.gong@intel.com>
Reviewed-by: "Song, Ruiling" <ruiling.song@intel.com>
| -rw-r--r-- | backend/src/ir/liveness.cpp | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/backend/src/ir/liveness.cpp b/backend/src/ir/liveness.cpp index 3469a208..c3d6fe4d 100644 --- a/backend/src/ir/liveness.cpp +++ b/backend/src/ir/liveness.cpp @@ -76,10 +76,16 @@ namespace ir { // A destination is a killed value for (uint32_t dstID = 0; dstID < dstNum; ++dstID) { const Register reg = insn.getDst(dstID); + int opCode = insn.getOpcode(); + // FIXME, ADDSAT and uniform vector should be supported. if (uniform && fn.getRegisterFamily(reg) != ir::FAMILY_QWORD && !info.bb.definedPhiRegs.contains(reg) && - insn.getOpcode() != ir::OP_ATOMIC && + opCode != ir::OP_ATOMIC && + opCode != ir::OP_MUL_HI && + opCode != ir::OP_HADD && + opCode != ir::OP_RHADD && + opCode != ir::OP_ADDSAT && (dstNum == 1 || insn.getOpcode() != ir::OP_LOAD) ) fn.setRegisterUniform(reg, true); |