diff options
| author | njn <njn@a5019735-40e9-0310-863c-91ae7b9d1cf9> | 2009-01-21 22:19:26 +0000 |
|---|---|---|
| committer | njn <njn@a5019735-40e9-0310-863c-91ae7b9d1cf9> | 2009-01-21 22:19:26 +0000 |
| commit | 63c7de1aa44e7c23c1c64ebdde034883732c0cd7 (patch) | |
| tree | 2c128169ebf5c2dc319d17ef7bced2772a9e8bf5 /cachegrind | |
| parent | 747f8b0ab93f5142c1b7ccfedf315cde839979d5 (diff) | |
Replace some 4-space indents with 3-space indents. Merged from DARWIN.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@9009 a5019735-40e9-0310-863c-91ae7b9d1cf9
Diffstat (limited to 'cachegrind')
| -rw-r--r-- | cachegrind/cg-x86.c | 12 | ||||
| -rw-r--r-- | cachegrind/cg_arch.h | 6 |
2 files changed, 9 insertions, 9 deletions
diff --git a/cachegrind/cg-x86.c b/cachegrind/cg-x86.c index 76e24d7c..873c3515 100644 --- a/cachegrind/cg-x86.c +++ b/cachegrind/cg-x86.c @@ -42,12 +42,12 @@ static void micro_ops_warn(Int actual_size, Int used_size, Int line_size) { - VG_(message)(Vg_DebugMsg, - "warning: Pentium 4 with %d KB micro-op instruction trace cache", - actual_size); - VG_(message)(Vg_DebugMsg, - " Simulating a %d KB I-cache with %d B lines", - used_size, line_size); + VG_(message)(Vg_DebugMsg, + "warning: Pentium 4 with %d KB micro-op instruction trace cache", + actual_size); + VG_(message)(Vg_DebugMsg, + " Simulating a %d KB I-cache with %d B lines", + used_size, line_size); } /* Intel method is truly wretched. We have to do an insane indexing into an diff --git a/cachegrind/cg_arch.h b/cachegrind/cg_arch.h index f771d346..dfa135dc 100644 --- a/cachegrind/cg_arch.h +++ b/cachegrind/cg_arch.h @@ -33,9 +33,9 @@ // For cache simulation typedef struct { - int size; // bytes - int assoc; - int line_size; // bytes + int size; // bytes + int assoc; + int line_size; // bytes } cache_t; // Gives the configuration of I1, D1 and L2 caches. They get overridden |