/*
 * Copyright © 2010 Jerome Glisse <glisse@freedesktop.org>
 *
 * This file is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License
 * as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 */
#include "radeon_device.h"
#include "r600_winsys.h"
#include "r600d.h"

void r700_batches_states_default(struct radeon_device *rdev, struct r600_batches *batches)
{
	struct radeon_ib *ib = batches->ib;

#if 0
	ib->ptr[ib->cpkts++] = PKT3(PKT3_START_3D_CMDBUF, 0);
	ib->ptr[ib->cpkts++] = 0x00000000;
#endif
	ib->ptr[ib->cpkts++] = PKT3(PKT3_CONTEXT_CONTROL, 1);
	ib->ptr[ib->cpkts++] = 0x80000000;
	ib->ptr[ib->cpkts++] = 0x80000000;
	ib->ptr[ib->cpkts++] = PKT3(PKT3_EVENT_WRITE, 0);
	ib->ptr[ib->cpkts++] = 0x00000016;
	/* R_008040_WAIT_UNTIL */
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONFIG_REG, 1);
	ib->ptr[ib->cpkts++] = 0x00000010;
	ib->ptr[ib->cpkts++] = S_008040_WAIT_3D_IDLE(1) | S_008040_WAIT_3D_IDLECLEAN(1);
	/* R_009714_VC_ENHANCE */
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONFIG_REG, 1);
	ib->ptr[ib->cpkts++] = 0x000005C5;
	ib->ptr[ib->cpkts++] = 0x00000000;
	/* R7xx R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ */
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONFIG_REG, 1);
	ib->ptr[ib->cpkts++] = 0x00000363;
	ib->ptr[ib->cpkts++] = 0x00004000;
	/* R_009839_DB_DEBUG */
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONFIG_REG, 1);
	ib->ptr[ib->cpkts++] = 0x0000060C;
	ib->ptr[ib->cpkts++] = 0x00000000;
	/* R_09838_DB_WATERMARK */
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONFIG_REG, 1);
	ib->ptr[ib->cpkts++] = 0x0000060E;
	ib->ptr[ib->cpkts++] = 0x00420204;
	/* R_0288A8_SQ_ESGS_RING_ITEMSIZE
	 * R_0288AC_SQ_GSVS_RING_ITEMSIZE
	 * R_0288B0_SQ_ESTMP_RING_ITEMSIZE
	 * R_0288B4_SQ_GSTMP_RING_ITEMSIZE
	 * R_0288B8_SQ_VSTMP_RING_ITEMSIZE
	 * R_0288BC_SQ_PSTMP_RING_ITEMSIZE
	 * R_0288C0_SQ_FBUF_RING_ITEMSIZE
	 * R_0288C4_SQ_REDUC_RING_ITEMSIZE
	 * R_0288C8_SQ_GS_VERT_ITEMSIZE
	 */
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONTEXT_REG, 9);
	ib->ptr[ib->cpkts++] = 0x0000022A;
	ib->ptr[ib->cpkts++] = 0x00000000;
	ib->ptr[ib->cpkts++] = 0x00000000;
	ib->ptr[ib->cpkts++] = 0x00000000;
	ib->ptr[ib->cpkts++] = 0x00000000;
	ib->ptr[ib->cpkts++] = 0x00000000;
	ib->ptr[ib->cpkts++] = 0x00000000;
	ib->ptr[ib->cpkts++] = 0x00000000;
	ib->ptr[ib->cpkts++] = 0x00000000;
	ib->ptr[ib->cpkts++] = 0x00000000;
	/* R7xx R_0287A0_CB_SHADER_CONTROL */
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
	ib->ptr[ib->cpkts++] = 0x000001E8;
	ib->ptr[ib->cpkts++] = 0x00000003;
	/* SX_MISC */
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
	ib->ptr[ib->cpkts++] = 0x000000D4;
	ib->ptr[ib->cpkts++] = 0x00000000;
	/* SX_ALPHA_TEST_CONTROL */
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
	ib->ptr[ib->cpkts++] = 0x00000104;
	ib->ptr[ib->cpkts++] = 0x00000000;
	/* SX_ALPHA_REF */
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
	ib->ptr[ib->cpkts++] = 0x0000010E;
	ib->ptr[ib->cpkts++] = 0x00000000;
	/* SPI_THREAD_GROUPING */
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
	ib->ptr[ib->cpkts++] = 0x000001B2;
	ib->ptr[ib->cpkts++] = 0x00000001;
	/* SPI_INTERP_CONTROL_0
	 * SPI_INPUT_Z
	 * SPI_FOG_CNTL
	 */
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONTEXT_REG, 3);
	ib->ptr[ib->cpkts++] = 0x000001B5;
	ib->ptr[ib->cpkts++] = 0x00000000;
	ib->ptr[ib->cpkts++] = 0x00000000;
	ib->ptr[ib->cpkts++] = 0x00000000;
	/* TA_CNTL_AUX */
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONFIG_REG, 1);
	ib->ptr[ib->cpkts++] = 0x00000542;
	ib->ptr[ib->cpkts++] = 0x07000002;
	/* VGT_VTX_VECT_EJECT_REG */
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONFIG_REG, 1);
	ib->ptr[ib->cpkts++] = 0x0000022C;
	ib->ptr[ib->cpkts++] = 0x00000000;
	/* VGT_GS_PER_ES
	 * VGT_ES_PER_GS
	 */
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONFIG_REG, 2);
	ib->ptr[ib->cpkts++] = 0x00000232;
	ib->ptr[ib->cpkts++] = 0x00000000;
	ib->ptr[ib->cpkts++] = 0x00000000;
	/* VGT_GS_VERTEX_REUSE
	 * VGT_MC_LAT_CNTL
	 */
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONFIG_REG, 2);
	ib->ptr[ib->cpkts++] = 0x00000235;
	ib->ptr[ib->cpkts++] = 0x00000000;
	ib->ptr[ib->cpkts++] = 0x00000000;
	/* VGT_GS_PER_VS */
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONFIG_REG, 1);
	ib->ptr[ib->cpkts++] = 0x0000023A;
	ib->ptr[ib->cpkts++] = 0x00000000;
	/* VGT_PRIMITIVE_TYPE */
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONFIG_REG, 1);
	ib->ptr[ib->cpkts++] = 0x00000256;
	ib->ptr[ib->cpkts++] = 0x00000005;
	/* VGT_NUM_INDICES
	 * VGT_NUM_INSTANCES
	 */
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONFIG_REG, 2);
	ib->ptr[ib->cpkts++] = 0x0000025C;
	ib->ptr[ib->cpkts++] = 0x00000000;
	ib->ptr[ib->cpkts++] = 0x00000000;
	/* VGT_MAX_VTX_INDX
	 * VGT_MIN_VTX_INDX
	 */
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONTEXT_REG, 2);
	ib->ptr[ib->cpkts++] = 0x00000100;
	ib->ptr[ib->cpkts++] = 0x00FFFFFF;
	ib->ptr[ib->cpkts++] = 0x00000000;
	/* VGT_MULTI_PRIM_IB_RESET_INDX */
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
	ib->ptr[ib->cpkts++] = 0x00000103;
	ib->ptr[ib->cpkts++] = 0x00000000;
	/* VGT_OUTPUT_PATH_CNTL */
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
	ib->ptr[ib->cpkts++] = 0x00000284;
	ib->ptr[ib->cpkts++] = 0x00000000;
	/* VGT_GS_MODE */
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
	ib->ptr[ib->cpkts++] = 0x00000290;
	ib->ptr[ib->cpkts++] = 0x00000000;
	/* VGT_ENHANCE */
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
	ib->ptr[ib->cpkts++] = 0x00000294;
	ib->ptr[ib->cpkts++] = 0x00000000;
	/* VGT_GS_OUT_PRIM_TYPE */
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
	ib->ptr[ib->cpkts++] = 0x0000029B;
	ib->ptr[ib->cpkts++] = 0x00000000;
	/* VGT_PRIMITIVEID_EN */
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
	ib->ptr[ib->cpkts++] = 0x000002A1;
	ib->ptr[ib->cpkts++] = 0x00000000;
	/* VGT_MULTI_PRIM_IB_RESET_EN */
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
	ib->ptr[ib->cpkts++] = 0x000002A5;
	ib->ptr[ib->cpkts++] = 0x00000000;
	/* VGT_INSTANCE_STEP_RATE_0
	 * VGT_INSTANCE_STEP_RATE_1
	 */
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONTEXT_REG, 2);
	ib->ptr[ib->cpkts++] = 0x000002A8;
	ib->ptr[ib->cpkts++] = 0x00000000;
	ib->ptr[ib->cpkts++] = 0x00000000;
	/* VGT_REUSE_OFF
	 * VGT_VTX_CNT_EN
	 */
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONTEXT_REG, 2);
	ib->ptr[ib->cpkts++] = 0x000002AD;
	ib->ptr[ib->cpkts++] = 0x00000000;
	ib->ptr[ib->cpkts++] = 0x00000000;
	/* VGT_VERTEX_REUSE_BLOCK_CNTL
	 * VGT_OUT_DEALLOC_CNTL
	 */
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONTEXT_REG, 2);
	ib->ptr[ib->cpkts++] = 0x00000316;
	ib->ptr[ib->cpkts++] = 0x00000000;
	ib->ptr[ib->cpkts++] = 0x00000000;
	/* SQ_CONFIG
	 * SQ_GPR_RESOURCE_MGMT_1
	 * SQ_GPR_RESOURCE_MGMT_2
	 * SQ_THREAD_RESOURCE_MGMT
	 * SQ_STACK_RESOURCE_MGMT_1
	 * SQ_STACK_RESOURCE_MGMT_2
	 */
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONFIG_REG, 6);
	ib->ptr[ib->cpkts++] = 0x00000300;
	ib->ptr[ib->cpkts++] = 0x0000000D;
	ib->ptr[ib->cpkts++] = 0x40240054;
	ib->ptr[ib->cpkts++] = 0x00000000;
	ib->ptr[ib->cpkts++] = 0x00003CBC;
	ib->ptr[ib->cpkts++] = 0x00800080;
	ib->ptr[ib->cpkts++] = 0x00000000;
	/* R7xx PA_SC_EDGERULE */
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
	ib->ptr[ib->cpkts++] = 0x0000008C;
	ib->ptr[ib->cpkts++] = 0xAAAAAAAA;
	/* PA_SC_AA_SAMPLE_LOCS_MCTX */
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
	ib->ptr[ib->cpkts++] = 0x00000307;
	ib->ptr[ib->cpkts++] = 0x00000000;
	/* PA_SC_AA_SAMPLE_LOCS_8S_WD1_M */
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
	ib->ptr[ib->cpkts++] = 0x00000308;
	ib->ptr[ib->cpkts++] = 0x00000000;
}