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path: root/drivers/net/ethernet/marvell/mvpp2.c
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2016-04-01net: mvpp2: use cache_line_size() to get cacheline sizeJisheng Zhang1-1/+1
L1_CACHE_BYTES may not be the real cacheline size, use cache_line_size to determine the cacheline size in runtime. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Suggested-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-04-01net: mvpp2: fix maybe-uninitialized warningJisheng Zhang1-1/+3
This is to fix the following maybe-uninitialized warning: drivers/net/ethernet/marvell/mvpp2.c:6007:18: warning: 'err' may be used uninitialized in this function [-Wmaybe-uninitialized] Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-03-31net: mvpp2: replace MVPP2_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTESJisheng Zhang1-13/+1
The mvpp2 ip maybe used in SoCs which may have have 64bytes cacheline size. Replace the MVPP2_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES. And since dma_alloc_coherent() is always cacheline size aligned, so remove the align checks. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-02-13net: mvpp2: Return correct error codesAmitoj Kaur Chawla1-2/+2
The return value of kzalloc on failure of allocation of memory should be -ENOMEM and not -1. Found using Coccinelle. A simplified version of the semantic patch used is: //<smpl> @@ expression *e; position p,q; @@ e@q = kzalloc(...); if@p (e == NULL) { ... return - -1 + -ENOMEM ; } //</smpl> This function may also return -1 after calling mpp2_prs_tcam_port_map_get. So that the function consistently returns meaningful error values on failure, the -1 is changed to -EINVAL. Signed-off-by: Amitoj Kaur Chawla <amitoj1606@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2015-12-04net: mvpp2: fix refilling BM pools in RX pathMarcin Wojtas1-12/+16
In hitherto code in case of RX buffer allocation error during refill, original buffer is pushed to the network stack, but the amount of available buffer pointers in BM pool is decreased. This commit fixes the situation by moving refill call before skb_put(), and returning original buffer pointer to the pool in case of an error. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Fixes: 3f518509dedc ("ethernet: Add new driver for Marvell Armada 375 network unit") Cc: <stable@vger.kernel.org> # v3.18+ Signed-off-by: David S. Miller <davem@davemloft.net>
2015-12-04net: mvpp2: fix buffers' DMA handling on RX pathMarcin Wojtas1-5/+16
Each allocated buffer, whose pointer is put into BM pool is DMA-mapped. Hence it should be properly unmapped after usage or when removing buffers from pool. This commit fixes DMA handling on RX path by adding dma_unmap_single() in mvpp2_rx() and in mvpp2_bufs_free(). The latter function's argument number had to be increased for this purpose. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Fixes: 3f518509dedc ("ethernet: Add new driver for Marvell Armada 375 network unit") Cc: <stable@vger.kernel.org> # v3.18+ Signed-off-by: David S. Miller <davem@davemloft.net>
2015-12-04net: mvpp2: fix missing DMA region unmap in egress processingMarcin Wojtas1-3/+2
The Tx descriptor release code currently calls dma_unmap_single() and dev_kfree_skb_any() if the descriptor is associated with a non-NULL skb. This condition is true only for the last fragment of the packet. Since every descriptor's buffer is DMA-mapped it has to be properly unmapped. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Fixes: 3f518509dedc ("ethernet: Add new driver for Marvell Armada 375 network unit") Cc: <stable@vger.kernel.org> # v3.18+ Signed-off-by: David S. Miller <davem@davemloft.net>
2015-08-10net: mvpp2: replace TX coalescing interrupts with hrtimerMarcin Wojtas1-47/+130
The PP2 controller is capable of per-CPU TX processing, which means there are per-CPU banked register sets and queues. Current version of the driver supports TX packet coalescing - once on given CPU sent packets amount reaches a threshold value, an IRQ occurs. However, there is a single interrupt line responsible for CPU0/1 TX and RX events (the latter is not per-CPU, the hardware does not support RSS). When the top-half executes the interrupt cause is not known. This is why in NAPI poll function, along with RX processing, IRQ cause register on both CPU's is accessed in order to determine on which of them the TX coalescing threshold might have been reached. Thus the egress processing and releasing the buffers is able to take place on the corresponding CPU. Hitherto approach lead to an illegal usage of on_each_cpu function in softirq context. The problem is solved by resigning from TX coalescing interrupts and separating egress finalization from NAPI processing. For that purpose a method of using hrtimer is introduced. In main transmit function (mvpp2_tx) buffers are released once a software coalescing threshold is reached. In case not all the data is processed a timer is set on this CPU - in its interrupt context a tasklet is scheduled in which all queues are processed. At once only one timer per-CPU can be running, which is controlled by a dedicated flag. This commit removes TX processing from NAPI polling function, disables hardware coalescing and enables hrtimer with tasklet, using new per-CPU port structure (mvpp2_port_pcpu). Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2015-08-10net: mvpp2: enable proper per-CPU TX buffers unmappingMarcin Wojtas1-15/+37
mvpp2 driver allows usage of per-CPU TX processing. Once the packets are prepared independetly on each CPU, the hardware enqueues the descriptors in common TX queue. After they are sent, the buffers and associated sk_buffs should be released on the corresponding CPU. This is why a special index is maintained in order to point to the right data to be released after transmission takes place. Each per-CPU TX queue comprise an array of sent sk_buffs, freed in mvpp2_txq_bufs_free function. However, the index was used there also for obtaining a descriptor (and therefore a buffer to be DMA-unmapped) from common TX queue, which was wrong, because it was not referring to the current CPU. This commit enables proper unmapping of sent data buffers by indexing them in per-CPU queues using a dedicated array for keeping their physical addresses. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2015-08-10net: mvpp2: remove excessive spinlocks from driver initializationMarcin Wojtas1-15/+0
Using spinlocks protection during one-time driver initialization is not necessary. Moreover it resulted in invalid GFP_KERNEL allocation under the lock. This commit removes redundant spinlocks from buffer manager part of mvpp2 initialization. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reported-by: Alexandre Fournier <alexandre.fournier@wisp-e.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2015-03-08ethernet: codespell comment spelling fixesJoe Perches1-2/+2
To test a checkpatch spelling patch, I ran codespell against drivers/net/ethernet/. $ git ls-files drivers/net/ethernet/ | \ while read file ; do \ codespell -w $file; \ done I removed a false positive in e1000_hw.h Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2014-11-01net: mvpp2: fix possible memory leakSudip Mukherjee1-9/+18
we are allocating memory using kzalloc for struct mvpp2_prs_entry, but later when we are getting error we were just returning the error value without releasing the memory. Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2014-07-29net: mvpp2: implement ioctl() operation for PHY ioctlsThomas Petazzoni1-0/+16
This commit implements the ->ndo_do_ioctl() operation so that the PHY-related ioctl() calls can work from userspace, which allows applications like mii-tool or mii-diag to do their job. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2014-07-29net: mvpp2: fix 10 Mbit/s usageThomas Petazzoni1-1/+1
This commit is similar to commit 4d12bc63ab5e ("net: mvneta: fix operation in 10 Mbit/s mode"), but this time for the mvpp2 driver. The driver was properly taking into account the 1 Gbit/s and 100 Mbit/s speeds, but not the 10 Mbit/s, which was handled as 100 Mbit/s. However, the MVPP2_GMAC_CONFIG_MII_SPEED bit in the MVPP2_GMAC_AUTONEG_CONFIG register must remain cleared to allow 10 Mbit/s operation. This commit therefore fixes 10 Mbit/s operation. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2014-07-22net: mvpp2: Simplify BM pool buffers freeingEzequiel Garcia1-13/+6
Now that all the users of mvpp2_bm_bufs_free() have been fixed, we can safely clean the function prototype. The function is always called to release all the buffers in a BM pool, and the number of buffers freed is not needed. Therefore, we change the return to a void, and remove the "num" parameter. This is a cosmetic change, to make the code slightly cleaner. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2014-07-22net: mvpp2: Fix the BM pool buffer release checkEzequiel Garcia1-3/+3
After a call to mvpp2_bm_bufs_free(), the caller usually wants to know if the function successfully freed the requested number. However, this cannot be done by looking into the BM pool count, because the current buffer count was updated by mvpp2_bm_bufs_free(). In fact, the current callers of mvpp2_bm_bufs_free() use it to release all the buffers in the pool, so we can fix this by simply checking if the pool is not empty. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2014-07-22net: mvpp2: Enable proper PHY polling and fix port functionalityMarcin Wojtas1-8/+32
Currently, the network interfaces that are not configured by the bootloader (using e.g. tftp or ping) can detect the link status but are unable to transmit data. The network controller has a functionality that allows the hardware to continuously poll the PHY and directly update the MAC configuration accordingly (speed, duplex, etc.). However, this doesn't work well with phylib's software-based polling and updating MAC configuration in the driver's callback. This commit fixes this issue by: 1. Setting MVPP2_PHY_AN_STOP_SMI0_MASK in MVPP2_PHY_AN_CFG0_REG in mvpp2_init(), which disables the harware polling feature. 2. Disabling MVPP2_GMAC_PCS_ENABLE_MASK bit in MVPP2_GMAC_CTRL_2_REG in mvpp2_port_mii_set() for port types other than SGMII. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2014-07-22net: mvpp2: Fix the periodic XON enable bitMarcin Wojtas1-1/+1
This bit was originally wrong, the correct value is BIT(1), so fix it. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2014-07-20net: mvpp2: Fix error return code in mvpp2_probe()Wei Yongjun1-0/+1
Fix to return -ENODEV from the no ports enabled error handling case instead of 0. Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: David S. Miller <davem@davemloft.net>
2014-07-20net: mvpp2: Remove redundant dev_err call in mvpp2_port_probe()Wei Yongjun1-1/+0
There is a error message within devm_ioremap_resource already, so remove the dev_err call to avoid redundant error message. Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: David S. Miller <davem@davemloft.net>
2014-07-15net: mvpp2: Fix a typo in the licenseEzequiel Garcia1-1/+1
The proper string for this license is "GPL v2", instead of "GPLv2". This commit fixes that. Reported-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2014-07-10ethernet: Add new driver for Marvell Armada 375 network unitMarcin Wojtas1-0/+6393
This commit adds a new network driver for the network controller in Marvell Armada 375 SoC. Given the controller is very different from the ones in the other Marvell SoCs that use the mv643xx_eth (Kirkwood, Orion, Discovery) and mvneta (Armada 370/38x/XP) drivers, a new driver is needed. Signed-off-by: Marcin Wojtas <mw@semihalf.com> [Ezequiel: coding style cleanup] Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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