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authorAlex Deucher <alexander.deucher@amd.com>2014-05-28 19:14:36 -0400
committerAlex Deucher <alexander.deucher@amd.com>2014-06-02 18:37:33 -0400
commit7b555e068de613b52b068adf3c74f0c774c28365 (patch)
tree49b964b6f96a47c8c6a6eba2eb3beb3bd76d66eb /drivers/gpu/drm/radeon/evergreen_hdmi.c
parentf71d9ebd92437faf8dd1ada32ab5ddac4c6e5e67 (diff)
drm/radeon: Setup HDMI_CONTROL for hdmi deep color gcp's (v2)
Program HDMI_CONTROL to send general control packets for hdmi deep color mode signalling at every video frame if bpc > 8. This is only supported on evergreen / DCE-4 and later. v2: rebase Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen_hdmi.c')
-rw-r--r--drivers/gpu/drm/radeon/evergreen_hdmi.c30
1 files changed, 30 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
index 8579721e8971..b760ef52fdcd 100644
--- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
+++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
@@ -298,6 +298,7 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
struct hdmi_avi_infoframe frame;
uint32_t offset;
ssize_t err;
+ uint32_t val;
int bpc = 8;
if (!dig || !dig->afmt)
@@ -330,6 +331,35 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
+ val = RREG32(HDMI_CONTROL + offset);
+ val &= ~HDMI_DEEP_COLOR_ENABLE;
+ val &= ~HDMI_DEEP_COLOR_DEPTH_MASK;
+
+ switch (bpc) {
+ case 0:
+ case 6:
+ case 8:
+ case 16:
+ default:
+ DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
+ drm_get_connector_name(connector), bpc);
+ break;
+ case 10:
+ val |= HDMI_DEEP_COLOR_ENABLE;
+ val |= HDMI_DEEP_COLOR_DEPTH(HDMI_30BIT_DEEP_COLOR);
+ DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
+ drm_get_connector_name(connector));
+ break;
+ case 12:
+ val |= HDMI_DEEP_COLOR_ENABLE;
+ val |= HDMI_DEEP_COLOR_DEPTH(HDMI_36BIT_DEEP_COLOR);
+ DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
+ drm_get_connector_name(connector));
+ break;
+ }
+
+ WREG32(HDMI_CONTROL + offset, val);
+
WREG32(HDMI_VBI_PACKET_CONTROL + offset,
HDMI_NULL_SEND | /* send null packets when required */
HDMI_GC_SEND | /* send general control packets */