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2014-10-22u_blitter: put a comment on util_blitter_cache_all_shaders()Brian Paul1-0/+7
2014-10-22u_blitter: use ctx->bind_fs_state(), not pipe->bind_fs_state()Brian Paul1-3/+3
2014-10-22u_blitter: create basic fs shaders in util_blitter_cache_all_shaders()Brian Paul1-1/+12
2014-10-22u_blitter: do error checking assertions for shader cachingBrian Paul1-21/+30
2014-10-22radeonsi: implement pipe_rasterizer_state::clip_halfzMarek Olšák1-0/+1
2014-10-22r600g: implement pipe_rasterizer_state::clip_halfzMarek Olšák2-0/+2
2014-10-22r300g: implement pipe_rasterizer_state::clip_halfzMarek Olšák3-0/+9
2014-10-22r600g: Drop references to destroyed blend stateMichel Dänzer1-1/+8
2014-10-21freedreno/a3xx: fix depth/stencil restore formatRob Clark1-1/+5
2014-10-21freedreno/a3xx: fix viewport state during clearRob Clark1-1/+19
2014-10-21freedreno: mark scissor state dirty when enable bit changesRob Clark1-0/+10
2014-10-21freedreno: clear vs scissorRob Clark7-13/+96
2014-10-21clover: Fix build error with LLVM 3.4.Vinson Lee1-1/+3
2014-10-21r600g,radeonsi: convert TGSI shader type to LLVM shader typeMarek Olšák1-1/+30
2014-10-21radeonsi: add some missing register definitionsMarek Olšák1-0/+23
2014-10-21radeonsi: load ring resource descriptors only onceMarek Olšák1-35/+42
2014-10-21radeonsi: clarify shader constant load functionsMarek Olšák1-40/+46
2014-10-21radeonsi: statically declare resource and sampler arraysMarek Olšák1-8/+2
2014-10-21radeonsi: remove conversion of DX9 FACE input to GLMarek Olšák1-14/+1
2014-10-21radeonsi: revert hack for random failures in glsl-max-varyingsMarek Olšák1-7/+1
2014-10-21radeonsi: generate shader pm4 states right after shader compilationMarek Olšák3-17/+24
2014-10-21radeonsi: make pm4 state generation for shaders independent of the contextMarek Olšák1-17/+9
2014-10-21radeonsi: inline si_pm4_alloc_stateMarek Olšák4-23/+17
2014-10-21r300g: replace r300_get_num_samples with a util variantMarek Olšák1-25/+1
2014-10-21gallium: add PIPE_SHADER_CAP_MAX_OUTPUTS and use it in st/mesaMarek Olšák15-0/+32
2014-10-21vc4: Fix SRC_ALPHA_SATURATE blending.Eric Anholt1-3/+11
2014-10-21vc4: Fix stencil writemask handling.Eric Anholt1-2/+2
2014-10-21vc4: Don't look at back stencil state unless two-sided stencil is enabled.Eric Anholt1-2/+6
2014-10-20freedreno/ir3: add debug flag to disable cpRob Clark4-1/+10
2014-10-20freedreno: positions come out as integers, not half-integersIlia Mirkin1-2/+2
2014-10-20freedreno/a3xx: disable early-z when we have kill'sRob Clark3-0/+10
2014-10-20freedreno/ir3: fix potential gpu lockup with killRob Clark4-2/+61
2014-10-20freedreno/ir3: comment + better fxn nameRob Clark1-3/+5
2014-10-20freedreno/a3xx: only emit dirty constsRob Clark2-5/+9
2014-10-20freedreno/a3xx: more layer/level fixesRob Clark3-8/+14
2014-10-20clover: Don't return CL_INVALID_VALUE if there is no header.EdB1-1/+1
2014-10-20clover: Add allow_empty_tag.EdB1-0/+18
2014-10-20clover: Add initial implementation of clCompileProgram for CL 1.2.EdB7-16/+77
2014-10-20clover: Add a simple compat::pair.EdB1-0/+9
2014-10-20clover/util: Allow using key_equals with pair-like objects other than std::pair.Francisco Jerez1-2/+2
2014-10-20clover/util: Define equality operators for a couple of compat classes.Francisco Jerez1-13/+30
2014-10-20clover/util: Fix construction of compat::vector with a general container as a...Francisco Jerez1-2/+4
2014-10-19vc4: Translate 4-byte index buffers to 2 bytes.Eric Anholt4-10/+92
2014-10-19vc4: Add support for rebasing texture levels so firstlevel == 0.Eric Anholt5-3/+83
2014-10-18vc4: Apply a Newton-Raphson step to improve RSQEric Anholt1-2/+20
2014-10-18vc4: Apply a Newton-Raphson step to improve RCP.Eric Anholt1-1/+17
2014-10-18vc4: Add a little bit more packet parsing to make dump reading easier.Eric Anholt1-19/+114
2014-10-17vc4: Make some assertions about how many flushes/EOFs the simulator sees.Eric Anholt4-9/+26
2014-10-17vc4: Fix accidental dropping of the low bits of the store tilebuffer packet.Eric Anholt1-3/+5
2014-10-17vc4: Set the primitive list format at the start of rendering.Eric Anholt2-0/+15
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