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2015-10-08AVX512: vpextrb/w/d/q and vpinsrb/w/d/q implementation.Igor Breger1-0/+374
This instructions doesn't have intrincis. Added tests for lowering and encoding. Differential Revision: http://reviews.llvm.org/D12317 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249688 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-20AVX512: Implement instructions encoding, lowering and intrinsicsIgor Breger1-0/+99
vinserti64x4, vinserti64x2, vinserti32x8, vinserti32x4, vinsertf64x4, vinsertf64x2, vinsertf32x8, vinsertf32x4 Added tests for encoding, lowering and intrinsics. Differential Revision: http://reviews.llvm.org/D11893 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248111 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-10AVX512: Implemented encoding and intrinsics forIgor Breger1-13/+33
vextracti64x4 ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4 Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D11802 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247276 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-09Revert "AVX512: Implemented encoding and intrinsics for vextracti64x4 ↵Renato Golin1-33/+13
,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4 Added tests for intrinsics and encoding." This reverts commit r247149, as it was breaking numerous buildbots of varied architectures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247177 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-09AVX512: Implemented encoding and intrinsics forIgor Breger1-13/+33
vextracti64x4 ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4 Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D11802 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247149 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-20AVX-512: fixed algorithm of building vectors of i1 elementsElena Demikhovsky1-14/+19
fixed extract-insert i1 element, load i1, zextload i1 should be with "and $1, %reg" to prevent loading garbage. added a bunch of new tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237793 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27[opaque pointer type] Add textual IR support for explicit type parameter to ↵David Blaikie1-5/+5
load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-12AVX-512: Fixed the "test" operation for i1 typeElena Demikhovsky1-6/+4
Using KORTESTW for comparison i1 value with zero was wrong since the instruction tests 16 bits. KORTESTW may be used with KSHIFTL+KSHIFTR that clean the 15 upper bits. I removed (X86cmp i1, 0) pattern and zero-extend i1 to i8 and then use TESTB. There are some cases where i1 is in the mask register and the upper bits are already zeroed. Then KORTESTW is the better solution, but it is subject for optimization. Meanwhile, I'm fixing the correctness issue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228916 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-25AVX-512: Changes in operations on masks registers for KNL and SKXElena Demikhovsky1-7/+14
- Added KSHIFTB/D/Q for skx - Added KORTESTB/D/Q for skx - Fixed store operation for v8i1 type for KNL - Store size of v8i1, v4i1 and v2i1 are changed to 8 bits git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227043 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-15[AVX512] Add DQ subvector insertsAdam Nemet1-3/+6
In AVX512f we support 64x2 and 32x8 inserts via matching them to 32x4 and 64x4 respectively. These are matched by "Alt" Pat<>'s (Alt stands for alternative VTs). Since DQ has native support for these intructions, I peeled off the non-"Alt" part of the baseclass into vinsert_for_size_no_alt. The DQ instructions are derived from this multiclass. The "Alt" Pat<>'s are disabled with DQ. Fixes <rdar://problem/18426089> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219874 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-15[AVX512] Add SKX testing to avx512-insert-extract.llAdam Nemet1-2/+4
This is in preparation to adding DQ subvector inserts to this testcase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219873 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-15[AVX512] Fix test to produce a defined valueAdam Nemet1-1/+1
We're inserting into a 8 wide vector, so the index should be < 8. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219872 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-25[AVX512] Make vextract*x4/vinsert*x4 tests check for the index as wellAdam Nemet1-7/+7
Extend test so that it provides coverage for the next commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218479 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09AVX-512: insert element to mask vector; store i1 dataElena Demikhovsky1-0/+38
Implemented INSERT_VECTOR_ELT operation for v16i1 and v8i1 vectors; Implemented "store" for i1 type git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205850 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-02AVX-512: Fixed extract_vector_elt for v8i1 vectorElena Demikhovsky1-6/+18
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202624 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-16AVX-512: simpyfied BUILD_VECTOR for masks; fixed cmp/test sequenceElena Demikhovsky1-2/+14
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201487 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-10AVX-512: Fixed extract_vector_elt for v16i1 and v8i1 vectors.Elena Demikhovsky1-0/+17
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201066 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-16AVX-512: Added legal type MVT::i1 and VK1 register for it.Elena Demikhovsky1-14/+8
Added scalar compare VCMPSS, VCMPSD. Implemented LowerSELECT for scalar FP operations. I replaced FSETCCss, FSETCCsd with one node type FSETCCs. Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197384 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-11AVX-512: Removed "z" suffix from AVX-512 instructions, since it is ↵Elena Demikhovsky1-5/+5
incompatible with GCC. I moved a test from avx512-vbroadcast-crash.ll to avx512-vbroadcast.ll I defined HasAVX512 predicate as AssemblerPredicate. It means that you should invoke llvm-mc with "-mcpu=knl" to get encoding for AVX-512 instructions. I need this to let AsmMatcher to set different encoding for AVX and AVX-512 instructions that have the same mnemonic and operands (all scalar instructions). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197041 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-14AVX-512: Handled extractelement from mask vector;Elena Demikhovsky1-0/+25
Added VMOSHDUP/VMOVSLDUP shuffle instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194691 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-12AVX-512: implemented extractelement with variable index.Elena Demikhovsky1-0/+37
Added parsing of mask register and "zeroing" semantic, like {%k1} {z}. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190595 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-09CHECK-LABEL-ify testsStephen Lin1-6/+6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188087 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-04AVX-512 set: added VEXTRACTPS instructionElena Demikhovsky1-1/+20
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187705 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31Added INSERT and EXTRACT intructions from AVX-512 ISA.Elena Demikhovsky1-0/+44
All insertf*/extractf* functions replaced with insert/extract since we have insertf and inserti forms. Added lowering for INSERT_VECTOR_ELT / EXTRACT_VECTOR_ELT for 512-bit vectors. Added lowering for EXTRACT/INSERT subvector for 512-bit vectors. Added a test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187491 91177308-0d34-0410-b5e6-96231b3b80d8
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