From 8b5ed7dffa1fa2835a782a8db8d4f3f1f772ada9 Mon Sep 17 00:00:00 2001 From: Peter Xu Date: Thu, 14 Jul 2016 13:56:25 +0800 Subject: intel_iommu: add support for split irqchip In split irqchip mode, IOAPIC is working in user space, only update kernel irq routes when entry changed. When IR is enabled, we directly update the kernel with translated messages. It works just like a kernel cache for the remapping entries. Since KVM irqfd is using kernel gsi routes to deliver interrupts, as long as we can support split irqchip, we will support irqfd as well. Also, since kernel gsi routes will cache translated interrupts, irqfd delivery will not suffer from any performance impact due to IR. And, since we supported irqfd, vhost devices will be able to work seamlessly with IR now. Logically this should contain both vhost-net and vhost-user case. Signed-off-by: Paolo Bonzini [move trace-events lines into target-i386/trace-events] Signed-off-by: Peter Xu Reviewed-by: Paolo Bonzini Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/i386/intel_iommu.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'hw/i386') diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 6ba5520283..c7ded0fc81 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2165,6 +2165,12 @@ do_not_translate: return 0; } +static int vtd_int_remap(X86IOMMUState *iommu, MSIMessage *src, + MSIMessage *dst, uint16_t sid) +{ + return vtd_interrupt_remap_msi(INTEL_IOMMU_DEVICE(iommu), src, dst); +} + static MemTxResult vtd_mem_ir_read(void *opaque, hwaddr addr, uint64_t *data, unsigned size, MemTxAttrs attrs) @@ -2399,6 +2405,7 @@ static void vtd_class_init(ObjectClass *klass, void *data) dc->props = vtd_properties; dc->hotpluggable = false; x86_class->realize = vtd_realize; + x86_class->int_remap = vtd_int_remap; } static const TypeInfo vtd_info = { -- cgit v1.2.3