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2017-10-24tcg: Initialize cpu_env genericallyRichard Henderson22-80/+0
2017-10-24tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota21-21/+21
2017-10-24target/sparc: check CF_PARALLEL instead of parallel_cpusEmilio G. Cota1-1/+1
2017-10-24target/sh4: check CF_PARALLEL instead of parallel_cpusEmilio G. Cota1-1/+1
2017-10-24target/s390x: check CF_PARALLEL instead of parallel_cpusEmilio G. Cota3-22/+88
2017-10-24target/m68k: check CF_PARALLEL instead of parallel_cpusEmilio G. Cota3-15/+31
2017-10-24target/i386: check CF_PARALLEL instead of parallel_cpusEmilio G. Cota1-2/+2
2017-10-24target/hppa: check CF_PARALLEL instead of parallel_cpusEmilio G. Cota3-6/+40
2017-10-24target/arm: check CF_PARALLEL instead of parallel_cpusEmilio G. Cota5-21/+68
2017-10-24tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota22-117/+118
2017-10-24qom: Introduce CPUClass.tcg_initializeRichard Henderson30-160/+28
2017-10-24tcg: Remove TCGV_EQUAL*Richard Henderson4-9/+9
2017-10-24tcg: Remove GET_TCGV_* and MAKE_TCGV_*Richard Henderson1-10/+5
2017-10-21openrisc/cputimer: Perparation for MulticoreStafford Horne4-5/+5
2017-10-21target/openrisc: Make coreid and numcores variableStafford Horne1-2/+3
2017-10-20s390x/tcg: low-address protection supportDavid Hildenbrand3-45/+62
2017-10-20s390x: refactor error handling for MSCH handlerHalil Pasic1-19/+4
2017-10-20s390x: refactor error handling for HSCH handlerHalil Pasic1-19/+4
2017-10-20s390x: refactor error handling for CSCH handlerHalil Pasic1-10/+4
2017-10-20s390x: refactor error handling for XSCH handlerHalil Pasic1-19/+4
2017-10-20s390x: improve error handling for SSCH and RSCHHalil Pasic1-46/+7
2017-10-20s390x: move s390x_new_cpu() into board codeIgor Mammedov2-21/+0
2017-10-20s390x: fix cpu object referrence leak in s390x_new_cpu()Igor Mammedov1-1/+1
2017-10-20target/s390x: special handling when starting a CPU with WAIT PSWDavid Hildenbrand2-3/+14
2017-10-20s390x/tcg: refactor stfl(e) to use s390_get_feat_block()David Hildenbrand2-39/+29
2017-10-20s390x/tcg: unlock NMIDavid Hildenbrand1-5/+0
2017-10-20s390x/cpumodel: allow to enable SENSE RUNNING STATUS for qemuDavid Hildenbrand1-0/+1
2017-10-20s390x/tcg: switch to new SIGP handling codeDavid Hildenbrand4-40/+11
2017-10-20s390x/tcg: flush the tlb on SIGP SET PREFIXDavid Hildenbrand1-0/+1
2017-10-20s390x/tcg: implement STOP and RESET interrupts for TCGDavid Hildenbrand6-6/+51
2017-10-20s390x/tcg: implement SIGP CONDITIONAL EMERGENCY SIGNALDavid Hildenbrand2-0/+38
2017-10-20s390x/tcg: implement SIGP EMERGENCY SIGNALDavid Hildenbrand1-0/+15
2017-10-20s390x/tcg: implement SIGP EXTERNAL CALLDavid Hildenbrand1-2/+23
2017-10-20s390x/tcg: implement SIGP SENSEDavid Hildenbrand1-0/+29
2017-10-20s390x/tcg: implement SIGP SENSE RUNNING STATUSDavid Hildenbrand2-0/+27
2017-10-20s390x/kvm: factor out actual handling of STOP interruptsDavid Hildenbrand3-8/+16
2017-10-20s390x/kvm: factor out SIGP code into sigp.cDavid Hildenbrand9-359/+385
2017-10-20s390x/kvm: drop two debug printsDavid Hildenbrand1-2/+0
2017-10-20s390x/kvm: factor out storing of adtl CPU statusDavid Hildenbrand3-29/+31
2017-10-20s390x/kvm: factor out storing of CPU statusDavid Hildenbrand3-66/+65
2017-10-20s390x/kvm: generalize SIGP stop and restart interrupt injectionDavid Hildenbrand5-12/+53
2017-10-20s390x/kvm: pass ipb directly into handle_sigp()David Hildenbrand1-3/+3
2017-10-20target/s390x: interpret PSW_MASK_WAIT only for TCGDavid Hildenbrand1-1/+2
2017-10-20s390x/tcg: handle WAIT PSWs during interrupt injectionDavid Hildenbrand1-0/+6
2017-10-20target/s390x: factor out handling of WAIT PSW into s390_handle_wait()David Hildenbrand3-19/+23
2017-10-20s390x/tcg: a CPU cannot switch state due to an interruptDavid Hildenbrand1-1/+0
2017-10-20s390x/tcg: STOPPED cpus can never wake upDavid Hildenbrand1-0/+6
2017-10-20s390x/tcg: take care of external interrupt subclassesDavid Hildenbrand4-13/+50
2017-10-20s390x/tcg: rework checking for deliverable interruptsDavid Hildenbrand4-17/+62
2017-10-20s390x/tcg: injection of emergency signals and external callsDavid Hildenbrand4-2/+50
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