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path: root/target/sparc
AgeCommit message (Expand)AuthorFilesLines
2017-05-23shutdown: Add source information to SHUTDOWN and RESETEric Blake1-1/+1
2017-03-09sparc/sparc64: grab BQL before calling cpu_check_irqsAlex Bennée2-0/+16
2017-03-02target/sparc: Restore ldstub of odd asisRichard Henderson1-2/+25
2017-02-24cputlb and arm/sparc targets: convert mmuidx flushes from varg to bitmapAlex Bennée1-3/+5
2017-02-21monitor: Fix crashes when using HMP commands without CPUThomas Huth1-0/+4
2017-01-24migration: extend VMStateInfoJianjun Duan1-2/+4
2017-01-18target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUsArtyom Tarasenko1-0/+11
2017-01-18target-sparc: store the UA2005 entries in sun4u formatArtyom Tarasenko2-8/+47
2017-01-18target-sparc: implement UA2005 ASI_MMU (0x21)Artyom Tarasenko1-0/+31
2017-01-18target-sparc: add more registers to dump_mmuArtyom Tarasenko1-0/+2
2017-01-18target-sparc: implement auto-demapping for UA2005 CPUsArtyom Tarasenko1-0/+22
2017-01-18target-sparc: allow 256M sized pagesArtyom Tarasenko1-17/+1
2017-01-18target-sparc: simplify ultrasparc_tsb_pointerArtyom Tarasenko1-36/+15
2017-01-18target-sparc: implement UA2005 TSB PointersArtyom Tarasenko2-22/+104
2017-01-18target-sparc: use SparcV9MMU type for sparc64 I/D-MMUsArtyom Tarasenko3-36/+24
2017-01-18target-sparc: replace the last tlb entry when no free entries leftArtyom Tarasenko1-2/+4
2017-01-18target-sparc: ignore writes to UA2005 CPU mondo queue registerArtyom Tarasenko1-0/+1
2017-01-18target-sparc: allow priveleged ASIs in hyperprivileged modeArtyom Tarasenko1-14/+18
2017-01-18target-sparc: use direct address translation in hyperprivileged modeArtyom Tarasenko2-5/+4
2017-01-18target-sparc: fix immediate UA2005 trapsArtyom Tarasenko1-1/+1
2017-01-18target-sparc: implement UA2005 rdhpstate and wrhpstate instructionsArtyom Tarasenko1-2/+5
2017-01-18target-sparc: implement UA2005 GL registerArtyom Tarasenko6-7/+58
2017-01-18target-sparc: implement UA2005 hypervisor trapsArtyom Tarasenko3-5/+39
2017-01-18target-sparc: hypervisor mode takes over nucleus modeArtyom Tarasenko2-3/+7
2017-01-18target-sparc: implement UltraSPARC-T1 Strand status ASRArtyom Tarasenko1-0/+11
2017-01-18target-sparc: implement UA2005 scratchpad registersArtyom Tarasenko3-0/+26
2017-01-18target-sparc: simplify replace_tlb_entry by using TTE_PGSIZEArtyom Tarasenko1-3/+2
2017-01-18target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor modeArtyom Tarasenko1-1/+2
2017-01-18target-sparc: add UltraSPARC T1 TLB #definesArtyom Tarasenko1-0/+4
2017-01-18target-sparc: add UA2005 TTE bit #definesArtyom Tarasenko1-0/+17
2017-01-18target-sparc: use explicit mmu register pointersArtyom Tarasenko2-12/+58
2017-01-18target-sparc: store cpu super- and hypervisor flags in TBArtyom Tarasenko2-5/+36
2017-01-18target-sparc: ignore MMU-faults if MMU is disabled in hypervisor modeArtyom Tarasenko2-2/+15
2017-01-13cputlb: drop flush_global flag from tlb_flushAlex Bennée1-6/+6
2017-01-13qom/cpu: move tlb_flush to cpu_common_resetAlex Bennée2-2/+4
2017-01-10target-sparc: Use ctpop helperRichard Henderson3-7/+1
2016-12-20Move target-* CPU file into a target/ folderThomas Huth21-0/+13805
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