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path: root/target-sh4/cpu.h
AgeCommit message (Expand)AuthorFilesLines
2012-06-04target-sh4: Let cpu_sh4_init() return SuperHCPUAndreas Färber1-2/+10
2012-04-30target-sh4: QOM'ify CPUAndreas Färber1-0/+2
2012-03-14Rename CPUState -> CPUArchStateAndreas Färber1-1/+1
2012-03-14target-sh4: Don't overuse CPUStateAndreas Färber1-5/+5
2011-08-07Remove unused is_softmmu parameter from cpu_handle_mmu_faultBlue Swirl1-1/+1
2011-06-26Move cpu_has_work and cpu_pc_from_tb to cpu.hBlue Swirl1-0/+13
2011-03-03target-sh4: move intr_at_halt out of cpu_halted()Aurelien Jarno1-1/+1
2011-01-26sh4: implement missing mmaped TLB read functionsAurelien Jarno1-0/+8
2011-01-26sh4: implement missing mmaped TLB write functionsAurelien Jarno1-2/+6
2011-01-14target-sh4: fix reset on r2dAurelien Jarno1-6/+8
2011-01-14target-sh4: define FPSCR constantsAurelien Jarno1-4/+31
2011-01-09target-sh4: implement writes to mmaped ITLBAurelien Jarno1-0/+2
2010-10-30target-xxx: Use fprintf_function (format checking)Stefan Weil1-1/+2
2010-07-03remove exec-all.h inclusion from cpu.hPaolo Bonzini1-1/+0
2010-07-03move cpu_pc_from_tb to target-*/exec.hPaolo Bonzini1-6/+0
2010-03-12Target specific usermode cleanupPaul Brook1-0/+2
2010-03-12Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.Richard Henderson1-0/+3
2010-02-09target-sh4: MMU: reduce the size of a TLB entryAurelien Jarno1-12/+11
2010-02-09sh7750: handle MMUCR TI bitAurelien Jarno1-0/+2
2009-10-01Revert "Get rid of _t suffix"Anthony Liguori1-1/+1
2009-10-01Get rid of _t suffixmalc1-1/+1
2009-08-24cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signalNathan Froyd1-0/+1
2009-07-16Update to a hopefully more future proof FSF addressBlue Swirl1-2/+1
2009-04-01SH: Improve movca.l/ocbi emulation.edgar_igl1-1/+14
2009-03-07The _exit syscall is used for both thread termination in NPTL applications,pbrook1-1/+2
2009-03-03clean build: Fix remaining sh4 warningsaurel321-0/+2
2009-03-02SH: Implement MOVCO.L and MOVLI.Laurel321-0/+2
2009-02-07SH7750/51: add register BCR3, BCR4, PCR, RTCOR, RTCNT, RTCSR, SDMR2, SDMR3 an...aurel321-0/+1
2009-01-04Update FSF address in GPL/LGPL boilerplateaurel321-1/+1
2008-12-13target-sh4: make the initial value of SR easier to readaurel321-0/+4
2008-12-13target-sh4: add prefi, icbi, syncoaurel321-0/+7
2008-12-13target-sh4: add SH7785 as CPU optionaurel321-0/+1
2008-12-11target-sh4: remove 2 warningsaurel321-0/+4
2008-12-07SH4: Implement FD bitaurel321-1/+2
2008-11-18Refactor translation block CPU state handling (Jan Kiszka)aliguori1-0/+11
2008-11-18Convert CPU_PC_FROM_TB to static inline (Jan Kiszka)aliguori1-5/+7
2008-09-15qemu sh4 nptl supportaurel321-0/+5
2008-09-02sh4: CPU versioning.aurel321-0/+17
2008-09-01SH4: Remove dyngen leftoversaurel321-3/+1
2008-08-22[sh4] memory mapped TLB entriesaurel321-0/+2
2008-08-22[sh4] sleep instructionaurel321-0/+1
2008-07-01Move interrupt_request and user_mode_only to common cpu state.pbrook1-2/+0
2008-06-29Add instruction counter.pbrook1-0/+5
2008-05-30Fix typo.pbrook1-1/+1
2008-05-30Move clone() register setup to target specific code. Handle fork-like clone.pbrook1-0/+9
2008-05-29Push common interrupt variables to cpu-defs.h (Glauber Costa)bellard1-2/+0
2008-05-28moved halted field to CPU_COMMONbellard1-1/+0
2008-05-09SH4 MMU improvementsaurel321-0/+73
2007-12-02SH4: system emulator interrupt update, by Magnus Damm.ths1-0/+1
2007-12-02SH4 delay slot code update, by Magnus Damm.ths1-9/+9