index
:
~fziglio/qemu
master
virgl-spice
Qemu experimental branch
UNKNOWN
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target-mips
/
op_helper.c
Age
Commit message (
Expand
)
Author
Files
Lines
2009-04-15
target-mips: variable names consistency
aurel32
1
-364
/
+364
2009-03-28
target-mips: implement FPU Flush-To-Zero mode
aurel32
1
-0
/
+5
2009-03-08
target-mips: remove dead code
aurel32
1
-34
/
+0
2009-03-08
target-mips: rename helpers from do_ to helper_
aurel32
1
-270
/
+261
2009-01-15
global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost)
aliguori
1
-3
/
+3
2009-01-15
Convert references to logfile/loglevel to use qemu_log*() macros
aliguori
1
-33
/
+33
2009-01-14
target-mips: fix indentation
aurel32
1
-11
/
+11
2009-01-04
Update FSF address in GPL/LGPL boilerplate
aurel32
1
-1
/
+1
2008-12-20
Fix remaining compiler warnings for mips targets.
ths
1
-2
/
+4
2008-12-07
MIPS: remove a few warnings
aurel32
1
-4
/
+4
2008-11-17
TCG variable type checking.
pbrook
1
-0
/
+21
2008-11-11
target-mips: convert bit shuffle ops to TCG
aurel32
1
-19
/
+0
2008-11-11
target-mips: convert bitfield ops to TCG
aurel32
1
-25
/
+1
2008-11-11
target-mips: fix mft* helpers/call
aurel32
1
-5
/
+5
2008-10-06
Show size for unassigned accesses (Robert Reif)
blueswir1
1
-1
/
+1
2008-09-18
Move the active FPU registers into env again, and use more TCG registers
ths
1
-261
/
+261
2008-09-14
MIPS: Fix tlbwi/tlbwr
aurel32
1
-3
/
+9
2008-07-23
Use plain standard inline.
ths
1
-7
/
+7
2008-07-23
Less hardcoding of TARGET_USER_ONLY.
ths
1
-93
/
+2
2008-07-09
Use temporary registers for the MIPS FPU emulation.
ths
1
-368
/
+612
2008-06-29
Remove unnecessary helper arguments, and fix some typos.
ths
1
-5
/
+5
2008-06-27
Avoid unused input arguments which triggered tcg errors. Spotted by
ths
1
-16
/
+18
2008-06-27
More efficient target register / TC accesses.
ths
1
-80
/
+188
2008-06-24
Remove remaining uses of T0 in the MIPS target.
ths
1
-34
/
+35
2008-06-24
Use temporaries instead of fixed registers for some instructions.
ths
1
-6
/
+6
2008-06-23
Pass T0/T1 explicitly to helper functions, and clean up a few dyngen
ths
1
-549
/
+514
2008-06-20
Convert unaligned load/store to TCG.
ths
1
-0
/
+337
2008-06-20
Convert vr54xx multiply instructions to TCG.
ths
1
-3
/
+3
2008-06-19
Convert remaining MIPS FP instructions to TCG.
ths
1
-0
/
+87
2008-06-12
Switch the standard multiplication instructions to TCG.
ths
1
-10
/
+12
2008-06-12
Switch bitfield instructions and assorted special ops to TCG.
ths
1
-0
/
+123
2008-06-12
TCGify a few more instructions.
ths
1
-0
/
+6
2008-06-09
Switch remaining CP0 instructions to TCG or helper functions.
ths
1
-4
/
+788
2008-05-25
Fix off-by-one unwinding error.
pbrook
1
-6
/
+0
2008-05-23
Fix build failure for MIPS64 targets on 64-bit hosts.
ths
1
-1
/
+2
2008-05-21
Switch MIPS clo/clz and the condition tests to TCG.
ths
1
-0
/
+10
2008-05-18
Switch most MIPS logical and arithmetic instructions to TCG.
ths
1
-50
/
+12
2008-05-10
fixed do_restore_state()
bellard
1
-5
/
+7
2008-02-12
Make MIPS MT implementation more cache friendly.
ths
1
-20
/
+20
2008-01-08
Fix broken absoluteness check for cabs.d.*.
ths
1
-2
/
+2
2007-12-25
Support for VR5432, and some of its special instructions. Original patch
ths
1
-1
/
+84
2007-12-25
Avoid host FPE for overflowing division on MIPS, by Richard Sandiford.
ths
1
-3
/
+10
2007-11-18
Add strict checking mode for softfp code.
pbrook
1
-4
/
+4
2007-11-18
Fix MIPS64 R2 instructions.
ths
1
-9
/
+7
2007-11-17
Fix int/float inconsistencies.
pbrook
1
-22
/
+20
2007-11-08
Clean out the N32 macros from target-mips, and introduce MIPS ABI specific
ths
1
-5
/
+5
2007-10-29
Adjust s390 addresses (the MSB is defined as "to be ignored").
ths
1
-1
/
+5
2007-10-28
Implement missing MIPS supervisor mode bits.
ths
1
-6
/
+12
2007-10-27
Add sharable clz/clo inline functions and use them for the mips target.
ths
1
-0
/
+13
2007-10-20
Handle IBE on MIPS properly.
ths
1
-0
/
+8
[next]