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path: root/target-mips/helper.c
AgeCommit message (Expand)AuthorFilesLines
2009-05-13Include assert.h from qemu-common.hPaul Brook1-1/+0
2009-01-15Convert references to logfile/loglevel to use qemu_log*() macrosaliguori1-25/+14
2009-01-14target-mips: fix indentationaurel321-19/+19
2009-01-12target-mips: get rid of tests on env->user_mode_onlyaurel321-220/+223
2009-01-04Update FSF address in GPL/LGPL boilerplateaurel321-1/+1
2008-12-20Fix remaining compiler warnings for mips targets.ths1-4/+0
2008-09-21Fix Xcontext fill, by Here Poussineau.ths1-1/+1
2008-07-23Less hardcoding of TARGET_USER_ONLY.ths1-221/+215
2008-06-27More efficient target register / TC accesses.ths1-15/+15
2008-03-29Fix infinite loop when invalidating TLB, by Herve Poussineau.ths1-1/+1
2008-01-04Handle some more exception types.ths1-29/+43
2008-01-03Fix exception debug output.ths1-39/+36
2007-12-26De-cruft exception definitions, and implement nicer debug output.ths1-11/+53
2007-12-25Improved PABITS handling, and config register fixes.ths1-3/+2
2007-11-22Fix off-by-one address checks in MIPS64 MMU, by Aurelien Jarno.ths1-4/+4
2007-11-08Clean out the N32 macros from target-mips, and introduce MIPS ABI specificths1-8/+8
2007-10-29Fix logic bug which broke TLBL/TLBS handling somewhat.ths1-3/+3
2007-10-28Implement missing MIPS supervisor mode bits.ths1-3/+3
2007-10-14Replace is_user variable with mmu_idx in softmmu core,j_mayer1-4/+4
2007-10-13Fix off-by-one in address check.ths1-11/+8
2007-09-30Code provision for n32/n64 mips userland emulation. Not functional yet.ths1-8/+8
2007-09-29Supervisor mode implementation, by Aurelien Jarno.ths1-27/+34
2007-09-26hflags computation cleanup, by Aurelien Jarno.ths1-7/+3
2007-09-25Optimise instructions accessing CP0, by Aurelien Jarno.ths1-0/+3
2007-09-24Per-CPU instruction decoding implementation, by Aurelien Jarno.ths1-6/+3
2007-09-17find -type f | xargs sed -i 's/[\t ]*$//g' # Yes, again. Note the star in the...ths1-1/+1
2007-09-16find -type f | xargs sed -i 's/[\t ]$//g' # on most filesths1-3/+3
2007-09-06Partial support for 34K multithreading, not functional yet.ths1-27/+30
2007-08-26Disable 64-bit instructions on 32-bit CPU, by Aurelien Jarno.ths1-3/+6
2007-06-25MIPS64 improvements, based on a patch by Aurelien Jarno.ths1-3/+3
2007-06-23Handle MIPS64 SEGBITS value correctly.ths1-13/+12
2007-05-28Handle PX/UX status flags correctly, by Aurelien Jarno.ths1-0/+3
2007-05-23The 24k wants more watch and srsmap registers.ths1-1/+1
2007-05-13Full MIPS64 MMU implementation, by Aurelien Jarno.ths1-5/+46
2007-05-13MMU code improvements, by Aurelien Jarno.ths1-12/+10
2007-05-13MIPS TLB style selection at runtime, by Herve Poussineau.ths1-31/+41
2007-05-09Preliminary MIPS 64-bit MMU implementation, by Aurelien Jarno.ths1-5/+57
2007-05-07MIPS 64-bit FPU support, plus some collateral bugfixes in theths1-0/+3
2007-05-07Clear BD slot on next exception if appropriate.ths1-0/+4
2007-04-13Another fix for CP0 Cause register handling.ths1-1/+1
2007-04-07cpu_get_phys_page_debug should return target_phys_addr_tj_mayer1-2/+2
2007-04-06Fix handling of ADES exceptions.ths1-1/+3
2007-04-05fix branch delay slot cornercases.ths1-1/+1
2007-04-05Handle EBase properly.ths1-1/+1
2007-03-30Squash logic bugs while they are fresh...ths1-1/+0
2007-03-30Sanitize mips exception handling.ths1-25/+20
2007-03-18Fix BD flag handling, cause register contents, implement some more bitsths1-3/+11
2007-02-20Replace TLSZ with TARGET_FMT_lx.ths1-6/+6
2007-02-18Fix sign-extension of VPN field in TLB, by Herve Poussineau.ths1-1/+1
2007-01-22Fix PageMask handling, second part.ths1-14/+33