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path: root/target-mips/cpu.h
AgeCommit message (Expand)AuthorFilesLines
2009-03-29target-mips: optimize gen_compute_branch()aurel321-1/+1
2009-03-08target-mips: rename helpers from do_ to helper_aurel321-8/+8
2009-03-07The _exit syscall is used for both thread termination in NPTL applications,pbrook1-1/+2
2008-12-20Fix remaining compiler warnings for mips targets.ths1-1/+18
2008-11-18Refactor translation block CPU state handling (Jan Kiszka)aliguori1-0/+8
2008-11-18Convert CPU_PC_FROM_TB to static inline (Jan Kiszka)aliguori1-5/+7
2008-11-11target-mips: optimize gen_op_addr_add() (2/2)aurel321-6/+7
2008-10-06Show size for unassigned accesses (Robert Reif)blueswir11-1/+1
2008-09-18Move the active FPU registers into env again, and use more TCG registersths1-4/+7
2008-07-23Less hardcoding of TARGET_USER_ONLY.ths1-8/+1
2008-07-09Use temporary registers for the MIPS FPU emulation.ths1-7/+1
2008-07-01Move interrupt_request and user_mode_only to common cpu state.pbrook1-2/+0
2008-06-30Move CPU save/load registration to common code.pbrook1-0/+2
2008-06-29Add instruction counter.pbrook1-0/+6
2008-06-27More efficient target register / TC accesses.ths1-37/+40
2008-06-24Remove remaining uses of T0 in the MIPS target.ths1-3/+0
2008-06-24T1 is now dead.ths1-1/+0
2008-06-11Move FP TNs to cpu env.ths1-5/+6
2008-05-30Fix typo.pbrook1-1/+1
2008-05-30Move clone() register setup to target specific code. Handle fork-like clone.pbrook1-0/+10
2008-05-29Push common interrupt variables to cpu-defs.h (Glauber Costa)bellard1-2/+0
2008-05-28moved halted field to CPU_COMMONbellard1-2/+0
2008-05-28Honour current_tc for MIPS M{T,F}{HI,LO}, by Richard Sandiford.ths1-0/+1
2008-05-06Use TCG for MIPS GPR moves.ths1-0/+1
2008-05-04Simplify mips branch handling. Retire T2 from use. Use TCG for branches.ths1-1/+0
2008-02-12Make MIPS MT implementation more cache friendly.ths1-4/+4
2007-12-30MIPS COP1X (and related) instructions, by Richard Sandiford.ths1-7/+11
2007-12-26De-cruft exception definitions, and implement nicer debug output.ths1-15/+12
2007-12-25Improved PABITS handling, and config register fixes.ths1-0/+2
2007-11-10added cpu_model parameter to cpu_init()bellard1-4/+2
2007-11-09Move kernel loader parameters from the cpu state to being board specific.ths1-5/+0
2007-10-28Implement missing MIPS supervisor mode bits.ths1-10/+16
2007-10-20Handle IBE on MIPS properly.ths1-0/+3
2007-10-14Replace is_user variable with mmu_idx in softmmu core,j_mayer1-0/+11
2007-10-12Unify '-cpu ?' option.j_mayer1-0/+1
2007-09-27Move get_sp_from_cpustate from cpu.h to target_signal.h.ths1-5/+0
2007-09-27linux-user sigaltstack() syscall, by Thayne Harbaugh.ths1-0/+5
2007-09-25Optimise instructions accessing CP0, by Aurelien Jarno.ths1-9/+10
2007-09-24Per-CPU instruction decoding implementation, by Aurelien Jarno.ths1-0/+1
2007-09-06Partial support for 34K multithreading, not functional yet.ths1-41/+198
2007-06-23Handle MIPS64 SEGBITS value correctly.ths1-0/+2
2007-06-03Move target-specific defines to the target directories.ths1-0/+6
2007-05-31Don't kill the registered irqs on reset.ths1-3/+4
2007-05-30Fix CPU (re-)selection on reset.ths1-1/+4
2007-05-29Fix usermode check, thanks Aurelien Jarno.ths1-1/+1
2007-05-29Don't check the FPU state for each FPU instruction, use hflags toths1-3/+5
2007-05-28Handle PX/UX status flags correctly, by Aurelien Jarno.ths1-0/+1
2007-05-23The 24k wants more watch and srsmap registers.ths1-2/+2
2007-05-18- Move FPU exception handling into helper functions, since they are big.ths1-3/+3
2007-05-13MIPS linux-user update.ths1-0/+1