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2018-03-12chardev: introduce chr_machine_done hookPeter Xu2-2/+2
Introduce ChardevClass.chr_machine_done() hook so that chardevs can run customized procedures after machine init. There was an existing mux user already that did similar thing but used a raw machine done notifier. Generalize it into a framework, and let the mux chardevs provide such a class-specific hook to achieve the same thing. Then we can move the mux related code to the char-mux.c file. Since at it, replace the mux_realized variable with the global machine_init_done varible. This notifier framework will be further leverged by other type of chardevs soon. Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <20180306053320.15401-6-peterx@redhat.com> Acked-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-03-12vl: export machine_init_donePeter Xu1-0/+2
We have that variable but not exported. Export that so modules can have a way to poke on whether machine init has finished. Meanwhile, set that up even before calling the notifiers, so that notifiers who may depend on this field will get a correct answer. Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <20180306053320.15401-2-peterx@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Acked-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-03-12q35: change default NIC to e1000ePaolo Bonzini1-1/+2
The e1000 NIC is getting old and is not a very good default for a PCIe machine type. Change it to e1000e, which should be supported by a good number of guests. In particular, drivers for 82574 were added first to Linux 2.6.27 (2008) and Windows 2008 R2. This does mean that Windows 2008 will not work anymore with Q35 machine types and a default "-net nic -net xxx" network configuration; it did work before because it does have an AHCI driver. However, Windows 2008 has been declared out of main stream support in 2015. It will get out of extended support in 2020. Windows 2008 R2 has the same end of support dates and, since the two are basically Vista vs. Windows 7, R2 probably is more popular. Reviewed-by: Jason Wang <jasowang@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-03-12qom: introduce object_class_get_list_sortedPaolo Bonzini1-0/+11
Unify half a dozen copies of very similar code (the only difference being whether comparisons were case-sensitive) and use it also in Tricore, which did not do any sorting of CPU model names. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-03-12Merge remote-tracking branch ↵Peter Maydell3-0/+326
'remotes/pmaydell/tags/pull-target-arm-20180309' into staging target-arm queue: * i.MX: Add i.MX7 SOC implementation and i.MX7 Sabre board * Report the correct core count in A53 L2CTLR on the ZynqMP board * linux-user: preliminary SVE support work (signal handling) * hw/arm/boot: fix memory leak in case of error loading ELF file * hw/arm/boot: avoid reading off end of buffer if passed very small image file * hw/arm: Use more CONFIG switches for the object files * target/arm: Add "-cpu max" support * hw/arm/virt: Support -machine gic-version=max * hw/sd: improve debug tracing * hw/sd: sdcard: Add the Tuning Command (CMD 19) * MAINTAINERS: add Philippe as odd-fixes maintainer for SD # gpg: Signature made Fri 09 Mar 2018 17:24:23 GMT # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20180309: (25 commits) MAINTAINERS: Add entries for SD (SDHCI, SDBus, SDCard) sdhci: Fix a typo in comment sdcard: Add the Tuning Command (CMD19) sdcard: Display which protocol is used when tracing (SD or SPI) sdcard: Display command name when tracing CMD/ACMD sdcard: Do not trace CMD55, except when we already expect an ACMD hw/arm/virt: Support -machine gic-version=max hw/arm/virt: Add "max" to the list of CPU types "virt" supports target/arm: Make 'any' CPU just an alias for 'max' target/arm: Add "-cpu max" support target/arm: Move definition of 'host' cpu type into cpu.c target/arm: Query host CPU features on-demand at instance init arm: avoid heap-buffer-overflow in load_aarch64_image arm: fix load ELF error leak hw/arm: Use more CONFIG switches for the object files aarch64-linux-user: Add support for SVE signal frame records aarch64-linux-user: Add support for EXTRA signal frame records aarch64-linux-user: Remove struct target_aux_context aarch64-linux-user: Split out helpers for guest signal handling linux-user: Implement aarch64 PR_SVE_SET/GET_VL ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-12Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into stagingPeter Maydell4-4/+19
Block layer patches # gpg: Signature made Fri 09 Mar 2018 15:09:20 GMT # gpg: using RSA key 7F09B272C88F2FD6 # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6 * remotes/kevin/tags/for-upstream: (56 commits) qemu-iotests: fix 203 migration completion race iotests: Tweak 030 in order to trigger a race condition with parallel jobs iotests: Skip test for ENOMEM error iotests: Mark all tests executable iotests: Test creating overlay when guest running qemu-iotests: Test ssh image creation over QMP qemu-iotests: Test qcow2 over file image creation with QMP block: Fail bdrv_truncate() with negative size file-posix: Fix no-op bdrv_truncate() with falloc preallocation ssh: Support .bdrv_co_create ssh: Pass BlockdevOptionsSsh to connect_to_ssh() ssh: QAPIfy host-key-check option ssh: Use QAPI BlockdevOptionsSsh object sheepdog: Support .bdrv_co_create sheepdog: QAPIfy "redundancy" create option nfs: Support .bdrv_co_create nfs: Use QAPI options in nfs_client_open() rbd: Use qemu_rbd_connect() in qemu_rbd_do_create() rbd: Assign s->snap/image_name in qemu_rbd_open() rbd: Support .bdrv_co_create ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-09Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into ↵Peter Maydell3-1/+14
staging # gpg: Signature made Fri 09 Mar 2018 13:19:02 GMT # gpg: using RSA key 9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/block-pull-request: vl: introduce vm_shutdown() virtio-scsi: fix race between .ioeventfd_stop() and vq handler virtio-blk: fix race between .ioeventfd_stop() and vq handler block: add aio_wait_bh_oneshot() virtio-blk: dataplane: Don't batch notifications if EVENT_IDX is present README: Fix typo 'git-publish' block: Fix qemu crash when using scsi-block Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-09i.MX: Add i.MX7 SOC implementation.Andrey Smirnov1-0/+222
The following interfaces are partially or fully emulated: * up to 2 Cortex A9 cores (SMP works with PSCI) * A7 MPCORE (identical to A15 MPCORE) * 4 GPTs modules * 7 GPIO controllers * 2 IOMUXC controllers * 1 CCM module * 1 SVNS module * 1 SRC module * 1 GPCv2 controller * 4 eCSPI controllers * 4 I2C controllers * 7 i.MX UART controllers * 2 FlexCAN controllers * 2 Ethernet controllers (FEC) * 3 SD controllers (USDHC) * 4 WDT modules * 1 SDMA module * 1 GPR module * 2 USBMISC modules * 2 ADC modules * 1 PCIe controller Tested to boot and work with upstream Linux (4.13+) guest. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> [PMM: folded a couple of long lines] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-09pci: Add support for Designware IP blockAndrey Smirnov2-0/+104
Add code needed to get a functional PCI subsytem when using in conjunction with upstream Linux guest (4.13+). Tested to work against "e1000e" (network adapter, using MSI interrupts) as well as "usb-ehci" (USB controller, using legacy PCI interrupts). Based on "i.MX6 Applications Processor Reference Manual" (Document Number: IMX6DQRM Rev. 4) as well as corresponding dirver in Linux kernel (circa 4.13 - 4.16 found in drivers/pci/dwc/*) Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-09block: x-blockdev-create QMP commandKevin Wolf1-1/+4
This adds a synchronous x-blockdev-create QMP command that can create qcow2 images on a given node name. We don't want to block while creating an image, so this is not the final interface in all aspects, but BlockdevCreateOptionsQcow2 and .bdrv_co_create() are what they actually might look like in the end. In any case, this should be good enough to test whether we interpret BlockdevCreateOptions as we should. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2018-03-09block: Make bdrv_is_whitelisted() publicKevin Wolf1-0/+1
We'll use a separate source file for image creation, and we need to check there whether the requested driver is whitelisted. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2018-03-09qdict: Introduce qdict_rename_keys()Kevin Wolf1-0/+6
A few block drivers will need to rename .bdrv_create options for their QAPIfication, so let's have a helper function for that. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2018-03-09util: Add qemu_opts_to_qdict_filtered()Kevin Wolf1-0/+2
This allows, given a QemuOpts for a QemuOptsList that was merged from multiple QemuOptsList, to only consider those options that exist in one specific list. Block drivers need this to separate format-layer create options from protocol-level options. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com>
2018-03-09qcow2: Use BlockdevRef in qcow2_co_create()Kevin Wolf1-0/+1
Instead of passing a separate BlockDriverState* into qcow2_co_create(), make use of the BlockdevRef that is included in BlockdevCreateOptions. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com>
2018-03-09block: convert bdrv_check callback to coroutine_fnPaolo Bonzini1-2/+3
Suggested-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1516279431-30424-8-git-send-email-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2018-03-09block: convert bdrv_invalidate_cache callback to coroutine_fnPaolo Bonzini1-1/+2
QED's bdrv_invalidate_cache implementation would like to reuse functions that acquire/release the metadata locks. Call it from coroutine context to simplify the logic. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1516279431-30424-6-git-send-email-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2018-03-09Merge remote-tracking branch 'remotes/riscv/tags/riscv-qemu-upstream-v8.2' ↵Peter Maydell16-14/+702
into staging QEMU RISC-V Emulation Support (RV64GC, RV32GC) This release renames the SiFive machines to sifive_e and sifive_u to represent the SiFive Everywhere and SiFive Unleashed platforms. SiFive has configurable soft-core IP, so it is intended that these machines will be extended to enable a variety of SiFive IP blocks. The CPU definition infrastructure has been improved and there are now vendor CPU modules including the SiFiVe E31, E51, U34 and U54 cores. The emulation accuracy for the E series has been improved by disabling the MMU for the E series. S mode has been disabled on cores that only support M mode and U mode. The two Spike machines that support two privileged ISA versions have been coalesced into one file. This series has Signed-off-by from the core contributors. *** Known Issues *** * Disassembler has some checkpatch warnings for the sake of code brevity * scripts/qemu-binfmt-conf.sh has checkpatch warnings due to line length * PMP (Physical Memory Protection) is as-of-yet unused and needs testing *** Changelog *** v8.2 * Rebase v8.1 * Fix missed case of renaming spike_v1.9 to spike_v1.9.1 v8 * Added linux-user/riscv/target_elf.h during rebase * Make resetvec configurable and clear mpp and mie on reset * Use SiFive E31, E51, U34 and U54 cores in SiFive machines * Define SiFive E31, E51, U34 and U54 cores * Refactor CPU core definition in preparation for vendor cores * Prevent S or U mode unless S or U extensions are present * SiFive E Series cores have no MMU * SiFive E Series cores have U mode * Make privileged ISA v1.10 implicit in CPU types * Remove DRAM_BASE and EXT_IO_BASE as they vary by machine * Correctly handle mtvec and stvec alignment with respect to RVC * Print more machine mode state in riscv_cpu_dump_state * Make riscv_isa_string use compact extension order method * Fix bug introduced in v6 RISCV_CPU_TYPE_NAME macro change * Parameterize spike v1.9.1 config string * Coalesce spike_v1.9.1 and spike_v1.10 machines * Rename sifive_e300 to sifive_e, and sifive_u500 to sifive_u v7 * Make spike_v1.10 the default machine * Rename spike_v1.9 to spike_v1.9.1 to match privileged spec version * Remove empty target/riscv/trace-events file * Monitor ROM 32-bit reset code needs to be target endian * Add TARGET_TIOCGPTPEER to linux-user/riscv/termbits.h * Add -initrd support to the virt board * Fix naming in spike machine interface header * Update copyright notice on RISC-V Spike machines * Update copyright notice on RISC-V HTIF Console device * Change CPU Core and translator to GPLv2+ * Change RISC-V Disassembler to GPLv2+ * Change SiFive Test Finisher to GPLv2+ * Change SiFive CLINT to GPLv2+ * Change SiFive PRCI to GPLv2+ * Change SiFive PLIC to GPLv2+ * Change RISC-V spike machines to GPLv2+ * Change RISC-V virt machine to GPLv2+ * Change SiFive E300 machine to GPLv2+ * Change SiFive U500 machine to GPLv2+ * Change RISC-V Hart Array to GPLv2+ * Change RISC-V HTIF device to GPLv2+ * Change SiFiveUART device to GPLv2+ v6 * Drop IEEE 754-201x minimumNumber/maximumNumber for fmin/fmax * Remove some unnecessary commented debug statements * Change RISCV_CPU_TYPE_NAME to use riscv-cpu suffix * Define all CPU variants for linux-user * qemu_log calls require trailing \n * Replace PLIC printfs with qemu_log * Tear out unused HTIF code and eliminate shouting debug messages * Fix illegal instruction when sfence.vma is passed (rs2) arguments * Make updates to PTE accessed and dirty bits atomic * Only require atomic PTE updates on MTTCG enabled guests * Page fault if accessed or dirty bits can't be updated * Fix get_physical_address PTE reads and writes on riscv32 * Remove erroneous comments from the PLIC * Default enable MTTCG * Make WFI less conservative * Unify local interrupt handling * Expunge HTIF interrupts * Always access mstatus.mip under a lock * Don't implement rdtime/rdtimeh in system mode (bbl emulates them) * Implement insreth/cycleh for rv32 and always enable user-mode counters * Add GDB stub support for reading and writing CSRs * Rename ENABLE_CHARDEV #ifdef from HTIF code * Replace bad HTIF ELF code with load_elf symbol callback * Convert chained if else fault handlers to switch statements * Use RISCV exception codes for linux-user page faults v5 * Implement NaN-boxing for flw, set high order bits to 1 * Use float_muladd_negate_* flags to floatXX_muladd * Use IEEE 754-201x minimumNumber/maximumNumber for fmin/fmax * Fix TARGET_NR_syscalls * Update linux-user/riscv/syscall_nr.h * Fix FENCE.I, needs to terminate translation block * Adjust unusual convention for interruptno >= 0 v4 * Add @riscv: since 2.12 to CpuInfoArch * Remove misleading little-endian comment from load_kernel * Rename cpu-model property to cpu-type * Drop some unnecessary inline function attributes * Don't allow GDB to set value of x0 register * Remove unnecessary empty property lists * Add Test Finisher device to implement poweroff in virt machine * Implement priv ISA v1.10 trap and sret/mret xPIE/xIE behavior * Store fflags data in fp_status * Purge runtime users of helper_raise_exception * Fix validate_csr * Tidy gen_jalr * Tidy immediate shifts * Add gen_exception_inst_addr_mis * Add gen_exception_debug * Add gen_exception_illegal * Tidy helper_fclass_* * Split rounding mode setting to a new function * Enforce MSTATUS_FS via TB flags * Implement acquire/release barrier semantics * Use atomic operations as required * Fix FENCE and FENCE_I * Remove commented code from spike machines * PAGE_WRITE permissions can be set on loads if page is already dirty * The result of format conversion on an NaN must be a quiet NaN * Add missing process_queued_cpu_work to riscv linux-user * Remove float(32|64)_classify from cpu.h * Removed nonsensical unions aliasing the same type * Use uintN_t instead of uintN_fast_t in fpu_helper.c * Use macros for FPU exception values in softfloat_flags_to_riscv * Move code to set round mode into set_fp_round_mode function * Convert set_fp_exceptions from a macro to an inline function * Convert round mode helper into an inline function * Make fpu_helper ieee_rm array static const * Include cpu_mmu_index in cpu_get_tb_cpu_state flags * Eliminate MPRV influence on mmu_index * Remove unrecoverable do_unassigned_access function * Only update PTE accessed and dirty bits if necessary * Remove unnecessary tlb_flush in set_mode as mode is in mmu_idx * Remove buggy support for misa writes. misa writes are optional and are not implemented in any known hardware * Always set PTE read or execute permissions during page walk * Reorder helper function declarations to match order in helper.c * Remove redundant variable declaration in get_physical_address * Remove duplicated code from get_physical_address * Use mmu_idx instead of mem_idx in riscv_cpu_get_phys_page_debug v3 * Fix indentation in PMP and HTIF debug macros * Fix disassembler checkpatch open brace '{' on next line errors * Fix trailing statements on next line in decode_inst_decompress * NOTE: the other checkpatch issues have been reviewed previously v2 * Remove redundant NULL terminators from disassembler register arrays * Change disassembler register name arrays to const * Refine disassembler internal function names * Update dates in disassembler copyright message * Remove #ifdef CONFIG_USER_ONLY version of cpu_has_work * Use ULL suffix on 64-bit constants * Move riscv_cpu_mmu_index from cpu.h to helper.c * Move riscv_cpu_hw_interrupts_pending from cpu.h to helper.c * Remove redundant TARGET_HAS_ICE from cpu.h * Use qemu_irq instead of void* for irq definition in cpu.h * Remove duplicate typedef from struct CPURISCVState * Remove redundant g_strdup from cpu_register * Remove redundant tlb_flush from riscv_cpu_reset * Remove redundant mode calculation from get_physical_address * Remove redundant debug mode printf and dcsr comment * Remove redundant clearing of MSB for bare physical addresses * Use g_assert_not_reached for invalid mode in get_physical_address * Use g_assert_not_reached for unreachable checks in get_physical_address * Use g_assert_not_reached for unreachable type in raise_mmu_exception * Return exception instead of aborting for misaligned fetches * Move exception defines from cpu.h to cpu_bits.h * Remove redundant breakpoint control definitions from cpu_bits.h * Implement riscv_cpu_unassigned_access exception handling * Log and raise exceptions for unimplemented CSRs * Match Spike HTIF exit behavior - don’t print TEST-PASSED * Make frm,fflags,fcsr writes trap when mstatus.FS is clear * Use g_assert_not_reached for unreachable invalid mode * Make hret,uret,dret generate illegal instructions * Move riscv_cpu_dump_state and int/fpr regnames to cpu.c * Lift interrupt flag and mask into constants in cpu_bits.h * Change trap debugging to use qemu_log_mask LOG_TRACE * Change CSR debugging to use qemu_log_mask LOG_TRACE * Change PMP debugging to use qemu_log_mask LOG_TRACE * Remove commented code from pmp.c * Change CpuInfoRISCV qapi schema docs to Since 2.12 * Change RV feature macro to use target_ulong cast * Remove riscv_feature and instead use misa extension flags * Make riscv_flush_icache_syscall a no-op * Undo checkpatch whitespace fixes in unrelated linux-user code * Remove redudant constants and tidy up cpu_bits.h * Make helper_fence_i a no-op * Move include "exec/cpu-all" to end of cpu.h * Rename set_privilege to riscv_set_mode * Move redundant forward declaration for cpu_riscv_translate_address * Remove TCGV_UNUSED from riscv_translate_init * Add comment to pmp.c stating the code is untested and currently unused * Use ctz to simplify decoding of PMP NAPOT address ranges * Change pmp_is_in_range to use than equal for end addresses * Fix off by one error in pmp_update_rule * Rearrange PMP_DEBUG so that formatting is compile-time checked * Rearrange trap debugging so that formatting is compile-time checked * Rearrange PLIC debugging so that formatting is compile-time checked * Use qemu_log/qemu_log_mask for HTIF logging and debugging * Move exception and interrupt names into cpu.c * Add Palmer Dabbelt as a RISC-V Maintainer * Rebase against current qemu master branch v1 * initial version based on forward port from riscv-qemu repository *** Background *** "RISC-V is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation." The QEMU RISC-V port has been developed and maintained out-of-tree for several years by Sagar Karandikar and Bastian Koppelmann. The RISC-V Privileged specification has evolved substantially over this period but has recently been solidifying. The RISC-V Base ISA has been frozon for some time and the Privileged ISA, GCC toolchain and Linux ABI are now quite stable. I have recently joined Sagar and Bastian as a RISC-V QEMU Maintainer and hope to support upstreaming the port. There are multiple vendors taping out, preparing to ship, or shipping silicon that implements the RISC-V Privileged ISA Version 1.10. There are also several RISC-V Soft-IP cores implementing Privileged ISA Version 1.10 that run on FPGA such as SiFive's Freedom U500 Platform and the U54‑MC RISC-V Core IP, among many more implementations from a variety of vendors. See https://riscv.org/ for more details. RISC-V support was upstreamed in binutils 2.28 and GCC 7.1 in the first half of 2016. RISC-V support is now available in LLVM top-of-tree and the RISC-V Linux port was accepted into Linux 4.15-rc1 late last year and is available in the Linux 4.15 release. GLIBC 2.27 added support for the RISC-V ISA running on Linux (requires at least binutils-2.30, gcc-7.3.0, and linux-4.15). We believe it is timely to submit the RISC-V QEMU port for upstream review with the goal of incorporating RISC-V support into the upcoming QEMU 2.12 release. The RISC-V QEMU port is still under active development, mostly with respect to device emulation, the addition of Hypervisor support as specified in the RISC-V Draft Privileged ISA Version 1.11, and Vector support once the first draft is finalized later this year. We believe now is the appropriate time for RISC-V QEMU development to be carried out in the main QEMU repository as the code will benefit from more rigorous review. The RISC-V QEMU port currently supports all the ISA extensions that have been finalized and frozen in the Base ISA. Blog post about recent additions to RISC-V QEMU: https://goo.gl/fJ4zgk The RISC-V QEMU wiki: https://github.com/riscv/riscv-qemu/wiki Instructions for building a busybox+dropbear root image, BBL (Berkeley Boot Loader) and linux kernel image for use with the RISC-V QEMU 'virt' machine: https://github.com/michaeljclark/busybear-linux *** Overview *** The RISC-V QEMU port implements the following specifications: * RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2 * RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1 * RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10 The RISC-V QEMU port supports the following instruction set extensions: * RV32GC with Supervisor-mode and User-mode (RV32IMAFDCSU) * RV64GC with Supervisor-mode and User-mode (RV64IMAFDCSU) The RISC-V QEMU port adds the following targets to QEMU: * riscv32-softmmu * riscv64-softmmu * riscv32-linux-user * riscv64-linux-user The RISC-V QEMU port supports the following hardware: * HTIF Console (Host Target Interface) * SiFive CLINT (Core Local Interruptor) for Timer interrupts and IPIs * SiFive PLIC (Platform Level Interrupt Controller) * SiFive Test (Test Finisher) for exiting simulation * SiFive UART, PRCI, AON, PWM, QSPI support is partially implemented * VirtIO MMIO (GPEX PCI support will be added in a future patch) * Generic 16550A UART emulation using 'hw/char/serial.c' * MTTCG and SMP support (PLIC and CLINT) on the 'virt' machine The RISC-V QEMU full system emulator supports 5 machines: * 'spike_v1.9.1', CLINT, PLIC, HTIF console, config-string, Priv v1.9.1 * 'spike_v1.10', CLINT, PLIC, HTIF console, device-tree, Priv v1.10 * 'sifive_e', CLINT, PLIC, SiFive UART, HiFive1 compat, Priv v1.10 * 'sifive_u', CLINT, PLIC, SiFive UART, device-tree, Priv v1.10 * 'virt', CLINT, PLIC, 16550A UART, VirtIO, device-tree, Priv v1.10 This is a list of RISC-V QEMU Port Contributors: * Alex Suykov * Andreas Schwab * Antony Pavlov * Bastian Koppelmann * Bruce Hoult * Chih-Min Chao * Daire McNamara * Darius Rad * David Abdurachmanov * Hesham Almatary * Ivan Griffin * Jim Wilson * Kito Cheng * Michael Clark * Palmer Dabbelt * Richard Henderson * Sagar Karandikar * Shea Levy * Stefan O'Rear Notes: * contributor email addresses available off-list on request. * checkpatch has been run on all 23 patches. * checkpatch exceptions are noted in patches that have errors. * passes "make check" on full build for all targets * tested riscv-linux-4.6.2 on 'spike_v1.9.1' machine * tested riscv-linux-4.15 on 'spike_v1.10' and 'virt' machines * tested SiFive HiFive1 binaries in 'sifive_e' machine * tested RV64 on 32-bit i386 This patch series includes the following patches: # gpg: Signature made Thu 08 Mar 2018 19:40:20 GMT # gpg: using DSA key 6BF1D7B357EF3E4F # gpg: Good signature from "Michael Clark <michaeljclark@mac.com>" # gpg: aka "Michael Clark <mjc@sifive.com>" # gpg: aka "Michael Clark <michael@metaparadigm.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 7C99 930E B17C D8BA 073D 5EFA 6BF1 D7B3 57EF 3E4F * remotes/riscv/tags/riscv-qemu-upstream-v8.2: (23 commits) RISC-V Build Infrastructure SiFive Freedom U Series RISC-V Machine SiFive Freedom E Series RISC-V Machine SiFive RISC-V PRCI Block SiFive RISC-V UART Device RISC-V VirtIO Machine SiFive RISC-V Test Finisher RISC-V Spike Machines SiFive RISC-V PLIC Block SiFive RISC-V CLINT Block RISC-V HART Array RISC-V HTIF Console Add symbol table callback interface to load_elf RISC-V Linux User Emulation RISC-V Physical Memory Protection RISC-V TCG Code Generation RISC-V GDB Stub RISC-V FPU Support RISC-V CPU Helpers RISC-V Disassembler ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-08vl: introduce vm_shutdown()Stefan Hajnoczi2-1/+1
Commit 00d09fdbbae5f7864ce754913efc84c12fdf9f1a ("vl: pause vcpus before stopping iothreads") and commit dce8921b2baaf95974af8176406881872067adfa ("iothread: Stop threads before main() quits") tried to work around the fact that emulation was still active during termination by stopping iothreads. They suffer from race conditions: 1. virtio_scsi_handle_cmd_vq() racing with iothread_stop_all() hits the virtio_scsi_ctx_check() assertion failure because the BDS AioContext has been modified by iothread_stop_all(). 2. Guest vq kick racing with main loop termination leaves a readable ioeventfd that is handled by the next aio_poll() when external clients are enabled again, resulting in unwanted emulation activity. This patch obsoletes those commits by fully disabling emulation activity when vcpus are stopped. Use the new vm_shutdown() function instead of pause_all_vcpus() so that vm change state handlers are invoked too. Virtio devices will now stop their ioeventfds, preventing further emulation activity after vm_stop(). Note that vm_stop(RUN_STATE_SHUTDOWN) cannot be used because it emits a QMP STOP event that may affect existing clients. It is no longer necessary to call replay_disable_events() directly since vm_shutdown() does so already. Drop iothread_stop_all() since it is no longer used. Cc: Fam Zheng <famz@redhat.com> Cc: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Fam Zheng <famz@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 20180307144205.20619-5-stefanha@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2018-03-08block: add aio_wait_bh_oneshot()Stefan Hajnoczi1-0/+13
Sometimes it's necessary for the main loop thread to run a BH in an IOThread and wait for its completion. This primitive is useful during startup/shutdown to synchronize and avoid race conditions. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Fam Zheng <famz@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 20180307144205.20619-2-stefanha@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2018-03-08s390x/sclp: clean up sclp masksClaudio Imbrenda1-9/+13
Introduce an sccb_mask_t to be used for SCLP event masks instead of just unsigned int or uint32_t. This will allow later to extend the mask with more ease. Signed-off-by: Claudio Imbrenda <imbrenda@linux.vnet.ibm.com> Message-Id: <1519407778-23095-3-git-send-email-imbrenda@linux.vnet.ibm.com> Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-03-08s390x/sclpconsole: Remove dead code - remove exit handlersNia Alarie1-1/+0
The other event handlers (quiesce and cpu) do not define these handlers, and this one does nothing, so it can be removed. Signed-off-by: Nia Alarie <nia.alarie@gmail.com> Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Message-Id: <20180306100721.19419-1-nia.alarie@gmail.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-03-08Merge remote-tracking branch 'remotes/berrange/tags/qio-next-pull-request' ↵Peter Maydell5-8/+85
into staging # gpg: Signature made Wed 07 Mar 2018 11:24:41 GMT # gpg: using RSA key BE86EBB415104FDF # gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>" # gpg: aka "Daniel P. Berrange <berrange@redhat.com>" # Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E 8E3F BE86 EBB4 1510 4FDF * remotes/berrange/tags/qio-next-pull-request: qio: non-default context for TLS handshake qio: non-default context for async conn qio: non-default context for threaded qtask qio: store gsources for net listeners qio: introduce qio_channel_add_watch_{full|source} qio: rename qio_task_thread_result Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-07RISC-V Build InfrastructureMichael Clark1-0/+1
This adds RISC-V into the build system enabling the following targets: - riscv32-softmmu - riscv64-softmmu - riscv32-linux-user - riscv64-linux-user This adds defaults configs for RISC-V, enables the build for the RISC-V CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh' script is updated to add the RISC-V ELF magic. Expected checkpatch errors for consistency reasons: ERROR: line over 90 characters FILE: scripts/qemu-binfmt-conf.sh Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07SiFive Freedom U Series RISC-V MachineMichael Clark1-0/+69
This provides a RISC-V Board compatible with the the SiFive Freedom U SDK. The following machine is implemented: - 'sifive_u'; CLINT, PLIC, UART, device-tree Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07SiFive Freedom E Series RISC-V MachineMichael Clark1-0/+79
This provides a RISC-V Board compatible with the the SiFive Freedom E SDK. The following machine is implemented: - 'sifive_e'; CLINT, PLIC, UART, AON, GPIO, QSPI, PWM Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07SiFive RISC-V PRCI BlockMichael Clark1-0/+37
Simple model of the PRCI (Power, Reset, Clock, Interrupt) to emulate register reads made by the SDK BSP. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07SiFive RISC-V UART DeviceMichael Clark1-0/+71
QEMU model of the UART on the SiFive E300 and U500 series SOCs. BBL supports the SiFive UART for early console access via the SBI (Supervisor Binary Interface) and the linux kernel SBI console. The SiFive UART implements the pre qom legacy interface consistent with the 16550a UART in 'hw/char/serial.c'. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stefan O'Rear <sorear2@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07RISC-V VirtIO MachineMichael Clark1-0/+74
RISC-V machine with device-tree, 16550a UART and VirtIO MMIO. The following machine is implemented: - 'virt'; CLINT, PLIC, 16550A UART, VirtIO MMIO, device-tree Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07SiFive RISC-V Test FinisherMichael Clark1-0/+42
Test finisher memory mapped device used to exit simulation. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07RISC-V Spike MachinesMichael Clark1-0/+53
RISC-V machines compatble with Spike aka riscv-isa-sim, the RISC-V Instruction Set Simulator. The following machines are implemented: - 'spike_v1.9.1'; HTIF console, config-string, Privileged ISA Version 1.9.1 - 'spike_v1.10'; HTIF console, device-tree, Privileged ISA Version 1.10 Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07SiFive RISC-V PLIC BlockMichael Clark1-0/+85
The PLIC (Platform Level Interrupt Controller) device provides a parameterizable interrupt controller based on SiFive's PLIC specification. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stefan O'Rear <sorear2@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07SiFive RISC-V CLINT BlockMichael Clark1-0/+50
The CLINT (Core Local Interruptor) device provides real-time clock, timer and interprocessor interrupts based on SiFive's CLINT specification. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Stefan O'Rear <sorear2@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07RISC-V HART ArrayMichael Clark1-0/+39
Holds the state of a heterogenous array of RISC-V hardware threads. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07RISC-V HTIF ConsoleMichael Clark1-0/+61
HTIF (Host Target Interface) provides console emulation for QEMU. HTIF allows identical copies of BBL (Berkeley Boot Loader) and linux to run on both Spike and QEMU. BBL provides HTIF console access via the SBI (Supervisor Binary Interface) and the linux kernel SBI console. The HTIT chardev implements the pre qom legacy interface consistent with the 16550a UART in 'hw/char/serial.c'. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Stefan O'Rear <sorear2@gmail.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07Add symbol table callback interface to load_elfMichael Clark2-14/+37
The RISC-V HTIF (Host Target Interface) console device requires access to the symbol table to locate the 'tohost' and 'fromhost' symbols. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07RISC-V DisassemblerMichael Clark1-0/+2
The RISC-V disassembler has no dependencies outside of the 'disas' directory so it can be applied independently. The majority of the disassembler is machine-generated from instruction set metadata: - https://github.com/michaeljclark/riscv-meta Expected checkpatch errors for consistency and brevity reasons: ERROR: line over 90 characters ERROR: trailing statements should be on next line ERROR: space prohibited between function name and open parenthesis '(' Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07RISC-V ELF Machine DefinitionMichael Clark1-0/+2
Define RISC-V ELF machine EM_RISCV 243 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-06address_space_read: address_space_to_flatview needs RCU lockPaolo Bonzini1-15/+10
address_space_read is calling address_space_to_flatview but it can be called outside the RCU lock. To fix it, push the rcu_read_lock/unlock pair up from flatview_read_full to address_space_read's constant size fast path and address_space_read_full. Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-03-06memory: inline some performance-sensitive accessorsPaolo Bonzini2-5/+30
These accessors are called from inlined functions, and the call sequence is much more expensive than just inlining the access. Move the struct declaration to memory-internal.h so that exec.c and memory.c can both use an inline function. Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-03-06lockable: workaround GCC link issue with ASANMarc-André Lureau1-1/+1
Current GCC has an optimization bug when compiling with ASAN. See also GCC bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84307 Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20180215212552.26997-3-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-03-06qmp: Add qom-list-properties to list QOM object propertiesAlexey Kardashevskiy1-0/+16
There is already 'device-list-properties' which does most of the job, however it does not handle everything returned by qom-list-types such as machines as they inherit directly from TYPE_OBJECT and not TYPE_DEVICE. It does not handle abstract classes either. This adds a new qom-list-properties command which prints properties of a specific class and its instance. It is pretty much a simplified copy of the device-list-properties handler. Since it creates an object instance, device properties should appear in the output as they are copied to QOM properties at the instance_init hook. This adds a object_class_property_iter_init() helper to allow class properties enumeration uses it in the new QMP command to allow properties listing for abstract classes. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Message-Id: <20180301130939.15875-3-aik@ozlabs.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-03-06scsi: Remove automatic creation of SCSI controllers with -drive if=scsiThomas Huth1-1/+1
Automatic creation of SCSI controllers for "-drive if=scsi" for x86 machines was quite a bad idea (see description of commit f778a82f0c179 for details). This is marked as deprecated since QEMU v2.9.0, and as far as I know, nobody complained that this is still urgently required anymore. Time to remove this now. Suggested-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1519123357-13225-1-git-send-email-thuth@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-03-06Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into stagingPeter Maydell4-67/+171
Block layer patches # gpg: Signature made Mon 05 Mar 2018 17:45:51 GMT # gpg: using RSA key 7F09B272C88F2FD6 # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6 * remotes/kevin/tags/for-upstream: (38 commits) block: Fix NULL dereference on empty drive error qcow2: Replace align_offset() with ROUND_UP() block/ssh: Add basic .bdrv_truncate() block/ssh: Make ssh_grow_file() blocking block/ssh: Pull ssh_grow_file() from ssh_create() qemu-img: Make resize error message more general qcow2: make qcow2_co_create2() a coroutine_fn block: rename .bdrv_create() to .bdrv_co_create_opts() Revert "IDE: Do not flush empty CDROM drives" block: test blk_aio_flush() with blk->root == NULL block: add BlockBackend->in_flight counter block: extract AIO_WAIT_WHILE() from BlockDriverState aio: rename aio_context_in_iothread() to in_aio_context_home_thread() docs: document how to use the l2-cache-entry-size parameter specs/qcow2: Fix documentation of the compressed cluster descriptor iotest 033: add misaligned write-zeroes test via truncate block: fix write with zero flag set and iovector provided block: Drop unused .bdrv_co_get_block_status() vvfat: Switch to .bdrv_co_block_status() vpc: Switch to .bdrv_co_block_status() ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # include/block/block.h
2018-03-06qio: non-default context for TLS handshakePeter Xu1-1/+4
A new parameter "context" is added to qio_channel_tls_handshake() is to allow the TLS to be run on a non-default context. Still, no functional change. Signed-off-by: Peter Xu <peterx@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2018-03-06qio: non-default context for async connPeter Xu1-3/+12
We have worked on qio_task_run_in_thread() already. Further, let all the qio channel APIs use that context. Signed-off-by: Peter Xu <peterx@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2018-03-06qio: non-default context for threaded qtaskPeter Xu1-2/+5
qio_task_run_in_thread() allows main thread to run blocking operations in the background. However it has an assumption on that it's always working with the default context. This patch tries to allow the threaded QIO task framework to run with non-default gcontext. Currently no functional change so far, so the QIOTasks are still always running on main context. Reviewed-by: Daniel P. Berrange <berrange@redhat.com> Signed-off-by: Peter Xu <peterx@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2018-03-06qio: store gsources for net listenersPeter Xu1-2/+20
Originally we were storing the GSources tag IDs. That'll be not enough if we are going to support non-default gcontext for QIO code. Switch to GSources without changing anything real. Now we still always pass in NULL, which means the default gcontext. Signed-off-by: Peter Xu <peterx@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2018-03-06qio: introduce qio_channel_add_watch_{full|source}Peter Xu1-0/+44
Firstly, introduce an internal qio_channel_add_watch_full(), which enhances qio_channel_add_watch() that context can be specified. Then add a new API wrapper qio_channel_add_watch_source() to return a GSource pointer rather than a tag ID. Note that the _source() call will keep a reference of GSource so that callers need to unref them explicitly when finished using the GSource. Signed-off-by: Peter Xu <peterx@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2018-03-06ppc/spapr-caps: Convert cap-ibs to custom spapr-capSuraj Jitindar Singh1-1/+4
Convert cap-ibs (indirect branch speculation) to a custom spapr-cap type. All tristate caps have now been converted to custom spapr-caps, so remove the remaining support for them. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> [dwg: Don't explicitly list "?"/help option, trust convention] [dwg: Fold tristate removal into here, to not break bisect] [dwg: Fix minor style problems] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-03-06mac_newworld: use object link to pass OpenPIC object to macioMark Cave-Ayland1-1/+3
Also switch macio_newworld_realize() over to use it rather than using the pic_mem memory region directly. Now that both Old World and New World macio devices no longer make use of the pic_mem memory region directly, we can remove it. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-22 21:00:11 +0000