~fziglio/qemu - Qemu experimental branch

Age	Commit message (Expand)	Author	Files	Lines
2018-06-01	hw: Do not include "exec/address-spaces.h" if it is not necessary	Philippe Mathieu-Daudé	1	-1/+0
2018-05-10	Merge remote-tracking branch 'remotes/riscv/tags/riscv-qemu-2.13-minor-fixes-...	Peter Maydell	1	-4/+8
2018-05-09	riscv: htif: increase the priority of the htif subregion	KONRAD Frederic	1	-2/+3
2018-05-09	riscv: spike: allow base == 0	KONRAD Frederic	1	-2/+5
2018-05-06	RISC-V: Mark ROM read-only after copying in code	Michael Clark	4	-82/+101
2018-05-06	RISC-V: Remove EM_RISCV ELF_MACHINE indirection	Michael Clark	4	-4/+4
2018-05-06	RISC-V: Remove unused class definitions	Michael Clark	5	-101/+0
2018-05-06	RISC-V: Remove identity_translate from load_elf	Michael Clark	4	-24/+4
2018-05-06	RISC-V: Use ROM base address and size from memmap	Michael Clark	1	-2/+2
2018-05-06	RISC-V: Make virt board description match spike	Michael Clark	1	-1/+1
2018-05-06	RISC-V: Replace hardcoded constants with enum values	Michael Clark	4	-12/+15
2018-04-26	Change references to serial_hds[] to serial_hd()	Peter Maydell	4	-7/+7
2018-03-07	RISC-V Build Infrastructure	Michael Clark	1	-0/+11
2018-03-07	SiFive Freedom U Series RISC-V Machine	Michael Clark	1	-0/+339
2018-03-07	SiFive Freedom E Series RISC-V Machine	Michael Clark	1	-0/+234
2018-03-07	SiFive RISC-V PRCI Block	Michael Clark	1	-0/+89
2018-03-07	SiFive RISC-V UART Device	Michael Clark	1	-0/+176
2018-03-07	RISC-V VirtIO Machine	Michael Clark	1	-0/+420
2018-03-07	SiFive RISC-V Test Finisher	Michael Clark	1	-0/+93
2018-03-07	RISC-V Spike Machines	Michael Clark	1	-0/+376
2018-03-07	SiFive RISC-V PLIC Block	Michael Clark	1	-0/+505
2018-03-07	SiFive RISC-V CLINT Block	Michael Clark	1	-0/+254
2018-03-07	RISC-V HART Array	Michael Clark	1	-0/+89
2018-03-07	RISC-V HTIF Console	Michael Clark	1	-0/+258