diff options
| author | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-08-28 21:02:19 +0000 |
|---|---|---|
| committer | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-08-28 21:02:19 +0000 |
| commit | ccc9cc5bab6158b70ca333878358a9fbfb149f89 (patch) | |
| tree | 4aa2497d87e485e8af937793917ac789e013b297 /target-sh4 | |
| parent | f36672ae1966eab1b8d87a01328a0ad1b50df090 (diff) | |
SH4: Convert immediate loads to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5098 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sh4')
| -rw-r--r-- | target-sh4/op.c | 12 | ||||
| -rw-r--r-- | target-sh4/translate.c | 8 |
2 files changed, 4 insertions, 16 deletions
diff --git a/target-sh4/op.c b/target-sh4/op.c index 21b8287de6..a37ff72047 100644 --- a/target-sh4/op.c +++ b/target-sh4/op.c @@ -37,18 +37,6 @@ static inline void cond_t(int cond) clr_t(); } -void OPPROTO op_movl_imm_T0(void) -{ - T0 = (uint32_t) PARAM1; - RETURN(); -} - -void OPPROTO op_movl_imm_T1(void) -{ - T1 = (uint32_t) PARAM1; - RETURN(); -} - void OPPROTO op_cmp_eq_imm_T0(void) { cond_t((int32_t) T0 == (int32_t) PARAM1); diff --git a/target-sh4/translate.c b/target-sh4/translate.c index c00f657493..9c1cb165c1 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -337,12 +337,12 @@ void _decode_opc(DisasContext * ctx) gen_op_movl_imm_rN(B7_0s, REG(B11_8)); return; case 0x9000: /* mov.w @(disp,PC),Rn */ - gen_op_movl_imm_T0(ctx->pc + 4 + B7_0 * 2); + tcg_gen_movi_tl(cpu_T[0], ctx->pc + 4 + B7_0 * 2); gen_op_ldw_T0_T0(ctx); gen_op_movl_T0_rN(REG(B11_8)); return; case 0xd000: /* mov.l @(disp,PC),Rn */ - gen_op_movl_imm_T0((ctx->pc + 4 + B7_0 * 4) & ~3); + tcg_gen_movi_tl(cpu_T[0], (ctx->pc + 4 + B7_0 * 4) & ~3); gen_op_ldl_T0_T0(ctx); gen_op_movl_T0_rN(REG(B11_8)); return; @@ -1181,14 +1181,14 @@ void _decode_opc(DisasContext * ctx) break; case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */ if (!(ctx->fpscr & FPSCR_PR)) { - gen_op_movl_imm_T0(0); + tcg_gen_movi_tl(cpu_T[0], 0); gen_op_fmov_T0_frN(FREG(B11_8)); return; } break; case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */ if (!(ctx->fpscr & FPSCR_PR)) { - gen_op_movl_imm_T0(0x3f800000); + tcg_gen_movi_tl(cpu_T[0], 0x3f800000); gen_op_fmov_T0_frN(FREG(B11_8)); return; } |