diff options
| author | j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-10-14 07:07:08 +0000 |
|---|---|---|
| committer | j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-10-14 07:07:08 +0000 |
| commit | 6ebbf390003270afece028facef4d9834df81a8c (patch) | |
| tree | adc8e9a3d586d5b1b550543fceb6ffdaeda03f6a /target-mips/helper.c | |
| parent | d0f48074dbc21248f3b0a9fb48126cb0d95991b5 (diff) | |
Replace is_user variable with mmu_idx in softmmu core,
allowing support of more than 2 mmu access modes.
Add backward compatibility is_user variable in targets code when needed.
Implement per target cpu_mmu_index function, avoiding duplicated code
and #ifdef TARGET_xxx in softmmu core functions.
Implement per target mmu modes definitions. As an example, add PowerPC
hypervisor mode definition and Alpha executive and kernel modes definitions.
Optimize PowerPC case, precomputing mmu_idx when MSR register changes
and using the same definition in code translation code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3384 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/helper.c')
| -rw-r--r-- | target-mips/helper.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target-mips/helper.c b/target-mips/helper.c index a881876ff2..45874d4462 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -229,7 +229,7 @@ void cpu_mips_init_mmu (CPUState *env) #endif /* !defined(CONFIG_USER_ONLY) */ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, - int is_user, int is_softmmu) + int mmu_idx, int is_softmmu) { target_ulong physical; int prot; @@ -241,8 +241,8 @@ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, #if 0 cpu_dump_state(env, logfile, fprintf, 0); #endif - fprintf(logfile, "%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d is_user %d smmu %d\n", - __func__, env->PC[env->current_tc], address, rw, is_user, is_softmmu); + fprintf(logfile, "%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d smmu %d\n", + __func__, env->PC[env->current_tc], address, rw, mmu_idx, is_softmmu); } rw &= 1; @@ -265,7 +265,7 @@ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, if (ret == TLBRET_MATCH) { ret = tlb_set_page(env, address & TARGET_PAGE_MASK, physical & TARGET_PAGE_MASK, prot, - is_user, is_softmmu); + mmu_idx, is_softmmu); } else if (ret < 0) { do_fault: switch (ret) { |