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authorNathan Rossi <nathan.rossi@xilinx.com>2014-04-08 18:52:39 -0700
committerStefan Hajnoczi <stefanha@redhat.com>2014-04-25 13:40:10 +0200
commitf663faac3e2e9d9134415f75d429ae30432e6038 (patch)
tree74af6becd3675ca3f88aad100c07244da59600e7 /hw
parentb925965294e8cf370a922ca0504c21877e748e70 (diff)
net: xilinx_axienet.c: Add phy soft reset bit clearing
Clear the BMCR Reset when writing to registers. Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com> [ PC: * Trivial style fixes to commit message ] Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Diffstat (limited to 'hw')
-rw-r--r--hw/net/xilinx_axienet.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
index 839d97ca86..0f485a0283 100644
--- a/hw/net/xilinx_axienet.c
+++ b/hw/net/xilinx_axienet.c
@@ -142,6 +142,9 @@ tdk_write(struct PHY *phy, unsigned int req, unsigned int data)
phy->regs[regnum] = data;
break;
}
+
+ /* Unconditionally clear regs[BMCR][BMCR_RESET] */
+ phy->regs[0] &= ~0x8000;
}
static void