diff options
| author | malc <av1474@comtv.ru> | 2009-10-01 22:20:47 +0400 |
|---|---|---|
| committer | malc <av1474@comtv.ru> | 2009-10-01 22:45:02 +0400 |
| commit | 99a0949b720a0936da2052cb9a46db04ffc6db29 (patch) | |
| tree | f9e39633853e35b49fc4465337cc196b9650866e | |
| parent | bc6291a1b95a2c4c546fde6e5cb4c68366f06649 (diff) | |
Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the time
being.
Signed-off-by: malc <av1474@comtv.ru>
316 files changed, 3327 insertions, 3334 deletions
diff --git a/CODING_STYLE b/CODING_STYLE index a579cb1b5f..08af61ad1f 100644 --- a/CODING_STYLE +++ b/CODING_STYLE @@ -40,14 +40,10 @@ Rationale: 3. Naming -Variables are lower_case_with_underscores; easy to type and read. Structured -type names are in CamelCase; harder to type but standing out. Scalar type -names are lower_case_with_underscores_ending_with_a_t, like the POSIX -uint64_t and family. Note that this last convention contradicts POSIX -and is therefore likely to be changed. - -Typedefs are used to eliminate the redundant 'struct' keyword. It is the -QEMU coding style. +Variables are lower_case_with_underscores; easy to type and read. +Structured type names are in CamelCase; harder to type but standing +out. Scalar type names are a_lower_case_beginning_with_an a or an. +Do not use _t suffix if you are including any headers. 4. Block structure @@ -16,12 +16,12 @@ #include "cpu-defs.h" -typedef ram_addr_t (QEMUBalloonEvent)(void *opaque, ram_addr_t target); +typedef a_ram_addr (QEMUBalloonEvent)(void *opaque, a_ram_addr target); void qemu_add_balloon_handler(QEMUBalloonEvent *func, void *opaque); -void qemu_balloon(ram_addr_t target); +void qemu_balloon(a_ram_addr target); -ram_addr_t qemu_balloon_status(void); +a_ram_addr qemu_balloon_status(void); #endif diff --git a/block/vvfat.c b/block/vvfat.c index 063f7318cf..6677028ced 100644 --- a/block/vvfat.c +++ b/block/vvfat.c @@ -71,12 +71,12 @@ void nonono(const char* file, int line, const char* msg) { #endif /* dynamic array functions */ -typedef struct array_t { +typedef struct array { char* pointer; unsigned int size,next,item_size; -} array_t; +} an_array; -static inline void array_init(array_t* array,unsigned int item_size) +static inline void array_init(an_array* array,unsigned int item_size) { array->pointer = NULL; array->size=0; @@ -84,7 +84,7 @@ static inline void array_init(array_t* array,unsigned int item_size) array->item_size=item_size; } -static inline void array_free(array_t* array) +static inline void array_free(an_array* array) { if(array->pointer) free(array->pointer); @@ -92,12 +92,12 @@ static inline void array_free(array_t* array) } /* does not automatically grow */ -static inline void* array_get(array_t* array,unsigned int index) { +static inline void* array_get(an_array* array,unsigned int index) { assert(index < array->next); return array->pointer + index * array->item_size; } -static inline int array_ensure_allocated(array_t* array, int index) +static inline int array_ensure_allocated(an_array* array, int index) { if((index + 1) * array->item_size > array->size) { int new_size = (index + 32) * array->item_size; @@ -111,7 +111,7 @@ static inline int array_ensure_allocated(array_t* array, int index) return 0; } -static inline void* array_get_next(array_t* array) { +static inline void* array_get_next(an_array* array) { unsigned int next = array->next; void* result; @@ -124,7 +124,7 @@ static inline void* array_get_next(array_t* array) { return result; } -static inline void* array_insert(array_t* array,unsigned int index,unsigned int count) { +static inline void* array_insert(an_array* array,unsigned int index,unsigned int count) { if((array->next+count)*array->item_size>array->size) { int increment=count*array->item_size; array->pointer=qemu_realloc(array->pointer,array->size+increment); @@ -141,7 +141,7 @@ static inline void* array_insert(array_t* array,unsigned int index,unsigned int /* this performs a "roll", so that the element which was at index_from becomes * index_to, but the order of all other elements is preserved. */ -static inline int array_roll(array_t* array,int index_to,int index_from,int count) +static inline int array_roll(an_array* array,int index_to,int index_from,int count) { char* buf; char* from; @@ -174,7 +174,7 @@ static inline int array_roll(array_t* array,int index_to,int index_from,int coun return 0; } -static inline int array_remove_slice(array_t* array,int index, int count) +static inline int array_remove_slice(an_array* array,int index, int count) { assert(index >=0); assert(count > 0); @@ -185,13 +185,13 @@ static inline int array_remove_slice(array_t* array,int index, int count) return 0; } -static int array_remove(array_t* array,int index) +static int array_remove(an_array* array,int index) { return array_remove_slice(array, index, 1); } /* return the index for a given member */ -static int array_index(array_t* array, void* pointer) +static int array_index(an_array* array, void* pointer) { size_t offset = (char*)pointer - array->pointer; assert((offset % array->item_size) == 0); @@ -202,7 +202,7 @@ static int array_index(array_t* array, void* pointer) /* These structures are used to fake a disk and the VFAT filesystem. * For this reason we need to use __attribute__((packed)). */ -typedef struct bootsector_t { +typedef struct bootsector { uint8_t jump[3]; uint8_t name[8]; uint16_t sector_size; @@ -238,32 +238,32 @@ typedef struct bootsector_t { uint8_t fat_type[8]; uint8_t ignored[0x1c0]; uint8_t magic[2]; -} __attribute__((packed)) bootsector_t; +} __attribute__((packed)) a_bootsector; typedef struct { uint8_t head; uint8_t sector; uint8_t cylinder; -} mbr_chs_t; +} a_mbr_chs; -typedef struct partition_t { +typedef struct partition { uint8_t attributes; /* 0x80 = bootable */ - mbr_chs_t start_CHS; + a_mbr_chs start_CHS; uint8_t fs_type; /* 0x1 = FAT12, 0x6 = FAT16, 0xe = FAT16_LBA, 0xb = FAT32, 0xc = FAT32_LBA */ - mbr_chs_t end_CHS; + a_mbr_chs end_CHS; uint32_t start_sector_long; uint32_t length_sector_long; -} __attribute__((packed)) partition_t; +} __attribute__((packed)) a_partition; -typedef struct mbr_t { +typedef struct mbr { uint8_t ignored[0x1b8]; uint32_t nt_id; uint8_t ignored2[2]; - partition_t partition[4]; + a_partition partition[4]; uint8_t magic[2]; -} __attribute__((packed)) mbr_t; +} __attribute__((packed)) a_mbr; -typedef struct direntry_t { +typedef struct direntry { uint8_t name[8]; uint8_t extension[3]; uint8_t attributes; @@ -276,11 +276,11 @@ typedef struct direntry_t { uint16_t mdate; uint16_t begin; uint32_t size; -} __attribute__((packed)) direntry_t; +} __attribute__((packed)) a_direntry; /* this structure are used to transparently access the files */ -typedef struct mapping_t { +typedef struct mapping { /* begin is the first cluster, end is the last+1 */ uint32_t begin,end; /* as s->directory is growable, no pointer may be used here */ @@ -308,11 +308,11 @@ typedef struct mapping_t { MODE_DIRECTORY = 4, MODE_FAKED = 8, MODE_DELETED = 16, MODE_RENAMED = 32 } mode; int read_only; -} mapping_t; +} a_mapping; #ifdef DEBUG -static void print_direntry(const struct direntry_t*); -static void print_mapping(const struct mapping_t* mapping); +static void print_direntry(const struct a_direntry*); +static void print_mapping(const struct a_mapping* mapping); #endif /* here begins the real VVFAT driver */ @@ -323,7 +323,7 @@ typedef struct BDRVVVFATState { unsigned char first_sectors[0x40*0x200]; int fat_type; /* 16 or 32 */ - array_t fat,directory,mapping; + an_array fat,directory,mapping; unsigned int cluster_size; unsigned int sectors_per_cluster; @@ -336,7 +336,7 @@ typedef struct BDRVVVFATState { uint32_t max_fat_value; int current_fd; - mapping_t* current_mapping; + a_mapping* current_mapping; unsigned char* cluster; /* points to current cluster */ unsigned char* cluster_buffer; /* points to a buffer to hold temp data */ unsigned int current_cluster; @@ -347,7 +347,7 @@ typedef struct BDRVVVFATState { BlockDriverState* qcow; void* fat2; char* used_clusters; - array_t commits; + an_array commits; const char* path; int downcase_short_names; } BDRVVVFATState; @@ -356,7 +356,7 @@ typedef struct BDRVVVFATState { * if the position is outside the specified geometry, fill maximum value for CHS * and return 1 to signal overflow. */ -static int sector2CHS(BlockDriverState* bs, mbr_chs_t * chs, int spos){ +static int sector2CHS(BlockDriverState* bs, a_mbr_chs * chs, int spos){ int head,sector; sector = spos % (bs->secs); spos/= bs->secs; head = spos % (bs->heads); spos/= bs->heads; @@ -378,8 +378,8 @@ static int sector2CHS(BlockDriverState* bs, mbr_chs_t * chs, int spos){ static void init_mbr(BDRVVVFATState* s) { /* TODO: if the files mbr.img and bootsect.img exist, use them */ - mbr_t* real_mbr=(mbr_t*)s->first_sectors; - partition_t* partition = &(real_mbr->partition[0]); + a_mbr* real_mbr=(a_mbr*)s->first_sectors; + a_partition* partition = &(real_mbr->partition[0]); int lba; memset(s->first_sectors,0,512); @@ -425,12 +425,12 @@ static inline int short2long_name(char* dest,const char* src) return len; } -static inline direntry_t* create_long_filename(BDRVVVFATState* s,const char* filename) +static inline a_direntry* create_long_filename(BDRVVVFATState* s,const char* filename) { char buffer[258]; int length=short2long_name(buffer,filename), number_of_entries=(length+25)/26,i; - direntry_t* entry; + a_direntry* entry; for(i=0;i<number_of_entries;i++) { entry=array_get_next(&(s->directory)); @@ -450,53 +450,53 @@ static inline direntry_t* create_long_filename(BDRVVVFATState* s,const char* fil return array_get(&(s->directory),s->directory.next-number_of_entries); } -static char is_free(const direntry_t* direntry) +static char is_free(const a_direntry* direntry) { return direntry->name[0]==0xe5 || direntry->name[0]==0x00; } -static char is_volume_label(const direntry_t* direntry) +static char is_volume_label(const a_direntry* direntry) { return direntry->attributes == 0x28; } -static char is_long_name(const direntry_t* direntry) +static char is_long_name(const a_direntry* direntry) { return direntry->attributes == 0xf; } -static char is_short_name(const direntry_t* direntry) +static char is_short_name(const a_direntry* direntry) { return !is_volume_label(direntry) && !is_long_name(direntry) && !is_free(direntry); } -static char is_directory(const direntry_t* direntry) +static char is_directory(const a_direntry* direntry) { return direntry->attributes & 0x10 && direntry->name[0] != 0xe5; } -static inline char is_dot(const direntry_t* direntry) +static inline char is_dot(const a_direntry* direntry) { return is_short_name(direntry) && direntry->name[0] == '.'; } -static char is_file(const direntry_t* direntry) +static char is_file(const a_direntry* direntry) { return is_short_name(direntry) && !is_directory(direntry); } -static inline uint32_t begin_of_direntry(const direntry_t* direntry) +static inline uint32_t begin_of_direntry(const a_direntry* direntry) { return le16_to_cpu(direntry->begin)|(le16_to_cpu(direntry->begin_hi)<<16); } -static inline uint32_t filesize_of_direntry(const direntry_t* direntry) +static inline uint32_t filesize_of_direntry(const a_direntry* direntry) { return le32_to_cpu(direntry->size); } -static void set_begin_of_direntry(direntry_t* direntry, uint32_t begin) +static void set_begin_of_direntry(a_direntry* direntry, uint32_t begin) { direntry->begin = cpu_to_le16(begin & 0xffff); direntry->begin_hi = cpu_to_le16((begin >> 16) & 0xffff); @@ -504,7 +504,7 @@ static void set_begin_of_direntry(direntry_t* direntry, uint32_t begin) /* fat functions */ -static inline uint8_t fat_chksum(const direntry_t* entry) +static inline uint8_t fat_chksum(const a_direntry* entry) { uint8_t chksum=0; int i; @@ -603,12 +603,12 @@ static inline void init_fat(BDRVVVFATState* s) /* TODO: in create_short_filename, 0xe5->0x05 is not yet handled! */ /* TODO: in parse_short_filename, 0x05->0xe5 is not yet handled! */ -static inline direntry_t* create_short_and_long_name(BDRVVVFATState* s, +static inline a_direntry* create_short_and_long_name(BDRVVVFATState* s, unsigned int directory_start, const char* filename, int is_dot) { int i,j,long_index=s->directory.next; - direntry_t* entry = NULL; - direntry_t* entry_long = NULL; + a_direntry* entry = NULL; + a_direntry* entry_long = NULL; if(is_dot) { entry=array_get_next(&(s->directory)); @@ -646,7 +646,7 @@ static inline direntry_t* create_short_and_long_name(BDRVVVFATState* s, /* mangle duplicates */ while(1) { - direntry_t* entry1=array_get(&(s->directory),directory_start); + a_direntry* entry1=array_get(&(s->directory),directory_start); int j; for(;entry1<entry;entry1++) @@ -693,12 +693,12 @@ static inline direntry_t* create_short_and_long_name(BDRVVVFATState* s, */ static int read_directory(BDRVVVFATState* s, int mapping_index) { - mapping_t* mapping = array_get(&(s->mapping), mapping_index); - direntry_t* direntry; + a_mapping* mapping = array_get(&(s->mapping), mapping_index); + a_direntry* direntry; const char* dirname = mapping->path; int first_cluster = mapping->begin; int parent_index = mapping->info.dir.parent_mapping_index; - mapping_t* parent_mapping = (mapping_t*) + a_mapping* parent_mapping = (a_mapping*) (parent_index >= 0 ? array_get(&(s->mapping), parent_index) : NULL); int first_cluster_of_parent = parent_mapping ? parent_mapping->begin : -1; @@ -720,7 +720,7 @@ static int read_directory(BDRVVVFATState* s, int mapping_index) while((entry=readdir(dir))) { unsigned int length=strlen(dirname)+2+strlen(entry->d_name); char* buffer; - direntry_t* direntry; + a_direntry* direntry; struct stat st; int is_dot=!strcmp(entry->d_name,"."); int is_dotdot=!strcmp(entry->d_name,".."); @@ -762,7 +762,7 @@ static int read_directory(BDRVVVFATState* s, int mapping_index) /* create mapping for this file */ if(!is_dot && !is_dotdot && (S_ISDIR(st.st_mode) || st.st_size)) { - s->current_mapping=(mapping_t*)array_get_next(&(s->mapping)); + s->current_mapping=(a_mapping*)array_get_next(&(s->mapping)); s->current_mapping->begin=0; s->current_mapping->end=st.st_size; /* @@ -788,8 +788,8 @@ static int read_directory(BDRVVVFATState* s, int mapping_index) /* fill with zeroes up to the end of the cluster */ while(s->directory.next%(0x10*s->sectors_per_cluster)) { - direntry_t* direntry=array_get_next(&(s->directory)); - memset(direntry,0,sizeof(direntry_t)); + a_direntry* direntry=array_get_next(&(s->directory)); + memset(direntry,0,sizeof(a_direntry)); } /* TODO: if there are more entries, bootsector has to be adjusted! */ @@ -799,16 +799,16 @@ static int read_directory(BDRVVVFATState* s, int mapping_index) int cur = s->directory.next; array_ensure_allocated(&(s->directory), ROOT_ENTRIES - 1); memset(array_get(&(s->directory), cur), 0, - (ROOT_ENTRIES - cur) * sizeof(direntry_t)); + (ROOT_ENTRIES - cur) * sizeof(a_direntry)); } /* reget the mapping, since s->mapping was possibly realloc()ed */ - mapping = (mapping_t*)array_get(&(s->mapping), mapping_index); + mapping = (a_mapping*)array_get(&(s->mapping), mapping_index); first_cluster += (s->directory.next - mapping->info.dir.first_dir_index) * 0x20 / s->cluster_size; mapping->end = first_cluster; - direntry = (direntry_t*)array_get(&(s->directory), mapping->dir_index); + direntry = (a_direntry*)array_get(&(s->directory), mapping->dir_index); set_begin_of_direntry(direntry, mapping->begin); return 0; @@ -830,19 +830,19 @@ static inline uint32_t sector_offset_in_cluster(BDRVVVFATState* s,off_t sector_n } #ifdef DBG -static direntry_t* get_direntry_for_mapping(BDRVVVFATState* s,mapping_t* mapping) +static a_direntry* get_direntry_for_mapping(BDRVVVFATState* s,a_mapping* mapping) { if(mapping->mode==MODE_UNDEFINED) return 0; - return (direntry_t*)(s->directory.pointer+sizeof(direntry_t)*mapping->dir_index); + return (a_direntry*)(s->directory.pointer+sizeof(a_direntry)*mapping->dir_index); } #endif static int init_directories(BDRVVVFATState* s, const char* dirname) { - bootsector_t* bootsector; - mapping_t* mapping; + a_bootsector* bootsector; + a_mapping* mapping; unsigned int i; unsigned int cluster; @@ -861,12 +861,12 @@ static int init_directories(BDRVVVFATState* s, i = 1+s->sectors_per_cluster*0x200*8/s->fat_type; s->sectors_per_fat=(s->sector_count+i)/i; /* round up */ - array_init(&(s->mapping),sizeof(mapping_t)); - array_init(&(s->directory),sizeof(direntry_t)); + array_init(&(s->mapping),sizeof(a_mapping)); + array_init(&(s->directory),sizeof(a_direntry)); /* add volume label */ { - direntry_t* entry=array_get_next(&(s->directory)); + a_direntry* entry=array_get_next(&(s->directory)); entry->attributes=0x28; /* archive | volume label */ snprintf((char*)entry->name,11,"QEMU VVFAT"); } @@ -910,7 +910,7 @@ static int init_directories(BDRVVVFATState* s, mapping->mode=MODE_NORMAL; mapping->begin = cluster; if (mapping->end > 0) { - direntry_t* direntry = array_get(&(s->directory), + a_direntry* direntry = array_get(&(s->directory), mapping->dir_index); mapping->end = cluster + 1 + (mapping->end-1)/s->cluster_size; @@ -954,7 +954,7 @@ static int init_directories(BDRVVVFATState* s, s->current_mapping = NULL; - bootsector=(bootsector_t*)(s->first_sectors+(s->first_sectors_number-1)*0x200); + bootsector=(a_bootsector*)(s->first_sectors+(s->first_sectors_number-1)*0x200); bootsector->jump[0]=0xeb; bootsector->jump[1]=0x3e; bootsector->jump[2]=0x90; @@ -1100,7 +1100,7 @@ static inline int find_mapping_for_cluster_aux(BDRVVVFATState* s,int cluster_num { int index3=index1+1; while(1) { - mapping_t* mapping; + a_mapping* mapping; index3=(index1+index2)/2; mapping=array_get(&(s->mapping),index3); assert(mapping->begin < mapping->end); @@ -1123,10 +1123,10 @@ static inline int find_mapping_for_cluster_aux(BDRVVVFATState* s,int cluster_num } } -static inline mapping_t* find_mapping_for_cluster(BDRVVVFATState* s,int cluster_num) +static inline a_mapping* find_mapping_for_cluster(BDRVVVFATState* s,int cluster_num) { int index=find_mapping_for_cluster_aux(s,cluster_num,0,s->mapping.next); - mapping_t* mapping; + a_mapping* mapping; if(index>=s->mapping.next) return NULL; mapping=array_get(&(s->mapping),index); @@ -1140,13 +1140,13 @@ static inline mapping_t* find_mapping_for_cluster(BDRVVVFATState* s,int cluster_ * This function simply compares path == mapping->path. Since the mappings * are sorted by cluster, this is expensive: O(n). */ -static inline mapping_t* find_mapping_for_path(BDRVVVFATState* s, +static inline a_mapping* find_mapping_for_path(BDRVVVFATState* s, const char* path) { int i; for (i = 0; i < s->mapping.next; i++) { - mapping_t* mapping = array_get(&(s->mapping), i); + a_mapping* mapping = array_get(&(s->mapping), i); if (mapping->first_mapping_index < 0 && !strcmp(path, mapping->path)) return mapping; @@ -1155,7 +1155,7 @@ static inline mapping_t* find_mapping_for_path(BDRVVVFATState* s, return NULL; } -static int open_file(BDRVVVFATState* s,mapping_t* mapping) +static int open_file(BDRVVVFATState* s,a_mapping* mapping) { if(!mapping) return -1; @@ -1182,7 +1182,7 @@ static inline int read_cluster(BDRVVVFATState *s,int cluster_num) || s->current_mapping->begin>cluster_num || s->current_mapping->end<=cluster_num) { /* binary search of mappings for file */ - mapping_t* mapping=find_mapping_for_cluster(s,cluster_num); + a_mapping* mapping=find_mapping_for_cluster(s,cluster_num); assert(!mapping || (cluster_num>=mapping->begin && cluster_num<mapping->end)); @@ -1238,7 +1238,7 @@ static void hexdump(const void* address, uint32_t len) } } -static void print_direntry(const direntry_t* direntry) +static void print_direntry(const a_direntry* direntry) { int j = 0; char buffer[1024]; @@ -1270,7 +1270,7 @@ static void print_direntry(const direntry_t* direntry) } } -static void print_mapping(const mapping_t* mapping) +static void print_mapping(const a_mapping* mapping) { fprintf(stderr, "mapping (0x%x): begin, end = %d, %d, dir_index = %d, first_mapping_index = %d, name = %s, mode = 0x%x, " , (int)mapping, mapping->begin, mapping->end, mapping->dir_index, mapping->first_mapping_index, mapping->path, mapping->mode); if (mapping->mode & MODE_DIRECTORY) @@ -1346,7 +1346,7 @@ DLOG(fprintf(stderr, "sector %d not allocated\n", (int)sector_num)); * */ -typedef struct commit_t { +typedef struct commit { char* path; union { struct { uint32_t cluster; } rename; @@ -1358,14 +1358,14 @@ typedef struct commit_t { enum { ACTION_RENAME, ACTION_WRITEOUT, ACTION_NEW_FILE, ACTION_MKDIR } action; -} commit_t; +} a_commit; static void clear_commits(BDRVVVFATState* s) { int i; DLOG(fprintf(stderr, "clear_commits (%d commits)\n", s->commits.next)); for (i = 0; i < s->commits.next; i++) { - commit_t* commit = array_get(&(s->commits), i); + a_commit* commit = array_get(&(s->commits), i); assert(commit->path || commit->action == ACTION_WRITEOUT); if (commit->action != ACTION_WRITEOUT) { assert(commit->path); @@ -1379,7 +1379,7 @@ DLOG(fprintf(stderr, "clear_commits (%d commits)\n", s->commits.next)); static void schedule_rename(BDRVVVFATState* s, uint32_t cluster, char* new_path) { - commit_t* commit = array_get_next(&(s->commits)); + a_commit* commit = array_get_next(&(s->commits)); commit->path = new_path; commit->param.rename.cluster = cluster; commit->action = ACTION_RENAME; @@ -1388,7 +1388,7 @@ static void schedule_rename(BDRVVVFATState* s, static void schedule_writeout(BDRVVVFATState* s, int dir_index, uint32_t modified_offset) { - commit_t* commit = array_get_next(&(s->commits)); + a_commit* commit = array_get_next(&(s->commits)); commit->path = NULL; commit->param.writeout.dir_index = dir_index; commit->param.writeout.modified_offset = modified_offset; @@ -1398,7 +1398,7 @@ static void schedule_writeout(BDRVVVFATState* s, static void schedule_new_file(BDRVVVFATState* s, char* path, uint32_t first_cluster) { - commit_t* commit = array_get_next(&(s->commits)); + a_commit* commit = array_get_next(&(s->commits)); commit->path = path; commit->param.new_file.first_cluster = first_cluster; commit->action = ACTION_NEW_FILE; @@ -1406,7 +1406,7 @@ static void schedule_new_file(BDRVVVFATState* s, static void schedule_mkdir(BDRVVVFATState* s, uint32_t cluster, char* path) { - commit_t* commit = array_get_next(&(s->commits)); + a_commit* commit = array_get_next(&(s->commits)); commit->path = path; commit->param.mkdir.cluster = cluster; commit->action = ACTION_MKDIR; @@ -1431,7 +1431,7 @@ static void lfn_init(long_file_name* lfn) /* return 0 if parsed successfully, > 0 if no long name, < 0 if error */ static int parse_long_name(long_file_name* lfn, - const direntry_t* direntry) + const a_direntry* direntry) { int i, j, offset; const unsigned char* pointer = (const unsigned char*)direntry; @@ -1474,7 +1474,7 @@ static int parse_long_name(long_file_name* lfn, /* returns 0 if successful, >0 if no short_name, and <0 on error */ static int parse_short_name(BDRVVVFATState* s, - long_file_name* lfn, direntry_t* direntry) + long_file_name* lfn, a_direntry* direntry) { int i, j; @@ -1566,7 +1566,7 @@ static const char* get_basename(const char* path) */ typedef enum { USED_DIRECTORY = 1, USED_FILE = 2, USED_ANY = 3, USED_ALLOCATED = 4 -} used_t; +} e_used; /* * get_cluster_count_for_direntry() not only determines how many clusters @@ -1579,7 +1579,7 @@ typedef enum { * assumed to be *not* deleted (and *only* those). */ static uint32_t get_cluster_count_for_direntry(BDRVVVFATState* s, - direntry_t* direntry, const char* path) + a_direntry* direntry, const char* path) { /* * This is a little bit tricky: @@ -1605,7 +1605,7 @@ static uint32_t get_cluster_count_for_direntry(BDRVVVFATState* s, uint32_t cluster_num = begin_of_direntry(direntry); uint32_t offset = 0; int first_mapping_index = -1; - mapping_t* mapping = NULL; + a_mapping* mapping = NULL; const char* basename2 = NULL; vvfat_close_current_file(s); @@ -1730,8 +1730,8 @@ static int check_directory_consistency(BDRVVVFATState *s, { int ret = 0; unsigned char* cluster = qemu_malloc(s->cluster_size); - direntry_t* direntries = (direntry_t*)cluster; - mapping_t* mapping = find_mapping_for_cluster(s, cluster_num); + a_direntry* direntries = (a_direntry*)cluster; + a_mapping* mapping = find_mapping_for_cluster(s, cluster_num); long_file_name lfn; int path_len = strlen(path); @@ -1889,7 +1889,7 @@ DLOG(checkpoint()); * (check_directory_consistency() will unmark those still present). */ if (s->qcow) for (i = 0; i < s->mapping.next; i++) { - mapping_t* mapping = array_get(&(s->mapping), i); + a_mapping* mapping = array_get(&(s->mapping), i); if (mapping->first_mapping_index < 0) mapping->mode |= MODE_DELETED; } @@ -1929,7 +1929,7 @@ static inline void adjust_mapping_indices(BDRVVVFATState* s, int i; for (i = 0; i < s->mapping.next; i++) { - mapping_t* mapping = array_get(&(s->mapping), i); + a_mapping* mapping = array_get(&(s->mapping), i); #define ADJUST_MAPPING_INDEX(name) \ if (mapping->name >= offset) \ @@ -1942,7 +1942,7 @@ static inline void adjust_mapping_indices(BDRVVVFATState* s, } /* insert or update mapping */ -static mapping_t* insert_mapping(BDRVVVFATState* s, +static a_mapping* insert_mapping(BDRVVVFATState* s, uint32_t begin, uint32_t end) { /* @@ -1953,8 +1953,8 @@ static mapping_t* insert_mapping(BDRVVVFATState* s, * - replace name */ int index = find_mapping_for_cluster_aux(s, begin, 0, s->mapping.next); - mapping_t* mapping = NULL; - mapping_t* first_mapping = array_get(&(s->mapping), 0); + a_mapping* mapping = NULL; + a_mapping* first_mapping = array_get(&(s->mapping), 0); if (index < s->mapping.next && (mapping = array_get(&(s->mapping), index)) && mapping->begin < begin) { @@ -1971,12 +1971,12 @@ static mapping_t* insert_mapping(BDRVVVFATState* s, mapping->begin = begin; mapping->end = end; -DLOG(mapping_t* next_mapping; +DLOG(a_mapping* next_mapping; assert(index + 1 >= s->mapping.next || ((next_mapping = array_get(&(s->mapping), index + 1)) && next_mapping->begin >= end))); - if (s->current_mapping && first_mapping != (mapping_t*)s->mapping.pointer) + if (s->current_mapping && first_mapping != (a_mapping*)s->mapping.pointer) s->current_mapping = array_get(&(s->mapping), s->current_mapping - first_mapping); @@ -1985,8 +1985,8 @@ assert(index + 1 >= s->mapping.next || static int remove_mapping(BDRVVVFATState* s, int mapping_index) { - mapping_t* mapping = array_get(&(s->mapping), mapping_index); - mapping_t* first_mapping = array_get(&(s->mapping), 0); + a_mapping* mapping = array_get(&(s->mapping), mapping_index); + a_mapping* first_mapping = array_get(&(s->mapping), 0); /* free mapping */ if (mapping->first_mapping_index < 0) @@ -1998,7 +1998,7 @@ static int remove_mapping(BDRVVVFATState* s, int mapping_index) /* adjust all references to mappings */ adjust_mapping_indices(s, mapping_index, -1); - if (s->current_mapping && first_mapping != (mapping_t*)s->mapping.pointer) + if (s->current_mapping && first_mapping != (a_mapping*)s->mapping.pointer) s->current_mapping = array_get(&(s->mapping), s->current_mapping - first_mapping); @@ -2009,7 +2009,7 @@ static void adjust_dirindices(BDRVVVFATState* s, int offset, int adjust) { int i; for (i = 0; i < s->mapping.next; i++) { - mapping_t* mapping = array_get(&(s->mapping), i); + a_mapping* mapping = array_get(&(s->mapping), i); if (mapping->dir_index >= offset) mapping->dir_index += adjust; if ((mapping->mode & MODE_DIRECTORY) && @@ -2018,14 +2018,14 @@ static void adjust_dirindices(BDRVVVFATState* s, int offset, int adjust) } } -static direntry_t* insert_direntries(BDRVVVFATState* s, +static a_direntry* insert_direntries(BDRVVVFATState* s, int dir_index, int count) { /* * make room in s->directory, * adjust_dirindices */ - direntry_t* result = array_insert(&(s->directory), dir_index, count); + a_direntry* result = array_insert(&(s->directory), dir_index, count); if (result == NULL) return NULL; adjust_dirindices(s, dir_index, count); @@ -2050,8 +2050,8 @@ static int remove_direntries(BDRVVVFATState* s, int dir_index, int count) static int commit_mappings(BDRVVVFATState* s, uint32_t first_cluster, int dir_index) { - mapping_t* mapping = find_mapping_for_cluster(s, first_cluster); - direntry_t* direntry = array_get(&(s->directory), dir_index); + a_mapping* mapping = find_mapping_for_cluster(s, first_cluster); + a_direntry* direntry = array_get(&(s->directory), dir_index); uint32_t cluster = first_cluster; vvfat_close_current_file(s); @@ -2083,7 +2083,7 @@ static int commit_mappings(BDRVVVFATState* s, if (!fat_eof(s, c1)) { int i = find_mapping_for_cluster_aux(s, c1, 0, s->mapping.next); - mapping_t* next_mapping = i >= s->mapping.next ? NULL : + a_mapping* next_mapping = i >= s->mapping.next ? NULL : array_get(&(s->mapping), i); if (next_mapping == NULL || next_mapping->begin > c1) { @@ -2127,9 +2127,9 @@ static int commit_mappings(BDRVVVFATState* s, static int commit_direntries(BDRVVVFATState* s, int dir_index, int parent_mapping_index) { - direntry_t* direntry = array_get(&(s->directory), dir_index); + a_direntry* direntry = array_get(&(s->directory), dir_index); uint32_t first_cluster = dir_index == 0 ? 0 : begin_of_direntry(direntry); - mapping_t* mapping = find_mapping_for_cluster(s, first_cluster); + a_mapping* mapping = find_mapping_for_cluster(s, first_cluster); int factor = 0x10 * s->sectors_per_cluster; int old_cluster_count, new_cluster_count; @@ -2207,10 +2207,10 @@ DLOG(fprintf(stderr, "commit_direntries for %s, parent_mapping_index %d\n", mapp static int commit_one_file(BDRVVVFATState* s, int dir_index, uint32_t offset) { - direntry_t* direntry = array_get(&(s->directory), dir_index); + a_direntry* direntry = array_get(&(s->directory), dir_index); uint32_t c = begin_of_direntry(direntry); uint32_t first_cluster = c; - mapping_t* mapping = find_mapping_for_cluster(s, c); + a_mapping* mapping = find_mapping_for_cluster(s, c); uint32_t size = filesize_of_direntry(direntry); char* cluster = qemu_malloc(s->cluster_size); uint32_t i; @@ -2268,14 +2268,14 @@ static void check1(BDRVVVFATState* s) { int i; for (i = 0; i < s->mapping.next; i++) { - mapping_t* mapping = array_get(&(s->mapping), i); + a_mapping* mapping = array_get(&(s->mapping), i); if (mapping->mode & MODE_DELETED) { fprintf(stderr, "deleted\n"); continue; } assert(mapping->dir_index >= 0); assert(mapping->dir_index < s->directory.next); - direntry_t* direntry = array_get(&(s->directory), mapping->dir_index); + a_direntry* direntry = array_get(&(s->directory), mapping->dir_index); assert(mapping->begin == begin_of_direntry(direntry) || mapping->first_mapping_index >= 0); if (mapping->mode & MODE_DIRECTORY) { assert(mapping->info.dir.first_dir_index + 0x10 * s->sectors_per_cluster * (mapping->end - mapping->begin) <= s->directory.next); @@ -2291,10 +2291,10 @@ static void check2(BDRVVVFATState* s) int first_mapping = -1; for (i = 0; i < s->directory.next; i++) { - direntry_t* direntry = array_get(&(s->directory), i); + a_direntry* direntry = array_get(&(s->directory), i); if (is_short_name(direntry) && begin_of_direntry(direntry)) { - mapping_t* mapping = find_mapping_for_cluster(s, begin_of_direntry(direntry)); + a_mapping* mapping = find_mapping_for_cluster(s, begin_of_direntry(direntry)); assert(mapping); assert(mapping->dir_index == i || is_dot(direntry)); assert(mapping->begin == begin_of_direntry(direntry) || is_dot(direntry)); @@ -2305,7 +2305,7 @@ static void check2(BDRVVVFATState* s) int j, count = 0; for (j = 0; j < s->mapping.next; j++) { - mapping_t* mapping = array_get(&(s->mapping), j); + a_mapping* mapping = array_get(&(s->mapping), j); if (mapping->mode & MODE_DELETED) continue; if (mapping->mode & MODE_DIRECTORY) { @@ -2318,7 +2318,7 @@ static void check2(BDRVVVFATState* s) if (mapping->info.dir.parent_mapping_index < 0) assert(j == 0); else { - mapping_t* parent = array_get(&(s->mapping), mapping->info.dir.parent_mapping_index); + a_mapping* parent = array_get(&(s->mapping), mapping->info.dir.parent_mapping_index); assert(parent->mode & MODE_DIRECTORY); assert(parent->info.dir.first_dir_index < mapping->info.dir.first_dir_index); } @@ -2339,15 +2339,15 @@ static int handle_renames_and_mkdirs(BDRVVVFATState* s) #ifdef DEBUG fprintf(stderr, "handle_renames\n"); for (i = 0; i < s->commits.next; i++) { - commit_t* commit = array_get(&(s->commits), i); + a_commit* commit = array_get(&(s->commits), i); fprintf(stderr, "%d, %s (%d, %d)\n", i, commit->path ? commit->path : "(null)", commit->param.rename.cluster, commit->action); } #endif for (i = 0; i < s->commits.next;) { - commit_t* commit = array_get(&(s->commits), i); + a_commit* commit = array_get(&(s->commits), i); if (commit->action == ACTION_RENAME) { - mapping_t* mapping = find_mapping_for_cluster(s, + a_mapping* mapping = find_mapping_for_cluster(s, commit->param.rename.cluster); char* old_path = mapping->path; @@ -2360,7 +2360,7 @@ static int handle_renames_and_mkdirs(BDRVVVFATState* s) int l1 = strlen(mapping->path); int l2 = strlen(old_path); int diff = l1 - l2; - direntry_t* direntry = array_get(&(s->directory), + a_direntry* direntry = array_get(&(s->directory), mapping->info.dir.first_dir_index); uint32_t c = mapping->begin; int i = 0; @@ -2368,10 +2368,10 @@ static int handle_renames_and_mkdirs(BDRVVVFATState* s) /* recurse */ while (!fat_eof(s, c)) { do { - direntry_t* d = direntry + i; + a_direntry* d = direntry + i; if (is_file(d) || (is_directory(d) && !is_dot(d))) { - mapping_t* m = find_mapping_for_cluster(s, + a_mapping* m = find_mapping_for_cluster(s, begin_of_direntry(d)); int l = strlen(m->path); char* new_path = qemu_malloc(l + diff + 1); @@ -2394,7 +2394,7 @@ static int handle_renames_and_mkdirs(BDRVVVFATState* s) array_remove(&(s->commits), i); continue; } else if (commit->action == ACTION_MKDIR) { - mapping_t* mapping; + a_mapping* mapping; int j, parent_path_len; #ifdef __MINGW32__ @@ -2422,7 +2422,7 @@ static int handle_renames_and_mkdirs(BDRVVVFATState* s) parent_path_len = strlen(commit->path) - strlen(get_basename(commit->path)) - 1; for (j = 0; j < s->mapping.next; j++) { - mapping_t* m = array_get(&(s->mapping), j); + a_mapping* m = array_get(&(s->mapping), j); if (m->first_mapping_index < 0 && m != mapping && !strncmp(m->path, mapping->path, parent_path_len) && strlen(m->path) == parent_path_len) @@ -2450,17 +2450,17 @@ static int handle_commits(BDRVVVFATState* s) vvfat_close_current_file(s); for (i = 0; !fail && i < s->commits.next; i++) { - commit_t* commit = array_get(&(s->commits), i); + a_commit* commit = array_get(&(s->commits), i); switch(commit->action) { case ACTION_RENAME: case ACTION_MKDIR: assert(0); fail = -2; break; case ACTION_WRITEOUT: { - direntry_t* entry = array_get(&(s->directory), + a_direntry* entry = array_get(&(s->directory), commit->param.writeout.dir_index); uint32_t begin = begin_of_direntry(entry); - mapping_t* mapping = find_mapping_for_cluster(s, begin); + a_mapping* mapping = find_mapping_for_cluster(s, begin); assert(mapping); assert(mapping->begin == begin); @@ -2474,8 +2474,8 @@ static int handle_commits(BDRVVVFATState* s) } case ACTION_NEW_FILE: { int begin = commit->param.new_file.first_cluster; - mapping_t* mapping = find_mapping_for_cluster(s, begin); - direntry_t* entry; + a_mapping* mapping = find_mapping_for_cluster(s, begin); + a_direntry* entry; int i; /* find direntry */ @@ -2530,9 +2530,9 @@ static int handle_deletes(BDRVVVFATState* s) deleted = 0; for (i = 1; i < s->mapping.next; i++) { - mapping_t* mapping = array_get(&(s->mapping), i); + a_mapping* mapping = array_get(&(s->mapping), i); if (mapping->mode & MODE_DELETED) { - direntry_t* entry = array_get(&(s->directory), + a_direntry* entry = array_get(&(s->directory), mapping->dir_index); if (is_free(entry)) { @@ -2550,7 +2550,7 @@ static int handle_deletes(BDRVVVFATState* s) } for (j = 1; j < s->mapping.next; j++) { - mapping_t* m = array_get(&(s->mapping), j); + a_mapping* m = array_get(&(s->mapping), j); if (m->mode & MODE_DIRECTORY && m->info.dir.first_dir_index > first_dir_index && @@ -2666,7 +2666,7 @@ DLOG(checkpoint()); for (i = sector2cluster(s, sector_num); i <= sector2cluster(s, sector_num + nb_sectors - 1);) { - mapping_t* mapping = find_mapping_for_cluster(s, i); + a_mapping* mapping = find_mapping_for_cluster(s, i); if (mapping) { if (mapping->read_only) { fprintf(stderr, "Tried to write to write-protected file %s\n", @@ -2678,7 +2678,7 @@ DLOG(checkpoint()); int begin = cluster2sector(s, i); int end = begin + s->sectors_per_cluster, k; int dir_index; - const direntry_t* direntries; + const a_direntry* direntries; long_file_name lfn; lfn_init(&lfn); @@ -2689,7 +2689,7 @@ DLOG(checkpoint()); end = sector_num + nb_sectors; dir_index = mapping->dir_index + 0x10 * (begin - mapping->begin * s->sectors_per_cluster); - direntries = (direntry_t*)(buf + 0x200 * (begin - sector_num)); + direntries = (a_direntry*)(buf + 0x200 * (begin - sector_num)); for (k = 0; k < (end - begin) * 0x10; k++) { /* do not allow non-ASCII filenames */ @@ -2702,7 +2702,7 @@ DLOG(checkpoint()); (direntries[k].attributes & 1)) { if (memcmp(direntries + k, array_get(&(s->directory), dir_index + k), - sizeof(direntry_t))) { + sizeof(a_direntry))) { fprintf(stderr, "Warning: tried to write to write-protected file\n"); return -1; } @@ -2774,7 +2774,7 @@ static int enable_write_target(BDRVVVFATState *s) int size = sector2cluster(s, s->sector_count); s->used_clusters = calloc(size, 1); - array_init(&(s->commits), sizeof(commit_t)); + array_init(&(s->commits), sizeof(a_commit)); s->qcow_filename = qemu_malloc(1024); get_tmp_filename(s->qcow_filename, 1024); @@ -2833,15 +2833,15 @@ block_init(bdrv_vvfat_init); #ifdef DEBUG static void checkpoint(void) { - assert(((mapping_t*)array_get(&(vvv->mapping), 0))->end == 2); + assert(((a_mapping*)array_get(&(vvv->mapping), 0))->end == 2); check1(vvv); check2(vvv); assert(!vvv->current_mapping || vvv->current_fd || (vvv->current_mapping->mode & MODE_DIRECTORY)); #if 0 - if (((direntry_t*)vvv->directory.pointer)[1].attributes != 0xf) + if (((a_direntry*)vvv->directory.pointer)[1].attributes != 0xf) fprintf(stderr, "Nonono!\n"); - mapping_t* mapping; - direntry_t* direntry; + a_mapping* mapping; + a_direntry* direntry; assert(vvv->mapping.size >= vvv->mapping.item_size * vvv->mapping.next); assert(vvv->directory.size >= vvv->directory.item_size * vvv->directory.next); if (vvv->mapping.next<47) @@ -110,12 +110,12 @@ typedef enum { GRAPHIC_CONSOLE, TEXT_CONSOLE, TEXT_CONSOLE_FIXED_SIZE -} console_type_t; +} e_console_type; /* ??? This is mis-named. It is used for both text and graphical consoles. */ struct TextConsole { - console_type_t console_type; + e_console_type console_type; DisplayState *ds; /* Graphic console state. */ vga_hw_update_ptr hw_update; @@ -183,7 +183,7 @@ void vga_hw_screen_dump(const char *filename) active_console = previous_active_console; } -void vga_hw_text_update(console_ch_t *chardata) +void vga_hw_text_update(a_console_ch *chardata) { if (active_console && active_console->hw_text_update) active_console->hw_text_update(active_console->hw, chardata); @@ -1197,7 +1197,7 @@ static void text_console_invalidate(void *opaque) console_refresh(s); } -static void text_console_update(void *opaque, console_ch_t *chardata) +static void text_console_update(void *opaque, a_console_ch *chardata) { TextConsole *s = (TextConsole *) opaque; int i, j, src; @@ -1236,7 +1236,7 @@ static TextConsole *get_graphic_console(DisplayState *ds) return NULL; } -static TextConsole *new_console(DisplayState *ds, console_type_t console_type) +static TextConsole *new_console(DisplayState *ds, e_console_type console_type) { TextConsole *s; int i; @@ -279,8 +279,8 @@ static inline int ds_get_bytes_per_pixel(DisplayState *ds) return ds->surface->pf.bytes_per_pixel; } -typedef unsigned long console_ch_t; -static inline void console_write_ch(console_ch_t *dest, uint32_t ch) +typedef unsigned long a_console_ch; +static inline void console_write_ch(a_console_ch *dest, uint32_t ch) { cpu_to_le32wu((uint32_t *) dest, ch); } @@ -288,7 +288,7 @@ static inline void console_write_ch(console_ch_t *dest, uint32_t ch) typedef void (*vga_hw_update_ptr)(void *); typedef void (*vga_hw_invalidate_ptr)(void *); typedef void (*vga_hw_screen_dump_ptr)(void *, const char *); -typedef void (*vga_hw_text_update_ptr)(void *, console_ch_t *); +typedef void (*vga_hw_text_update_ptr)(void *, a_console_ch *); DisplayState *graphic_console_init(vga_hw_update_ptr update, vga_hw_invalidate_ptr invalidate, @@ -299,7 +299,7 @@ DisplayState *graphic_console_init(vga_hw_update_ptr update, void vga_hw_update(void); void vga_hw_invalidate(void); void vga_hw_screen_dump(const char *filename); -void vga_hw_text_update(console_ch_t *chardata); +void vga_hw_text_update(a_console_ch *chardata); int is_graphic_console(void); int is_fixedsize_console(void); @@ -814,7 +814,7 @@ void cpu_reset(CPUState *s); /* Return the physical page corresponding to a virtual one. Use it only for debugging because no protection checks are done. Return -1 if no page found. */ -target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr); +a_target_phys_addr cpu_get_phys_page_debug(CPUState *env, target_ulong addr); #define CPU_LOG_TB_OUT_ASM (1 << 0) #define CPU_LOG_TB_IN_ASM (1 << 1) @@ -847,8 +847,8 @@ int cpu_str_to_log_mask(const char *str); extern int phys_ram_fd; extern uint8_t *phys_ram_dirty; -extern ram_addr_t ram_size; -extern ram_addr_t last_ram_offset; +extern a_ram_addr ram_size; +extern a_ram_addr last_ram_offset; /* physical memory access */ @@ -876,23 +876,23 @@ int cpu_memory_rw_debug(CPUState *env, target_ulong addr, #define MIGRATION_DIRTY_FLAG 0x08 /* read dirty bit (return 0 or 1) */ -static inline int cpu_physical_memory_is_dirty(ram_addr_t addr) +static inline int cpu_physical_memory_is_dirty(a_ram_addr addr) { return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff; } -static inline int cpu_physical_memory_get_dirty(ram_addr_t addr, +static inline int cpu_physical_memory_get_dirty(a_ram_addr addr, int dirty_flags) { return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags; } -static inline void cpu_physical_memory_set_dirty(ram_addr_t addr) +static inline void cpu_physical_memory_set_dirty(a_ram_addr addr) { phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff; } -void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, +void cpu_physical_memory_reset_dirty(a_ram_addr start, a_ram_addr end, int dirty_flags); void cpu_tlb_update_dirty(CPUState *env); @@ -900,8 +900,8 @@ int cpu_physical_memory_set_dirty_tracking(int enable); int cpu_physical_memory_get_dirty_tracking(void); -int cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr, - target_phys_addr_t end_addr); +int cpu_physical_sync_dirty_bitmap(a_target_phys_addr start_addr, + a_target_phys_addr end_addr); void dump_exec_info(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); @@ -911,9 +911,9 @@ void dump_exec_info(FILE *f, * batching which can make a major impact on performance when using * virtualization. */ -void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size); +void qemu_register_coalesced_mmio(a_target_phys_addr addr, a_ram_addr size); -void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size); +void qemu_unregister_coalesced_mmio(a_target_phys_addr addr, a_ram_addr size); /*******************************************/ /* host CPU ticks (if available) */ diff --git a/cpu-common.h b/cpu-common.h index 630237203d..854f629ad4 100644 --- a/cpu-common.h +++ b/cpu-common.h @@ -10,69 +10,69 @@ #include "bswap.h" /* address in the RAM (different from a physical address) */ -typedef unsigned long ram_addr_t; +typedef unsigned long a_ram_addr; /* memory API */ -typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value); -typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr); +typedef void CPUWriteMemoryFunc(void *opaque, a_target_phys_addr addr, uint32_t value); +typedef uint32_t CPUReadMemoryFunc(void *opaque, a_target_phys_addr addr); -void cpu_register_physical_memory_offset(target_phys_addr_t start_addr, - ram_addr_t size, - ram_addr_t phys_offset, - ram_addr_t region_offset); -static inline void cpu_register_physical_memory(target_phys_addr_t start_addr, - ram_addr_t size, - ram_addr_t phys_offset) +void cpu_register_physical_memory_offset(a_target_phys_addr start_addr, + a_ram_addr size, + a_ram_addr phys_offset, + a_ram_addr region_offset); +static inline void cpu_register_physical_memory(a_target_phys_addr start_addr, + a_ram_addr size, + a_ram_addr phys_offset) { cpu_register_physical_memory_offset(start_addr, size, phys_offset, 0); } -ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr); -ram_addr_t qemu_ram_alloc(ram_addr_t); -void qemu_ram_free(ram_addr_t addr); +a_ram_addr cpu_get_physical_page_desc(a_target_phys_addr addr); +a_ram_addr qemu_ram_alloc(a_ram_addr); +void qemu_ram_free(a_ram_addr addr); /* This should only be used for ram local to a device. */ -void *qemu_get_ram_ptr(ram_addr_t addr); +void *qemu_get_ram_ptr(a_ram_addr addr); /* This should not be used by devices. */ -ram_addr_t qemu_ram_addr_from_host(void *ptr); +a_ram_addr qemu_ram_addr_from_host(void *ptr); int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read, CPUWriteMemoryFunc * const *mem_write, void *opaque); void cpu_unregister_io_memory(int table_address); -void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, +void cpu_physical_memory_rw(a_target_phys_addr addr, uint8_t *buf, int len, int is_write); -static inline void cpu_physical_memory_read(target_phys_addr_t addr, +static inline void cpu_physical_memory_read(a_target_phys_addr addr, uint8_t *buf, int len) { cpu_physical_memory_rw(addr, buf, len, 0); } -static inline void cpu_physical_memory_write(target_phys_addr_t addr, +static inline void cpu_physical_memory_write(a_target_phys_addr addr, const uint8_t *buf, int len) { cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1); } -void *cpu_physical_memory_map(target_phys_addr_t addr, - target_phys_addr_t *plen, +void *cpu_physical_memory_map(a_target_phys_addr addr, + a_target_phys_addr *plen, int is_write); -void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len, - int is_write, target_phys_addr_t access_len); +void cpu_physical_memory_unmap(void *buffer, a_target_phys_addr len, + int is_write, a_target_phys_addr access_len); void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)); void cpu_unregister_map_client(void *cookie); -uint32_t ldub_phys(target_phys_addr_t addr); -uint32_t lduw_phys(target_phys_addr_t addr); -uint32_t ldl_phys(target_phys_addr_t addr); -uint64_t ldq_phys(target_phys_addr_t addr); -void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val); -void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val); -void stb_phys(target_phys_addr_t addr, uint32_t val); -void stw_phys(target_phys_addr_t addr, uint32_t val); -void stl_phys(target_phys_addr_t addr, uint32_t val); -void stq_phys(target_phys_addr_t addr, uint64_t val); - -void cpu_physical_memory_write_rom(target_phys_addr_t addr, +uint32_t ldub_phys(a_target_phys_addr addr); +uint32_t lduw_phys(a_target_phys_addr addr); +uint32_t ldl_phys(a_target_phys_addr addr); +uint64_t ldq_phys(a_target_phys_addr addr); +void stl_phys_notdirty(a_target_phys_addr addr, uint32_t val); +void stq_phys_notdirty(a_target_phys_addr addr, uint64_t val); +void stb_phys(a_target_phys_addr addr, uint32_t val); +void stw_phys(a_target_phys_addr addr, uint32_t val); +void stl_phys(a_target_phys_addr addr, uint32_t val); +void stq_phys(a_target_phys_addr addr, uint64_t val); + +void cpu_physical_memory_write_rom(a_target_phys_addr addr, const uint8_t *buf, int len); #define IO_MEM_SHIFT 3 diff --git a/cpu-defs.h b/cpu-defs.h index 95068b5304..a48fb02132 100644 --- a/cpu-defs.h +++ b/cpu-defs.h @@ -95,15 +95,15 @@ typedef struct CPUTLBEntry { use the corresponding iotlb value. */ #if TARGET_PHYS_ADDR_BITS == 64 /* on i386 Linux make sure it is aligned */ - target_phys_addr_t addend __attribute__((aligned(8))); + a_target_phys_addr addend __attribute__((aligned(8))); #else - target_phys_addr_t addend; + a_target_phys_addr addend; #endif /* padding to get a power of two size */ uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) - (sizeof(target_ulong) * 3 + - ((-sizeof(target_ulong) * 3) & (sizeof(target_phys_addr_t) - 1)) + - sizeof(target_phys_addr_t))]; + ((-sizeof(target_ulong) * 3) & (sizeof(a_target_phys_addr) - 1)) + + sizeof(a_target_phys_addr))]; } CPUTLBEntry; #ifdef HOST_WORDS_BIGENDIAN @@ -152,7 +152,7 @@ typedef struct CPUWatchpoint { volatile sig_atomic_t exit_request; \ /* The meaning of the MMU modes is defined in the target code. */ \ CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ - target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ + a_target_phys_addr iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \ /* buffer for temporaries in the code generator */ \ long temp_buf[CPU_TEMP_BUF_NLONGS]; \ @@ -40,7 +40,7 @@ #define FONT_HEIGHT 16 #define FONT_WIDTH 8 -static console_ch_t screen[160 * 100]; +static a_console_ch screen[160 * 100]; static WINDOW *screenpad = NULL; static int width, height, gwidth, gheight, invalidate; static int px, py, sminx, sminy, smaxx, smaxy; @@ -158,7 +158,7 @@ static void curses_cursor_position(DisplayState *ds, int x, int y) #include "curses_keys.h" -static kbd_layout_t *kbd_layout = NULL; +static a_kbd_layout *kbd_layout = NULL; static int keycode2keysym[CURSES_KEYS]; static void curses_refresh(DisplayState *ds) diff --git a/curses_keys.h b/curses_keys.h index a6e41cf4e4..210a368848 100644 --- a/curses_keys.h +++ b/curses_keys.h @@ -243,7 +243,7 @@ static const int curses2keysym[CURSES_KEYS] = { }; -static const name2keysym_t name2keysym[] = { +static const a_name2keysym name2keysym[] = { /* Plain ASCII */ { "space", 0x020 }, { "exclam", 0x021 }, diff --git a/darwin-user/commpage.c b/darwin-user/commpage.c index 2b41bc5e3a..641fdb390a 100644 --- a/darwin-user/commpage.c +++ b/darwin-user/commpage.c @@ -109,7 +109,7 @@ static struct commpage_entry commpage_entries[] = COMMPAGE_ENTRY(add_atomic_word64, 0, 0x1c0, unimpl_commpage, CALL_INDIRECT | HAS_PTR), COMMPAGE_ENTRY(mach_absolute_time, 0, 0x200, unimpl_commpage, CALL_INDIRECT), - COMMPAGE_ENTRY(spinlock_try, 1, 0x220, unimpl_commpage, CALL_INDIRECT), + COMMPAGE_ENTRY(a_spinlockry, 1, 0x220, unimpl_commpage, CALL_INDIRECT), COMMPAGE_ENTRY(spinlock_lock, 1, 0x260, OSSpinLockLock, CALL_DIRECT), COMMPAGE_ENTRY(spinlock_unlock, 1, 0x2a0, OSSpinLockUnlock, CALL_DIRECT), COMMPAGE_ENTRY(pthread_getspecific, 0, 0x2c0, unimpl_commpage, CALL_INDIRECT), diff --git a/darwin-user/machload.c b/darwin-user/machload.c index 4bb5c7276a..027976b456 100644 --- a/darwin-user/machload.c +++ b/darwin-user/machload.c @@ -101,7 +101,7 @@ typedef struct mach_i386_thread_state { unsigned int es; unsigned int fs; unsigned int gs; -} mach_i386_thread_state_t; +}; void bswap_i386_thread_state(struct mach_i386_thread_state *ts) { diff --git a/darwin-user/qemu.h b/darwin-user/qemu.h index 462bbdac22..4084819d9b 100644 --- a/darwin-user/qemu.h +++ b/darwin-user/qemu.h @@ -10,7 +10,7 @@ #include "gdbstub.h" -typedef siginfo_t target_siginfo_t; +typedef siginfo_t a_target_siginfo; #define target_sigaction sigaction #ifdef TARGET_I386 struct target_pt_regs { @@ -22,7 +22,7 @@ struct syminfo; struct elf32_sym; struct elf64_sym; -typedef const char *(*lookup_symbol_t)(struct syminfo *s, target_phys_addr_t orig_addr); +typedef const char *(*lookup_symbol_t)(struct syminfo *s, a_target_phys_addr orig_addr); struct syminfo { lookup_symbol_t lookup_symbol; diff --git a/dma-helpers.c b/dma-helpers.c index 712ed897f3..3b7323f5f1 100644 --- a/dma-helpers.c +++ b/dma-helpers.c @@ -18,8 +18,8 @@ void qemu_sglist_init(QEMUSGList *qsg, int alloc_hint) qsg->size = 0; } -void qemu_sglist_add(QEMUSGList *qsg, target_phys_addr_t base, - target_phys_addr_t len) +void qemu_sglist_add(QEMUSGList *qsg, a_target_phys_addr base, + a_target_phys_addr len) { if (qsg->nsg == qsg->nalloc) { qsg->nalloc = 2 * qsg->nalloc + 1; @@ -44,7 +44,7 @@ typedef struct { uint64_t sector_num; int is_write; int sg_cur_index; - target_phys_addr_t sg_cur_byte; + a_target_phys_addr sg_cur_byte; QEMUIOVector iov; QEMUBH *bh; } DMAAIOCB; @@ -82,7 +82,7 @@ static void dma_bdrv_unmap(DMAAIOCB *dbs) static void dma_bdrv_cb(void *opaque, int ret) { DMAAIOCB *dbs = (DMAAIOCB *)opaque; - target_phys_addr_t cur_addr, cur_len; + a_target_phys_addr cur_addr, cur_len; void *mem; dbs->acb = NULL; @@ -16,20 +16,20 @@ #include "block.h" typedef struct { - target_phys_addr_t base; - target_phys_addr_t len; + a_target_phys_addr base; + a_target_phys_addr len; } ScatterGatherEntry; typedef struct { ScatterGatherEntry *sg; int nsg; int nalloc; - target_phys_addr_t size; + a_target_phys_addr size; } QEMUSGList; void qemu_sglist_init(QEMUSGList *qsg, int alloc_hint); -void qemu_sglist_add(QEMUSGList *qsg, target_phys_addr_t base, - target_phys_addr_t len); +void qemu_sglist_add(QEMUSGList *qsg, a_target_phys_addr base, + a_target_phys_addr len); void qemu_sglist_destroy(QEMUSGList *qsg); BlockDriverAIOCB *dma_bdrv_read(BlockDriverState *bs, diff --git a/dyngen-exec.h b/dyngen-exec.h index 86e61c3df1..ae744f24f3 100644 --- a/dyngen-exec.h +++ b/dyngen-exec.h @@ -37,7 +37,7 @@ #endif /* XXX: This may be wrong for 64-bit ILP32 hosts. */ -typedef void * host_reg_t; +typedef void * a_host_reg; #ifdef CONFIG_BSD typedef struct __sFILE FILE; diff --git a/exec-all.h b/exec-all.h index dd134a99f8..412b53a071 100644 --- a/exec-all.h +++ b/exec-all.h @@ -81,16 +81,16 @@ TranslationBlock *tb_gen_code(CPUState *env, void cpu_exec_init(CPUState *env); void QEMU_NORETURN cpu_loop_exit(void); int page_unprotect(target_ulong address, unsigned long pc, void *puc); -void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end, +void tb_invalidate_phys_page_range(a_target_phys_addr start, a_target_phys_addr end, int is_cpu_write_access); void tb_invalidate_page_range(target_ulong start, target_ulong end); void tlb_flush_page(CPUState *env, target_ulong addr); void tlb_flush(CPUState *env, int flush_global); int tlb_set_page_exec(CPUState *env, target_ulong vaddr, - target_phys_addr_t paddr, int prot, + a_target_phys_addr paddr, int prot, int mmu_idx, int is_softmmu); static inline int tlb_set_page(CPUState *env1, target_ulong vaddr, - target_phys_addr_t paddr, int prot, + a_target_phys_addr paddr, int prot, int mmu_idx, int is_softmmu) { if (prot & PAGE_READ) @@ -269,7 +269,7 @@ extern void *io_mem_opaque[IO_MEM_NB_ENTRIES]; #include "qemu-lock.h" -extern spinlock_t tb_lock; +extern a_spinlock tb_lock; extern int tb_invalidated_flag; @@ -83,7 +83,7 @@ int code_gen_max_blocks; TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; static int nb_tbs; /* any access to the tbs or the page table must use this lock */ -spinlock_t tb_lock = SPIN_LOCK_UNLOCKED; +a_spinlock tb_lock = SPIN_LOCK_UNLOCKED; #if defined(__arm__) || defined(__sparc_v9__) /* The prologue must be reachable with a direct jump. ARM and Sparc64 @@ -115,8 +115,8 @@ static int in_migration; typedef struct RAMBlock { uint8_t *host; - ram_addr_t offset; - ram_addr_t length; + a_ram_addr offset; + a_ram_addr length; struct RAMBlock *next; } RAMBlock; @@ -124,7 +124,7 @@ static RAMBlock *ram_blocks; /* TODO: When we implement (and use) ram deallocation (e.g. for hotplug) then we can no longer assume contiguous ram offsets, and external uses of this variable will break. */ -ram_addr_t last_ram_offset; +a_ram_addr last_ram_offset; #endif CPUState *first_cpu; @@ -153,8 +153,8 @@ typedef struct PageDesc { typedef struct PhysPageDesc { /* offset in host memory of the page + io_index in the low bits */ - ram_addr_t phys_offset; - ram_addr_t region_offset; + a_ram_addr phys_offset; + a_ram_addr region_offset; } PhysPageDesc; #define L2_BITS 10 @@ -203,13 +203,13 @@ static int tb_flush_count; static int tb_phys_invalidate_count; #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK) -typedef struct subpage_t { - target_phys_addr_t base; +typedef struct subpage { + a_target_phys_addr base; CPUReadMemoryFunc * const *mem_read[TARGET_PAGE_SIZE][4]; CPUWriteMemoryFunc * const *mem_write[TARGET_PAGE_SIZE][4]; void *opaque[TARGET_PAGE_SIZE][2][4]; - ram_addr_t region_offset[TARGET_PAGE_SIZE][2][4]; -} subpage_t; + a_ram_addr region_offset[TARGET_PAGE_SIZE][2][4]; +} a_subpage; #ifdef _WIN32 static void map_exec(void *addr, long size) @@ -346,7 +346,7 @@ static inline PageDesc *page_find(target_ulong index) return p + (index & (L2_SIZE - 1)); } -static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc) +static PhysPageDesc *phys_page_find_alloc(a_target_phys_addr index, int alloc) { void **lp, **p; PhysPageDesc *pd; @@ -385,14 +385,14 @@ static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc) return ((PhysPageDesc *)pd) + (index & (L2_SIZE - 1)); } -static inline PhysPageDesc *phys_page_find(target_phys_addr_t index) +static inline PhysPageDesc *phys_page_find(a_target_phys_addr index) { return phys_page_find_alloc(index, 0); } #if !defined(CONFIG_USER_ONLY) -static void tlb_protect_code(ram_addr_t ram_addr); -static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, +static void tlb_protect_code(a_ram_addr ram_addr); +static void tlb_unprotect_code_phys(CPUState *env, a_ram_addr ram_addr, target_ulong vaddr); #define mmap_lock() do { } while(0) #define mmap_unlock() do { } while(0) @@ -766,7 +766,7 @@ void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr) CPUState *env; PageDesc *p; unsigned int h, n1; - target_phys_addr_t phys_pc; + a_target_phys_addr phys_pc; TranslationBlock *tb1, *tb2; /* remove the TB from the hash list */ @@ -914,7 +914,7 @@ TranslationBlock *tb_gen_code(CPUState *env, the same physical page. 'is_cpu_write_access' should be true if called from a real cpu write access: the virtual CPU will exit the current TB if code is modified inside this TB. */ -void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end, +void tb_invalidate_phys_page_range(a_target_phys_addr start, a_target_phys_addr end, int is_cpu_write_access) { TranslationBlock *tb, *tb_next, *saved_tb; @@ -1021,7 +1021,7 @@ void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t } /* len must be <= 8 and start must be a multiple of len */ -static inline void tb_invalidate_phys_page_fast(target_phys_addr_t start, int len) +static inline void tb_invalidate_phys_page_fast(a_target_phys_addr start, int len) { PageDesc *p; int offset, b; @@ -1048,7 +1048,7 @@ static inline void tb_invalidate_phys_page_fast(target_phys_addr_t start, int le } #if !defined(CONFIG_SOFTMMU) -static void tb_invalidate_phys_page(target_phys_addr_t addr, +static void tb_invalidate_phys_page(a_target_phys_addr addr, unsigned long pc, void *puc) { TranslationBlock *tb; @@ -1310,9 +1310,9 @@ static void tb_reset_jump_recursive(TranslationBlock *tb) #if defined(TARGET_HAS_ICE) static void breakpoint_invalidate(CPUState *env, target_ulong pc) { - target_phys_addr_t addr; + a_target_phys_addr addr; target_ulong pd; - ram_addr_t ram_addr; + a_ram_addr ram_addr; PhysPageDesc *p; addr = cpu_get_phys_page_debug(env, pc); @@ -1533,7 +1533,7 @@ static void cpu_unlink_tb(CPUState *env) signals are used primarily to interrupt blocking syscalls. */ #else TranslationBlock *tb; - static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED; + static a_spinlock interrupt_lock = SPIN_LOCK_UNLOCKED; tb = env->current_tb; /* if the cpu is currently executing code, we must unlink it and @@ -1810,7 +1810,7 @@ void tlb_flush_page(CPUState *env, target_ulong addr) /* update the TLBs so that writes to code in the virtual page 'addr' can be detected */ -static void tlb_protect_code(ram_addr_t ram_addr) +static void tlb_protect_code(a_ram_addr ram_addr) { cpu_physical_memory_reset_dirty(ram_addr, ram_addr + TARGET_PAGE_SIZE, @@ -1819,7 +1819,7 @@ static void tlb_protect_code(ram_addr_t ram_addr) /* update the TLB so that writes in physical page 'phys_addr' are no longer tested for self modifying code */ -static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, +static void tlb_unprotect_code_phys(CPUState *env, a_ram_addr ram_addr, target_ulong vaddr) { phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] |= CODE_DIRTY_FLAG; @@ -1838,7 +1838,7 @@ static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, } /* Note: start and end must be within the same ram block. */ -void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, +void cpu_physical_memory_reset_dirty(a_ram_addr start, a_ram_addr end, int dirty_flags) { CPUState *env; @@ -1892,8 +1892,8 @@ int cpu_physical_memory_get_dirty_tracking(void) return in_migration; } -int cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr, - target_phys_addr_t end_addr) +int cpu_physical_sync_dirty_bitmap(a_target_phys_addr start_addr, + a_target_phys_addr end_addr) { int ret = 0; @@ -1904,7 +1904,7 @@ int cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr, static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry) { - ram_addr_t ram_addr; + a_ram_addr ram_addr; void *p; if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) { @@ -1952,7 +1952,7 @@ static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr) (can only happen in non SOFTMMU mode for I/O pages or pages conflicting with the host address space). */ int tlb_set_page_exec(CPUState *env, target_ulong vaddr, - target_phys_addr_t paddr, int prot, + a_target_phys_addr paddr, int prot, int mmu_idx, int is_softmmu) { PhysPageDesc *p; @@ -1960,11 +1960,11 @@ int tlb_set_page_exec(CPUState *env, target_ulong vaddr, unsigned int index; target_ulong address; target_ulong code_address; - target_phys_addr_t addend; + a_target_phys_addr addend; int ret; CPUTLBEntry *te; CPUWatchpoint *wp; - target_phys_addr_t iotlb; + a_target_phys_addr iotlb; p = phys_page_find(paddr >> TARGET_PAGE_BITS); if (!p) { @@ -2061,7 +2061,7 @@ void tlb_flush_page(CPUState *env, target_ulong addr) } int tlb_set_page_exec(CPUState *env, target_ulong vaddr, - target_phys_addr_t paddr, int prot, + a_target_phys_addr paddr, int prot, int mmu_idx, int is_softmmu) { return 0; @@ -2267,10 +2267,10 @@ static inline void tlb_set_dirty(CPUState *env, #if !defined(CONFIG_USER_ONLY) -static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, - ram_addr_t memory, ram_addr_t region_offset); -static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys, - ram_addr_t orig_memory, ram_addr_t region_offset); +static int subpage_register (a_subpage *mmio, uint32_t start, uint32_t end, + a_ram_addr memory, a_ram_addr region_offset); +static void *subpage_init (a_target_phys_addr base, a_ram_addr *phys, + a_ram_addr orig_memory, a_ram_addr region_offset); #define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \ need_subpage) \ do { \ @@ -2298,15 +2298,15 @@ static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys, start_addr and region_offset are rounded down to a page boundary before calculating this offset. This should not be a problem unless the low bits of start_addr and region_offset differ. */ -void cpu_register_physical_memory_offset(target_phys_addr_t start_addr, - ram_addr_t size, - ram_addr_t phys_offset, - ram_addr_t region_offset) +void cpu_register_physical_memory_offset(a_target_phys_addr start_addr, + a_ram_addr size, + a_ram_addr phys_offset, + a_ram_addr region_offset) { - target_phys_addr_t addr, end_addr; + a_target_phys_addr addr, end_addr; PhysPageDesc *p; CPUState *env; - ram_addr_t orig_size = size; + a_ram_addr orig_size = size; void *subpage; if (kvm_enabled()) @@ -2317,12 +2317,12 @@ void cpu_register_physical_memory_offset(target_phys_addr_t start_addr, } region_offset &= TARGET_PAGE_MASK; size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; - end_addr = start_addr + (target_phys_addr_t)size; + end_addr = start_addr + (a_target_phys_addr)size; for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) { p = phys_page_find(addr >> TARGET_PAGE_BITS); if (p && p->phys_offset != IO_MEM_UNASSIGNED) { - ram_addr_t orig_memory = p->phys_offset; - target_phys_addr_t start_addr2, end_addr2; + a_ram_addr orig_memory = p->phys_offset; + a_target_phys_addr start_addr2, end_addr2; int need_subpage = 0; CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, @@ -2353,7 +2353,7 @@ void cpu_register_physical_memory_offset(target_phys_addr_t start_addr, (phys_offset & IO_MEM_ROMD)) { phys_offset += TARGET_PAGE_SIZE; } else { - target_phys_addr_t start_addr2, end_addr2; + a_target_phys_addr start_addr2, end_addr2; int need_subpage = 0; CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, @@ -2381,7 +2381,7 @@ void cpu_register_physical_memory_offset(target_phys_addr_t start_addr, } /* XXX: temporary until new memory mapping API */ -ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr) +a_ram_addr cpu_get_physical_page_desc(a_target_phys_addr addr) { PhysPageDesc *p; @@ -2391,19 +2391,19 @@ ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr) return p->phys_offset; } -void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size) +void qemu_register_coalesced_mmio(a_target_phys_addr addr, a_ram_addr size) { if (kvm_enabled()) kvm_coalesce_mmio_region(addr, size); } -void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size) +void qemu_unregister_coalesced_mmio(a_target_phys_addr addr, a_ram_addr size) { if (kvm_enabled()) kvm_uncoalesce_mmio_region(addr, size); } -ram_addr_t qemu_ram_alloc(ram_addr_t size) +a_ram_addr qemu_ram_alloc(a_ram_addr size) { RAMBlock *new_block; @@ -2430,7 +2430,7 @@ ram_addr_t qemu_ram_alloc(ram_addr_t size) return new_block->offset; } -void qemu_ram_free(ram_addr_t addr) +void qemu_ram_free(a_ram_addr addr) { /* TODO: implement this. */ } @@ -2443,7 +2443,7 @@ void qemu_ram_free(ram_addr_t addr) It should not be used for general purpose DMA. Use cpu_physical_memory_map/cpu_physical_memory_rw instead. */ -void *qemu_get_ram_ptr(ram_addr_t addr) +void *qemu_get_ram_ptr(a_ram_addr addr) { RAMBlock *prev; RAMBlock **prevp; @@ -2474,7 +2474,7 @@ void *qemu_get_ram_ptr(ram_addr_t addr) /* Some of the softmmu routines need to translate from a host pointer (typically a TLB entry) back to a ram offset. */ -ram_addr_t qemu_ram_addr_from_host(void *ptr) +a_ram_addr qemu_ram_addr_from_host(void *ptr) { RAMBlock *prev; RAMBlock **prevp; @@ -2498,7 +2498,7 @@ ram_addr_t qemu_ram_addr_from_host(void *ptr) return block->offset + (host - block->host); } -static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr) +static uint32_t unassigned_mem_readb(void *opaque, a_target_phys_addr addr) { #ifdef DEBUG_UNASSIGNED printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); @@ -2509,7 +2509,7 @@ static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr) return 0; } -static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr) +static uint32_t unassigned_mem_readw(void *opaque, a_target_phys_addr addr) { #ifdef DEBUG_UNASSIGNED printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); @@ -2520,7 +2520,7 @@ static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr) return 0; } -static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr) +static uint32_t unassigned_mem_readl(void *opaque, a_target_phys_addr addr) { #ifdef DEBUG_UNASSIGNED printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); @@ -2531,7 +2531,7 @@ static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr) return 0; } -static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) +static void unassigned_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val) { #ifdef DEBUG_UNASSIGNED printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); @@ -2541,7 +2541,7 @@ static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_ #endif } -static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) +static void unassigned_mem_writew(void *opaque, a_target_phys_addr addr, uint32_t val) { #ifdef DEBUG_UNASSIGNED printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); @@ -2551,7 +2551,7 @@ static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_ #endif } -static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) +static void unassigned_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val) { #ifdef DEBUG_UNASSIGNED printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); @@ -2573,7 +2573,7 @@ static CPUWriteMemoryFunc * const unassigned_mem_write[3] = { unassigned_mem_writel, }; -static void notdirty_mem_writeb(void *opaque, target_phys_addr_t ram_addr, +static void notdirty_mem_writeb(void *opaque, a_target_phys_addr ram_addr, uint32_t val) { int dirty_flags; @@ -2593,7 +2593,7 @@ static void notdirty_mem_writeb(void *opaque, target_phys_addr_t ram_addr, tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); } -static void notdirty_mem_writew(void *opaque, target_phys_addr_t ram_addr, +static void notdirty_mem_writew(void *opaque, a_target_phys_addr ram_addr, uint32_t val) { int dirty_flags; @@ -2613,7 +2613,7 @@ static void notdirty_mem_writew(void *opaque, target_phys_addr_t ram_addr, tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); } -static void notdirty_mem_writel(void *opaque, target_phys_addr_t ram_addr, +static void notdirty_mem_writel(void *opaque, a_target_phys_addr ram_addr, uint32_t val) { int dirty_flags; @@ -2693,39 +2693,39 @@ static void check_watchpoint(int offset, int len_mask, int flags) /* Watchpoint access routines. Watchpoints are inserted using TLB tricks, so these check for a hit then pass through to the normal out-of-line phys routines. */ -static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr) +static uint32_t watch_mem_readb(void *opaque, a_target_phys_addr addr) { check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_READ); return ldub_phys(addr); } -static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr) +static uint32_t watch_mem_readw(void *opaque, a_target_phys_addr addr) { check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_READ); return lduw_phys(addr); } -static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr) +static uint32_t watch_mem_readl(void *opaque, a_target_phys_addr addr) { check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_READ); return ldl_phys(addr); } -static void watch_mem_writeb(void *opaque, target_phys_addr_t addr, +static void watch_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val) { check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_WRITE); stb_phys(addr, val); } -static void watch_mem_writew(void *opaque, target_phys_addr_t addr, +static void watch_mem_writew(void *opaque, a_target_phys_addr addr, uint32_t val) { check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_WRITE); stw_phys(addr, val); } -static void watch_mem_writel(void *opaque, target_phys_addr_t addr, +static void watch_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val) { check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_WRITE); @@ -2744,7 +2744,7 @@ static CPUWriteMemoryFunc * const watch_mem_write[3] = { watch_mem_writel, }; -static inline uint32_t subpage_readlen (subpage_t *mmio, target_phys_addr_t addr, +static inline uint32_t subpage_readlen (a_subpage *mmio, a_target_phys_addr addr, unsigned int len) { uint32_t ret; @@ -2761,7 +2761,7 @@ static inline uint32_t subpage_readlen (subpage_t *mmio, target_phys_addr_t addr return ret; } -static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr, +static inline void subpage_writelen (a_subpage *mmio, a_target_phys_addr addr, uint32_t value, unsigned int len) { unsigned int idx; @@ -2776,7 +2776,7 @@ static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr, value); } -static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr) +static uint32_t subpage_readb (void *opaque, a_target_phys_addr addr) { #if defined(DEBUG_SUBPAGE) printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); @@ -2785,7 +2785,7 @@ static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr) return subpage_readlen(opaque, addr, 0); } -static void subpage_writeb (void *opaque, target_phys_addr_t addr, +static void subpage_writeb (void *opaque, a_target_phys_addr addr, uint32_t value) { #if defined(DEBUG_SUBPAGE) @@ -2794,7 +2794,7 @@ static void subpage_writeb (void *opaque, target_phys_addr_t addr, subpage_writelen(opaque, addr, value, 0); } -static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr) +static uint32_t subpage_readw (void *opaque, a_target_phys_addr addr) { #if defined(DEBUG_SUBPAGE) printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); @@ -2803,7 +2803,7 @@ static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr) return subpage_readlen(opaque, addr, 1); } -static void subpage_writew (void *opaque, target_phys_addr_t addr, +static void subpage_writew (void *opaque, a_target_phys_addr addr, uint32_t value) { #if defined(DEBUG_SUBPAGE) @@ -2812,7 +2812,7 @@ static void subpage_writew (void *opaque, target_phys_addr_t addr, subpage_writelen(opaque, addr, value, 1); } -static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr) +static uint32_t subpage_readl (void *opaque, a_target_phys_addr addr) { #if defined(DEBUG_SUBPAGE) printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); @@ -2822,7 +2822,7 @@ static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr) } static void subpage_writel (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { #if defined(DEBUG_SUBPAGE) printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value); @@ -2842,8 +2842,8 @@ static CPUWriteMemoryFunc * const subpage_write[] = { &subpage_writel, }; -static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, - ram_addr_t memory, ram_addr_t region_offset) +static int subpage_register (a_subpage *mmio, uint32_t start, uint32_t end, + a_ram_addr memory, a_ram_addr region_offset) { int idx, eidx; unsigned int i; @@ -2875,13 +2875,13 @@ static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, return 0; } -static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys, - ram_addr_t orig_memory, ram_addr_t region_offset) +static void *subpage_init (a_target_phys_addr base, a_ram_addr *phys, + a_ram_addr orig_memory, a_ram_addr region_offset) { - subpage_t *mmio; + a_subpage *mmio; int subpage_memory; - mmio = qemu_mallocz(sizeof(subpage_t)); + mmio = qemu_mallocz(sizeof(a_subpage)); mmio->base = base; subpage_memory = cpu_register_io_memory(subpage_read, subpage_write, mmio); @@ -2981,7 +2981,7 @@ static void io_mem_init(void) /* physical memory access (slow version, mainly for debug) */ #if defined(CONFIG_USER_ONLY) -void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, +void cpu_physical_memory_rw(a_target_phys_addr addr, uint8_t *buf, int len, int is_write) { int l, flags; @@ -3022,13 +3022,13 @@ void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, } #else -void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, +void cpu_physical_memory_rw(a_target_phys_addr addr, uint8_t *buf, int len, int is_write) { int l, io_index; uint8_t *ptr; uint32_t val; - target_phys_addr_t page; + a_target_phys_addr page; unsigned long pd; PhysPageDesc *p; @@ -3046,7 +3046,7 @@ void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, if (is_write) { if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { - target_phys_addr_t addr1 = addr; + a_target_phys_addr addr1 = addr; io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); if (p) addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset; @@ -3085,7 +3085,7 @@ void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, } else { if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) { - target_phys_addr_t addr1 = addr; + a_target_phys_addr addr1 = addr; /* I/O case */ io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); if (p) @@ -3120,12 +3120,12 @@ void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, } /* used for ROM loading : can write in RAM and ROM */ -void cpu_physical_memory_write_rom(target_phys_addr_t addr, +void cpu_physical_memory_write_rom(a_target_phys_addr addr, const uint8_t *buf, int len) { int l; uint8_t *ptr; - target_phys_addr_t page; + a_target_phys_addr page; unsigned long pd; PhysPageDesc *p; @@ -3160,8 +3160,8 @@ void cpu_physical_memory_write_rom(target_phys_addr_t addr, typedef struct { void *buffer; - target_phys_addr_t addr; - target_phys_addr_t len; + a_target_phys_addr addr; + a_target_phys_addr len; } BounceBuffer; static BounceBuffer bounce; @@ -3211,16 +3211,16 @@ static void cpu_notify_map_clients(void) * Use cpu_register_map_client() to know when retrying the map operation is * likely to succeed. */ -void *cpu_physical_memory_map(target_phys_addr_t addr, - target_phys_addr_t *plen, +void *cpu_physical_memory_map(a_target_phys_addr addr, + a_target_phys_addr *plen, int is_write) { - target_phys_addr_t len = *plen; - target_phys_addr_t done = 0; + a_target_phys_addr len = *plen; + a_target_phys_addr done = 0; int l; uint8_t *ret = NULL; uint8_t *ptr; - target_phys_addr_t page; + a_target_phys_addr page; unsigned long pd; PhysPageDesc *p; unsigned long addr1; @@ -3270,12 +3270,12 @@ void *cpu_physical_memory_map(target_phys_addr_t addr, * Will also mark the memory as dirty if is_write == 1. access_len gives * the amount of memory that was actually read or written by the caller. */ -void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len, - int is_write, target_phys_addr_t access_len) +void cpu_physical_memory_unmap(void *buffer, a_target_phys_addr len, + int is_write, a_target_phys_addr access_len) { if (buffer != bounce.buffer) { if (is_write) { - ram_addr_t addr1 = qemu_ram_addr_from_host(buffer); + a_ram_addr addr1 = qemu_ram_addr_from_host(buffer); while (access_len) { unsigned l; l = TARGET_PAGE_SIZE; @@ -3303,7 +3303,7 @@ void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len, } /* warning: addr must be aligned */ -uint32_t ldl_phys(target_phys_addr_t addr) +uint32_t ldl_phys(a_target_phys_addr addr) { int io_index; uint8_t *ptr; @@ -3335,7 +3335,7 @@ uint32_t ldl_phys(target_phys_addr_t addr) } /* warning: addr must be aligned */ -uint64_t ldq_phys(target_phys_addr_t addr) +uint64_t ldq_phys(a_target_phys_addr addr) { int io_index; uint8_t *ptr; @@ -3373,7 +3373,7 @@ uint64_t ldq_phys(target_phys_addr_t addr) } /* XXX: optimize */ -uint32_t ldub_phys(target_phys_addr_t addr) +uint32_t ldub_phys(a_target_phys_addr addr) { uint8_t val; cpu_physical_memory_read(addr, &val, 1); @@ -3381,7 +3381,7 @@ uint32_t ldub_phys(target_phys_addr_t addr) } /* XXX: optimize */ -uint32_t lduw_phys(target_phys_addr_t addr) +uint32_t lduw_phys(a_target_phys_addr addr) { uint16_t val; cpu_physical_memory_read(addr, (uint8_t *)&val, 2); @@ -3391,7 +3391,7 @@ uint32_t lduw_phys(target_phys_addr_t addr) /* warning: addr must be aligned. The ram page is not masked as dirty and the code inside is not invalidated. It is useful if the dirty bits are used to track modified PTEs */ -void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val) +void stl_phys_notdirty(a_target_phys_addr addr, uint32_t val) { int io_index; uint8_t *ptr; @@ -3427,7 +3427,7 @@ void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val) } } -void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val) +void stq_phys_notdirty(a_target_phys_addr addr, uint64_t val) { int io_index; uint8_t *ptr; @@ -3460,7 +3460,7 @@ void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val) } /* warning: addr must be aligned */ -void stl_phys(target_phys_addr_t addr, uint32_t val) +void stl_phys(a_target_phys_addr addr, uint32_t val) { int io_index; uint8_t *ptr; @@ -3496,21 +3496,21 @@ void stl_phys(target_phys_addr_t addr, uint32_t val) } /* XXX: optimize */ -void stb_phys(target_phys_addr_t addr, uint32_t val) +void stb_phys(a_target_phys_addr addr, uint32_t val) { uint8_t v = val; cpu_physical_memory_write(addr, &v, 1); } /* XXX: optimize */ -void stw_phys(target_phys_addr_t addr, uint32_t val) +void stw_phys(a_target_phys_addr addr, uint32_t val) { uint16_t v = tswap16(val); cpu_physical_memory_write(addr, (const uint8_t *)&v, 2); } /* XXX: optimize */ -void stq_phys(target_phys_addr_t addr, uint64_t val) +void stq_phys(a_target_phys_addr addr, uint64_t val) { val = tswap64(val); cpu_physical_memory_write(addr, (const uint8_t *)&val, 8); @@ -3523,7 +3523,7 @@ int cpu_memory_rw_debug(CPUState *env, target_ulong addr, uint8_t *buf, int len, int is_write) { int l; - target_phys_addr_t phys_addr; + a_target_phys_addr phys_addr; target_ulong page; while (len > 0) { diff --git a/hostregs_helper.h b/hostregs_helper.h index 3a0bece81c..fa94292c1c 100644 --- a/hostregs_helper.h +++ b/hostregs_helper.h @@ -27,8 +27,8 @@ #if defined(DECLARE_HOST_REGS) #define DO_REG(REG) \ - register host_reg_t reg_AREG##REG asm(AREG##REG); \ - volatile host_reg_t saved_AREG##REG; + register a_host_reg reg_AREG##REG asm(AREG##REG); \ + volatile a_host_reg saved_AREG##REG; #elif defined(SAVE_HOST_REGS) diff --git a/hw/an5206.c b/hw/an5206.c index a4b83b0f44..2a458b7ef6 100644 --- a/hw/an5206.c +++ b/hw/an5206.c @@ -29,7 +29,7 @@ void irq_info(Monitor *mon) /* Board init. */ -static void an5206_init(ram_addr_t ram_size, +static void an5206_init(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -37,7 +37,7 @@ static void an5206_init(ram_addr_t ram_size, CPUState *env; int kernel_size; uint64_t elf_entry; - target_phys_addr_t entry; + a_target_phys_addr entry; if (!cpu_model) cpu_model = "m5206"; diff --git a/hw/apb_pci.c b/hw/apb_pci.c index eb77042503..6bb0324728 100644 --- a/hw/apb_pci.c +++ b/hw/apb_pci.c @@ -39,7 +39,7 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0) #define APB_DPRINTF(fmt, ...) #endif -typedef target_phys_addr_t pci_addr_t; +typedef a_target_phys_addr a_pci_addr; #include "pci_host.h" typedef struct APBState { @@ -47,7 +47,7 @@ typedef struct APBState { PCIHostState host_state; } APBState; -static void pci_apb_config_writel (void *opaque, target_phys_addr_t addr, +static void pci_apb_config_writel (void *opaque, a_target_phys_addr addr, uint32_t val) { APBState *s = opaque; @@ -61,7 +61,7 @@ static void pci_apb_config_writel (void *opaque, target_phys_addr_t addr, } static uint32_t pci_apb_config_readl (void *opaque, - target_phys_addr_t addr) + a_target_phys_addr addr) { APBState *s = opaque; uint32_t val; @@ -87,7 +87,7 @@ static CPUReadMemoryFunc * const pci_apb_config_read[] = { &pci_apb_config_readl, }; -static void apb_config_writel (void *opaque, target_phys_addr_t addr, +static void apb_config_writel (void *opaque, a_target_phys_addr addr, uint32_t val) { //PCIBus *s = opaque; @@ -105,7 +105,7 @@ static void apb_config_writel (void *opaque, target_phys_addr_t addr, } static uint32_t apb_config_readl (void *opaque, - target_phys_addr_t addr) + a_target_phys_addr addr) { //PCIBus *s = opaque; uint32_t val; @@ -148,25 +148,25 @@ static CPUReadMemoryFunc * const pci_apb_read[] = { &pci_host_data_readl, }; -static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr, +static void pci_apb_iowriteb (void *opaque, a_target_phys_addr addr, uint32_t val) { cpu_outb(addr & IOPORTS_MASK, val); } -static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr, +static void pci_apb_iowritew (void *opaque, a_target_phys_addr addr, uint32_t val) { cpu_outw(addr & IOPORTS_MASK, val); } -static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr, +static void pci_apb_iowritel (void *opaque, a_target_phys_addr addr, uint32_t val) { cpu_outl(addr & IOPORTS_MASK, val); } -static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr) +static uint32_t pci_apb_ioreadb (void *opaque, a_target_phys_addr addr) { uint32_t val; @@ -174,7 +174,7 @@ static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr) return val; } -static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr) +static uint32_t pci_apb_ioreadw (void *opaque, a_target_phys_addr addr) { uint32_t val; @@ -182,7 +182,7 @@ static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr) return val; } -static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr) +static uint32_t pci_apb_ioreadl (void *opaque, a_target_phys_addr addr) { uint32_t val; @@ -226,8 +226,8 @@ static void pci_apb_set_irq(void *opaque, int irq_num, int level) qemu_set_irq(pic[irq_num], level); } -PCIBus *pci_apb_init(target_phys_addr_t special_base, - target_phys_addr_t mem_base, +PCIBus *pci_apb_init(a_target_phys_addr special_base, + a_target_phys_addr mem_base, qemu_irq *pic, PCIBus **bus2, PCIBus **bus3) { DeviceState *dev; @@ -661,25 +661,25 @@ static void apic_timer(void *opaque) apic_timer_update(s, s->next_time); } -static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr) +static uint32_t apic_mem_readb(void *opaque, a_target_phys_addr addr) { return 0; } -static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr) +static uint32_t apic_mem_readw(void *opaque, a_target_phys_addr addr) { return 0; } -static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) +static void apic_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val) { } -static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) +static void apic_mem_writew(void *opaque, a_target_phys_addr addr, uint32_t val) { } -static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr) +static uint32_t apic_mem_readl(void *opaque, a_target_phys_addr addr) { CPUState *env; APICState *s; @@ -760,7 +760,7 @@ static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr) return val; } -static void apic_send_msi(target_phys_addr_t addr, uint32 data) +static void apic_send_msi(a_target_phys_addr addr, uint32 data) { uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT; uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT; @@ -771,7 +771,7 @@ static void apic_send_msi(target_phys_addr_t addr, uint32 data) apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode); } -static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) +static void apic_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val) { CPUState *env; APICState *s; diff --git a/hw/arm-misc.h b/hw/arm-misc.h index 367dd25c0b..bc67ebde15 100644 --- a/hw/arm-misc.h +++ b/hw/arm-misc.h @@ -26,8 +26,8 @@ struct arm_boot_info { const char *kernel_filename; const char *kernel_cmdline; const char *initrd_filename; - target_phys_addr_t loader_start; - target_phys_addr_t smp_loader_start; + a_target_phys_addr loader_start; + a_target_phys_addr smp_loader_start; int nb_cpus; int board_id; int (*atag_board)(struct arm_boot_info *info, void *p); diff --git a/hw/arm_boot.c b/hw/arm_boot.c index a8a38c5a36..ef5d2083b5 100644 --- a/hw/arm_boot.c +++ b/hw/arm_boot.c @@ -61,9 +61,9 @@ static void main_cpu_reset(void *opaque) } while (0) static void set_kernel_args(struct arm_boot_info *info, - int initrd_size, target_phys_addr_t base) + int initrd_size, a_target_phys_addr base) { - target_phys_addr_t p; + a_target_phys_addr p; p = base + KERNEL_ARGS_ADDR; /* ATAG_CORE */ @@ -114,9 +114,9 @@ static void set_kernel_args(struct arm_boot_info *info, } static void set_kernel_args_old(struct arm_boot_info *info, - int initrd_size, target_phys_addr_t base) + int initrd_size, a_target_phys_addr base) { - target_phys_addr_t p; + a_target_phys_addr p; const char *s; @@ -193,7 +193,7 @@ void arm_load_kernel(CPUState *env, struct arm_boot_info *info) int n; int is_linux = 0; uint64_t elf_entry; - target_phys_addr_t entry; + a_target_phys_addr entry; int big_endian; /* Load the kernel. */ diff --git a/hw/arm_gic.c b/hw/arm_gic.c index 12f5109924..a466ba4bdf 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -238,7 +238,7 @@ static void gic_complete_irq(gic_state * s, int cpu, int irq) } } -static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset) +static uint32_t gic_dist_readb(void *opaque, a_target_phys_addr offset) { gic_state *s = (gic_state *)opaque; uint32_t res; @@ -348,7 +348,7 @@ bad_reg: return 0; } -static uint32_t gic_dist_readw(void *opaque, target_phys_addr_t offset) +static uint32_t gic_dist_readw(void *opaque, a_target_phys_addr offset) { uint32_t val; val = gic_dist_readb(opaque, offset); @@ -356,7 +356,7 @@ static uint32_t gic_dist_readw(void *opaque, target_phys_addr_t offset) return val; } -static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset) +static uint32_t gic_dist_readl(void *opaque, a_target_phys_addr offset) { uint32_t val; #ifdef NVIC @@ -371,7 +371,7 @@ static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset) return val; } -static void gic_dist_writeb(void *opaque, target_phys_addr_t offset, +static void gic_dist_writeb(void *opaque, a_target_phys_addr offset, uint32_t value) { gic_state *s = (gic_state *)opaque; @@ -509,14 +509,14 @@ bad_reg: hw_error("gic_dist_writeb: Bad offset %x\n", (int)offset); } -static void gic_dist_writew(void *opaque, target_phys_addr_t offset, +static void gic_dist_writew(void *opaque, a_target_phys_addr offset, uint32_t value) { gic_dist_writeb(opaque, offset, value & 0xff); gic_dist_writeb(opaque, offset + 1, value >> 8); } -static void gic_dist_writel(void *opaque, target_phys_addr_t offset, +static void gic_dist_writel(void *opaque, a_target_phys_addr offset, uint32_t value) { gic_state *s = (gic_state *)opaque; diff --git a/hw/arm_sysctl.c b/hw/arm_sysctl.c index 26300ef8ad..624f1128ca 100644 --- a/hw/arm_sysctl.c +++ b/hw/arm_sysctl.c @@ -27,7 +27,7 @@ typedef struct { uint32_t resetlevel; } arm_sysctl_state; -static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset) +static uint32_t arm_sysctl_read(void *opaque, a_target_phys_addr offset) { arm_sysctl_state *s = (arm_sysctl_state *)opaque; @@ -104,7 +104,7 @@ static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset) } } -static void arm_sysctl_write(void *opaque, target_phys_addr_t offset, +static void arm_sysctl_write(void *opaque, a_target_phys_addr offset, uint32_t val) { arm_sysctl_state *s = (arm_sysctl_state *)opaque; diff --git a/hw/arm_timer.c b/hw/arm_timer.c index 9fef191cbc..0bb3591a9d 100644 --- a/hw/arm_timer.c +++ b/hw/arm_timer.c @@ -42,7 +42,7 @@ static void arm_timer_update(arm_timer_state *s) } } -static uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset) +static uint32_t arm_timer_read(void *opaque, a_target_phys_addr offset) { arm_timer_state *s = (arm_timer_state *)opaque; @@ -84,7 +84,7 @@ static void arm_timer_recalibrate(arm_timer_state *s, int reload) ptimer_set_limit(s->timer, limit, reload); } -static void arm_timer_write(void *opaque, target_phys_addr_t offset, +static void arm_timer_write(void *opaque, a_target_phys_addr offset, uint32_t value) { arm_timer_state *s = (arm_timer_state *)opaque; @@ -199,7 +199,7 @@ static void sp804_set_irq(void *opaque, int irq, int level) qemu_set_irq(s->irq, s->level[0] || s->level[1]); } -static uint32_t sp804_read(void *opaque, target_phys_addr_t offset) +static uint32_t sp804_read(void *opaque, a_target_phys_addr offset) { sp804_state *s = (sp804_state *)opaque; @@ -211,7 +211,7 @@ static uint32_t sp804_read(void *opaque, target_phys_addr_t offset) } } -static void sp804_write(void *opaque, target_phys_addr_t offset, +static void sp804_write(void *opaque, a_target_phys_addr offset, uint32_t value) { sp804_state *s = (sp804_state *)opaque; @@ -283,7 +283,7 @@ typedef struct { arm_timer_state *timer[3]; } icp_pit_state; -static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset) +static uint32_t icp_pit_read(void *opaque, a_target_phys_addr offset) { icp_pit_state *s = (icp_pit_state *)opaque; int n; @@ -297,7 +297,7 @@ static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset) return arm_timer_read(s->timer[n], offset & 0xff); } -static void icp_pit_write(void *opaque, target_phys_addr_t offset, +static void icp_pit_write(void *opaque, a_target_phys_addr offset, uint32_t value) { icp_pit_state *s = (icp_pit_state *)opaque; diff --git a/hw/armv7m.c b/hw/armv7m.c index a96288d0dd..0f40b406ca 100644 --- a/hw/armv7m.c +++ b/hw/armv7m.c @@ -26,14 +26,14 @@ static inline uint32_t bitband_addr(void * opaque, uint32_t addr) } -static uint32_t bitband_readb(void *opaque, target_phys_addr_t offset) +static uint32_t bitband_readb(void *opaque, a_target_phys_addr offset) { uint8_t v; cpu_physical_memory_read(bitband_addr(opaque, offset), &v, 1); return (v & (1 << ((offset >> 2) & 7))) != 0; } -static void bitband_writeb(void *opaque, target_phys_addr_t offset, +static void bitband_writeb(void *opaque, a_target_phys_addr offset, uint32_t value) { uint32_t addr; @@ -49,7 +49,7 @@ static void bitband_writeb(void *opaque, target_phys_addr_t offset, cpu_physical_memory_write(addr, &v, 1); } -static uint32_t bitband_readw(void *opaque, target_phys_addr_t offset) +static uint32_t bitband_readw(void *opaque, a_target_phys_addr offset) { uint32_t addr; uint16_t mask; @@ -61,7 +61,7 @@ static uint32_t bitband_readw(void *opaque, target_phys_addr_t offset) return (v & mask) != 0; } -static void bitband_writew(void *opaque, target_phys_addr_t offset, +static void bitband_writew(void *opaque, a_target_phys_addr offset, uint32_t value) { uint32_t addr; @@ -78,7 +78,7 @@ static void bitband_writew(void *opaque, target_phys_addr_t offset, cpu_physical_memory_write(addr, (uint8_t *)&v, 2); } -static uint32_t bitband_readl(void *opaque, target_phys_addr_t offset) +static uint32_t bitband_readl(void *opaque, a_target_phys_addr offset) { uint32_t addr; uint32_t mask; @@ -90,7 +90,7 @@ static uint32_t bitband_readl(void *opaque, target_phys_addr_t offset) return (v & mask) != 0; } -static void bitband_writel(void *opaque, target_phys_addr_t offset, +static void bitband_writel(void *opaque, a_target_phys_addr offset, uint32_t value) { uint32_t addr; diff --git a/hw/axis_dev88.c b/hw/axis_dev88.c index 81a41c9446..5ceb653920 100644 --- a/hw/axis_dev88.c +++ b/hw/axis_dev88.c @@ -44,7 +44,7 @@ struct nand_state_t }; static struct nand_state_t nand_state; -static uint32_t nand_readl (void *opaque, target_phys_addr_t addr) +static uint32_t nand_readl (void *opaque, a_target_phys_addr addr) { struct nand_state_t *s = opaque; uint32_t r; @@ -59,7 +59,7 @@ static uint32_t nand_readl (void *opaque, target_phys_addr_t addr) } static void -nand_writel (void *opaque, target_phys_addr_t addr, uint32_t value) +nand_writel (void *opaque, a_target_phys_addr addr, uint32_t value) { struct nand_state_t *s = opaque; int rdy; @@ -168,7 +168,7 @@ static struct gpio_state_t uint32_t regs[0x5c / 4]; } gpio_state; -static uint32_t gpio_readl (void *opaque, target_phys_addr_t addr) +static uint32_t gpio_readl (void *opaque, a_target_phys_addr addr) { struct gpio_state_t *s = opaque; uint32_t r = 0; @@ -197,7 +197,7 @@ static uint32_t gpio_readl (void *opaque, target_phys_addr_t addr) D(printf("%s %x=%x\n", __func__, addr, r)); } -static void gpio_writel (void *opaque, target_phys_addr_t addr, uint32_t value) +static void gpio_writel (void *opaque, a_target_phys_addr addr, uint32_t value) { struct gpio_state_t *s = opaque; D(printf("%s %x=%x\n", __func__, addr, value)); @@ -250,7 +250,7 @@ static void main_cpu_reset(void *opaque) } static -void axisdev88_init (ram_addr_t ram_size, +void axisdev88_init (a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -265,8 +265,8 @@ void axisdev88_init (ram_addr_t ram_size, int i; int nand_regs; int gpio_regs; - ram_addr_t phys_ram; - ram_addr_t phys_intmem; + a_ram_addr phys_ram; + a_ram_addr phys_intmem; /* init CPUs */ if (cpu_model == NULL) { diff --git a/hw/boards.h b/hw/boards.h index d8893413d4..68414d7990 100644 --- a/hw/boards.h +++ b/hw/boards.h @@ -5,7 +5,7 @@ #include "qdev.h" -typedef void QEMUMachineInitFunc(ram_addr_t ram_size, +typedef void QEMUMachineInitFunc(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, diff --git a/hw/bt-hci-csr.c b/hw/bt-hci-csr.c index 7300ea6799..892801e00a 100644 --- a/hw/bt-hci-csr.c +++ b/hw/bt-hci-csr.c @@ -44,7 +44,7 @@ struct csrhci_s { QEMUTimer *out_tm; int64_t baud_delay; - bdaddr_t bd_addr; + a_bdaddr bd_addr; struct HCIInfo *hci; }; @@ -398,7 +398,7 @@ static void csrhci_reset(struct csrhci_s *s) /* After a while... (but sooner than 10ms) */ s->modem_state |= CHR_TIOCM_CTS; - memset(&s->bd_addr, 0, sizeof(bdaddr_t)); + memset(&s->bd_addr, 0, sizeof(a_bdaddr)); } static void csrhci_out_tick(void *opaque) diff --git a/hw/bt-hci.c b/hw/bt-hci.c index 669866a5c3..f70dba0f51 100644 --- a/hw/bt-hci.c +++ b/hw/bt-hci.c @@ -62,7 +62,7 @@ struct bt_hci_s { uint32_t role_bmp; int last_handle; int connecting; - bdaddr_t awaiting_bdaddr[HCI_HANDLES_MAX]; + a_bdaddr awaiting_bdaddr[HCI_HANDLES_MAX]; } lm; uint8_t event_mask[8]; @@ -672,7 +672,7 @@ static void bt_hci_lmp_link_teardown(struct bt_hci_s *hci, uint16_t handle) } } -static int bt_hci_connect(struct bt_hci_s *hci, bdaddr_t *bdaddr) +static int bt_hci_connect(struct bt_hci_s *hci, a_bdaddr *bdaddr) { struct bt_device_s *slave; struct bt_link_s link; @@ -706,7 +706,7 @@ static void bt_hci_connection_reject(struct bt_hci_s *hci, } static void bt_hci_connection_reject_event(struct bt_hci_s *hci, - bdaddr_t *bdaddr) + a_bdaddr *bdaddr) { evt_conn_complete params; @@ -808,7 +808,7 @@ static void bt_hci_conn_accept_timeout(void *opaque) * that's been cancelled by the host in the meantime and immediately * try to detach the link and send a Connection Complete. */ static int bt_hci_lmp_connection_ready(struct bt_hci_s *hci, - bdaddr_t *bdaddr) + a_bdaddr *bdaddr) { int i; @@ -939,7 +939,7 @@ static void bt_hci_lmp_disconnect_slave(struct bt_link_s *btlink) ¶ms, EVT_DISCONN_COMPLETE_SIZE); } -static int bt_hci_name_req(struct bt_hci_s *hci, bdaddr_t *bdaddr) +static int bt_hci_name_req(struct bt_hci_s *hci, a_bdaddr *bdaddr) { struct bt_device_s *slave; evt_remote_name_req_complete params; @@ -1290,7 +1290,7 @@ static inline void bt_hci_event_complete_status(struct bt_hci_s *hci, } static inline void bt_hci_event_complete_conn_cancel(struct bt_hci_s *hci, - uint8_t status, bdaddr_t *bd_addr) + uint8_t status, a_bdaddr *bd_addr) { create_conn_cancel_rp params = { .status = status, @@ -1324,7 +1324,7 @@ static inline void bt_hci_event_encrypt_change(struct bt_hci_s *hci, } static inline void bt_hci_event_complete_name_cancel(struct bt_hci_s *hci, - bdaddr_t *bd_addr) + a_bdaddr *bd_addr) { remote_name_req_cancel_rp params = { .status = HCI_INVALID_PARAMETERS, @@ -2134,7 +2134,7 @@ static int bt_hci_bdaddr_set(struct HCIInfo *info, const uint8_t *bd_addr) { struct bt_hci_s *hci = hci_from_info(info); - bacpy(&hci->device.bd_addr, (const bdaddr_t *) bd_addr); + bacpy(&hci->device.bd_addr, (const a_bdaddr *) bd_addr); return 0; } @@ -26,20 +26,20 @@ /* BD Address */ typedef struct { uint8_t b[6]; -} __attribute__((packed)) bdaddr_t; +} __attribute__((packed)) a_bdaddr; -#define BDADDR_ANY (&(bdaddr_t) {{0, 0, 0, 0, 0, 0}}) -#define BDADDR_ALL (&(bdaddr_t) {{0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}) -#define BDADDR_LOCAL (&(bdaddr_t) {{0, 0, 0, 0xff, 0xff, 0xff}}) +#define BDADDR_ANY (&(a_bdaddr) {{0, 0, 0, 0, 0, 0}}) +#define BDADDR_ALL (&(a_bdaddr) {{0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}) +#define BDADDR_LOCAL (&(a_bdaddr) {{0, 0, 0, 0xff, 0xff, 0xff}}) /* Copy, swap, convert BD Address */ -static inline int bacmp(const bdaddr_t *ba1, const bdaddr_t *ba2) +static inline int bacmp(const a_bdaddr *ba1, const a_bdaddr *ba2) { - return memcmp(ba1, ba2, sizeof(bdaddr_t)); + return memcmp(ba1, ba2, sizeof(a_bdaddr)); } -static inline void bacpy(bdaddr_t *dst, const bdaddr_t *src) +static inline void bacpy(a_bdaddr *dst, const a_bdaddr *src) { - memcpy(dst, src, sizeof(bdaddr_t)); + memcpy(dst, src, sizeof(a_bdaddr)); } #define BAINIT(orig) { .b = { \ @@ -71,7 +71,7 @@ struct bt_link_s { struct bt_device_s { int lt_addr; - bdaddr_t bd_addr; + a_bdaddr bd_addr; int mtu; int setup; struct bt_scatternet_s *net; @@ -451,7 +451,7 @@ typedef struct { typedef struct { uint8_t status; - bdaddr_t bdaddr; + a_bdaddr bdaddr; } __attribute__ ((packed)) status_bdaddr_rp; #define STATUS_BDADDR_RP_SIZE 7 @@ -471,7 +471,7 @@ typedef struct { #define OCF_CREATE_CONN 0x0005 typedef struct { - bdaddr_t bdaddr; + a_bdaddr bdaddr; uint16_t pkt_type; uint8_t pscan_rep_mode; uint8_t pscan_mode; @@ -497,33 +497,33 @@ typedef struct { #define OCF_CREATE_CONN_CANCEL 0x0008 typedef struct { uint8_t status; - bdaddr_t bdaddr; + a_bdaddr bdaddr; } __attribute__ ((packed)) create_conn_cancel_cp; #define CREATE_CONN_CANCEL_CP_SIZE 6 typedef struct { uint8_t status; - bdaddr_t bdaddr; + a_bdaddr bdaddr; } __attribute__ ((packed)) create_conn_cancel_rp; #define CREATE_CONN_CANCEL_RP_SIZE 7 #define OCF_ACCEPT_CONN_REQ 0x0009 typedef struct { - bdaddr_t bdaddr; + a_bdaddr bdaddr; uint8_t role; } __attribute__ ((packed)) accept_conn_req_cp; #define ACCEPT_CONN_REQ_CP_SIZE 7 #define OCF_REJECT_CONN_REQ 0x000A typedef struct { - bdaddr_t bdaddr; + a_bdaddr bdaddr; uint8_t reason; } __attribute__ ((packed)) reject_conn_req_cp; #define REJECT_CONN_REQ_CP_SIZE 7 #define OCF_LINK_KEY_REPLY 0x000B typedef struct { - bdaddr_t bdaddr; + a_bdaddr bdaddr; uint8_t link_key[16]; } __attribute__ ((packed)) link_key_reply_cp; #define LINK_KEY_REPLY_CP_SIZE 22 @@ -532,7 +532,7 @@ typedef struct { #define OCF_PIN_CODE_REPLY 0x000D typedef struct { - bdaddr_t bdaddr; + a_bdaddr bdaddr; uint8_t pin_len; uint8_t pin_code[16]; } __attribute__ ((packed)) pin_code_reply_cp; @@ -574,7 +574,7 @@ typedef struct { #define OCF_REMOTE_NAME_REQ 0x0019 typedef struct { - bdaddr_t bdaddr; + a_bdaddr bdaddr; uint8_t pscan_rep_mode; uint8_t pscan_mode; uint16_t clock_offset; @@ -583,13 +583,13 @@ typedef struct { #define OCF_REMOTE_NAME_REQ_CANCEL 0x001A typedef struct { - bdaddr_t bdaddr; + a_bdaddr bdaddr; } __attribute__ ((packed)) remote_name_req_cancel_cp; #define REMOTE_NAME_REQ_CANCEL_CP_SIZE 6 typedef struct { uint8_t status; - bdaddr_t bdaddr; + a_bdaddr bdaddr; } __attribute__ ((packed)) remote_name_req_cancel_rp; #define REMOTE_NAME_REQ_CANCEL_RP_SIZE 7 @@ -646,7 +646,7 @@ typedef struct { #define OCF_ACCEPT_SYNC_CONN_REQ 0x0029 typedef struct { - bdaddr_t bdaddr; + a_bdaddr bdaddr; uint32_t tx_bandwith; uint32_t rx_bandwith; uint16_t max_latency; @@ -658,7 +658,7 @@ typedef struct { #define OCF_REJECT_SYNC_CONN_REQ 0x002A typedef struct { - bdaddr_t bdaddr; + a_bdaddr bdaddr; uint8_t reason; } __attribute__ ((packed)) reject_sync_conn_req_cp; #define REJECT_SYNC_CONN_REQ_CP_SIZE 7 @@ -734,7 +734,7 @@ typedef struct { #define OCF_SWITCH_ROLE 0x000B typedef struct { - bdaddr_t bdaddr; + a_bdaddr bdaddr; uint8_t role; } __attribute__ ((packed)) switch_role_cp; #define SWITCH_ROLE_CP_SIZE 7 @@ -847,7 +847,7 @@ typedef struct { #define OCF_READ_STORED_LINK_KEY 0x000D typedef struct { - bdaddr_t bdaddr; + a_bdaddr bdaddr; uint8_t read_all; } __attribute__ ((packed)) read_stored_link_key_cp; #define READ_STORED_LINK_KEY_CP_SIZE 7 @@ -872,7 +872,7 @@ typedef struct { #define OCF_DELETE_STORED_LINK_KEY 0x0012 typedef struct { - bdaddr_t bdaddr; + a_bdaddr bdaddr; uint8_t delete_all; } __attribute__ ((packed)) delete_stored_link_key_cp; #define DELETE_STORED_LINK_KEY_CP_SIZE 7 @@ -1238,7 +1238,7 @@ typedef struct { #define OCF_READ_BD_ADDR 0x0009 typedef struct { uint8_t status; - bdaddr_t bdaddr; + a_bdaddr bdaddr; } __attribute__ ((packed)) read_bd_addr_rp; #define READ_BD_ADDR_RP_SIZE 7 @@ -1317,7 +1317,7 @@ typedef struct { #define EVT_INQUIRY_RESULT 0x02 typedef struct { uint8_t num_responses; - bdaddr_t bdaddr; + a_bdaddr bdaddr; uint8_t pscan_rep_mode; uint8_t pscan_period_mode; uint8_t pscan_mode; @@ -1330,7 +1330,7 @@ typedef struct { typedef struct { uint8_t status; uint16_t handle; - bdaddr_t bdaddr; + a_bdaddr bdaddr; uint8_t link_type; uint8_t encr_mode; } __attribute__ ((packed)) evt_conn_complete; @@ -1338,7 +1338,7 @@ typedef struct { #define EVT_CONN_REQUEST 0x04 typedef struct { - bdaddr_t bdaddr; + a_bdaddr bdaddr; uint8_t dev_class[3]; uint8_t link_type; } __attribute__ ((packed)) evt_conn_request; @@ -1362,7 +1362,7 @@ typedef struct { #define EVT_REMOTE_NAME_REQ_COMPLETE 0x07 typedef struct { uint8_t status; - bdaddr_t bdaddr; + a_bdaddr bdaddr; char name[248]; } __attribute__ ((packed)) evt_remote_name_req_complete; #define EVT_REMOTE_NAME_REQ_COMPLETE_SIZE 255 @@ -1447,7 +1447,7 @@ typedef struct { #define EVT_ROLE_CHANGE 0x12 typedef struct { uint8_t status; - bdaddr_t bdaddr; + a_bdaddr bdaddr; uint8_t role; } __attribute__ ((packed)) evt_role_change; #define EVT_ROLE_CHANGE_SIZE 8 @@ -1480,19 +1480,19 @@ typedef struct { #define EVT_PIN_CODE_REQ 0x16 typedef struct { - bdaddr_t bdaddr; + a_bdaddr bdaddr; } __attribute__ ((packed)) evt_pin_code_req; #define EVT_PIN_CODE_REQ_SIZE 6 #define EVT_LINK_KEY_REQ 0x17 typedef struct { - bdaddr_t bdaddr; + a_bdaddr bdaddr; } __attribute__ ((packed)) evt_link_key_req; #define EVT_LINK_KEY_REQ_SIZE 6 #define EVT_LINK_KEY_NOTIFY 0x18 typedef struct { - bdaddr_t bdaddr; + a_bdaddr bdaddr; uint8_t link_key[16]; uint8_t key_type; } __attribute__ ((packed)) evt_link_key_notify; @@ -1537,7 +1537,7 @@ typedef struct { #define EVT_PSCAN_REP_MODE_CHANGE 0x20 typedef struct { - bdaddr_t bdaddr; + a_bdaddr bdaddr; uint8_t pscan_rep_mode; } __attribute__ ((packed)) evt_pscan_rep_mode_change; #define EVT_PSCAN_REP_MODE_CHANGE_SIZE 7 @@ -1555,7 +1555,7 @@ typedef struct { #define EVT_INQUIRY_RESULT_WITH_RSSI 0x22 typedef struct { uint8_t num_responses; - bdaddr_t bdaddr; + a_bdaddr bdaddr; uint8_t pscan_rep_mode; uint8_t pscan_period_mode; uint8_t dev_class[3]; @@ -1565,7 +1565,7 @@ typedef struct { #define INQUIRY_INFO_WITH_RSSI_SIZE 15 typedef struct { uint8_t num_responses; - bdaddr_t bdaddr; + a_bdaddr bdaddr; uint8_t pscan_rep_mode; uint8_t pscan_period_mode; uint8_t pscan_mode; @@ -1589,7 +1589,7 @@ typedef struct { typedef struct { uint8_t status; uint16_t handle; - bdaddr_t bdaddr; + a_bdaddr bdaddr; uint8_t link_type; uint8_t trans_interval; uint8_t retrans_window; @@ -1623,7 +1623,7 @@ typedef struct { #define EVT_EXTENDED_INQUIRY_RESULT 0x2F typedef struct { - bdaddr_t bdaddr; + a_bdaddr bdaddr; uint8_t pscan_rep_mode; uint8_t pscan_period_mode; uint8_t dev_class[3]; diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c index 7e95f10bdb..09bd10cfce 100644 --- a/hw/cirrus_vga.c +++ b/hw/cirrus_vga.c @@ -1214,7 +1214,7 @@ static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index) /* Thinking about changing bank base? First, drop the dirty bitmap information * on the current location, otherwise we lose this pointer forever */ if (s->vga.lfb_vram_mapped) { - target_phys_addr_t base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000; + a_target_phys_addr base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000; cpu_physical_sync_dirty_bitmap(base_addr, base_addr + 0x8000); } s->cirrus_bank_base[bank_index] = offset; @@ -1988,7 +1988,7 @@ static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s, * ***************************************/ -static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr) +static uint32_t cirrus_vga_mem_readb(void *opaque, a_target_phys_addr addr) { CirrusVGAState *s = opaque; unsigned bank_index; @@ -2032,7 +2032,7 @@ static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr) return val; } -static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr) +static uint32_t cirrus_vga_mem_readw(void *opaque, a_target_phys_addr addr) { uint32_t v; #ifdef TARGET_WORDS_BIGENDIAN @@ -2045,7 +2045,7 @@ static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr) return v; } -static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr) +static uint32_t cirrus_vga_mem_readl(void *opaque, a_target_phys_addr addr) { uint32_t v; #ifdef TARGET_WORDS_BIGENDIAN @@ -2062,7 +2062,7 @@ static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr) return v; } -static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr, +static void cirrus_vga_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t mem_value) { CirrusVGAState *s = opaque; @@ -2127,7 +2127,7 @@ static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr, } } -static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) +static void cirrus_vga_mem_writew(void *opaque, a_target_phys_addr addr, uint32_t val) { #ifdef TARGET_WORDS_BIGENDIAN cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff); @@ -2138,7 +2138,7 @@ static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_ #endif } -static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) +static void cirrus_vga_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val) { #ifdef TARGET_WORDS_BIGENDIAN cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff); @@ -2341,7 +2341,7 @@ static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y) * ***************************************/ -static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr) +static uint32_t cirrus_linear_readb(void *opaque, a_target_phys_addr addr) { CirrusVGAState *s = opaque; uint32_t ret; @@ -2369,7 +2369,7 @@ static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr) return ret; } -static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr) +static uint32_t cirrus_linear_readw(void *opaque, a_target_phys_addr addr) { uint32_t v; #ifdef TARGET_WORDS_BIGENDIAN @@ -2382,7 +2382,7 @@ static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr) return v; } -static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr) +static uint32_t cirrus_linear_readl(void *opaque, a_target_phys_addr addr) { uint32_t v; #ifdef TARGET_WORDS_BIGENDIAN @@ -2399,7 +2399,7 @@ static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr) return v; } -static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr, +static void cirrus_linear_writeb(void *opaque, a_target_phys_addr addr, uint32_t val) { CirrusVGAState *s = opaque; @@ -2440,7 +2440,7 @@ static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr, } } -static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr, +static void cirrus_linear_writew(void *opaque, a_target_phys_addr addr, uint32_t val) { #ifdef TARGET_WORDS_BIGENDIAN @@ -2452,7 +2452,7 @@ static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr, #endif } -static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr, +static void cirrus_linear_writel(void *opaque, a_target_phys_addr addr, uint32_t val) { #ifdef TARGET_WORDS_BIGENDIAN @@ -2488,7 +2488,7 @@ static CPUWriteMemoryFunc * const cirrus_linear_write[3] = { ***************************************/ -static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr) +static uint32_t cirrus_linear_bitblt_readb(void *opaque, a_target_phys_addr addr) { uint32_t ret; @@ -2497,7 +2497,7 @@ static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr return ret; } -static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr) +static uint32_t cirrus_linear_bitblt_readw(void *opaque, a_target_phys_addr addr) { uint32_t v; #ifdef TARGET_WORDS_BIGENDIAN @@ -2510,7 +2510,7 @@ static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr return v; } -static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr) +static uint32_t cirrus_linear_bitblt_readl(void *opaque, a_target_phys_addr addr) { uint32_t v; #ifdef TARGET_WORDS_BIGENDIAN @@ -2527,7 +2527,7 @@ static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr return v; } -static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr, +static void cirrus_linear_bitblt_writeb(void *opaque, a_target_phys_addr addr, uint32_t val) { CirrusVGAState *s = opaque; @@ -2541,7 +2541,7 @@ static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr, } } -static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr, +static void cirrus_linear_bitblt_writew(void *opaque, a_target_phys_addr addr, uint32_t val) { #ifdef TARGET_WORDS_BIGENDIAN @@ -2553,7 +2553,7 @@ static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr, #endif } -static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr, +static void cirrus_linear_bitblt_writel(void *opaque, a_target_phys_addr addr, uint32_t val) { #ifdef TARGET_WORDS_BIGENDIAN @@ -2855,7 +2855,7 @@ static void cirrus_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) * ***************************************/ -static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr) +static uint32_t cirrus_mmio_readb(void *opaque, a_target_phys_addr addr) { CirrusVGAState *s = opaque; @@ -2868,7 +2868,7 @@ static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr) } } -static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr) +static uint32_t cirrus_mmio_readw(void *opaque, a_target_phys_addr addr) { uint32_t v; #ifdef TARGET_WORDS_BIGENDIAN @@ -2881,7 +2881,7 @@ static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr) return v; } -static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr) +static uint32_t cirrus_mmio_readl(void *opaque, a_target_phys_addr addr) { uint32_t v; #ifdef TARGET_WORDS_BIGENDIAN @@ -2898,7 +2898,7 @@ static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr) return v; } -static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr, +static void cirrus_mmio_writeb(void *opaque, a_target_phys_addr addr, uint32_t val) { CirrusVGAState *s = opaque; @@ -2912,7 +2912,7 @@ static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr, } } -static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr, +static void cirrus_mmio_writew(void *opaque, a_target_phys_addr addr, uint32_t val) { #ifdef TARGET_WORDS_BIGENDIAN @@ -2924,7 +2924,7 @@ static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr, #endif } -static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr, +static void cirrus_mmio_writel(void *opaque, a_target_phys_addr addr, uint32_t val) { #ifdef TARGET_WORDS_BIGENDIAN diff --git a/hw/cs4231.c b/hw/cs4231.c index 843f86ed65..e4708f8777 100644 --- a/hw/cs4231.c +++ b/hw/cs4231.c @@ -64,7 +64,7 @@ static void cs_reset(void *opaque) s->dregs[25] = CS_VER; } -static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr) +static uint32_t cs_mem_readl(void *opaque, a_target_phys_addr addr) { CSState *s = opaque; uint32_t saddr, ret; @@ -90,7 +90,7 @@ static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr) return ret; } -static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) +static void cs_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val) { CSState *s = opaque; uint32_t saddr; @@ -250,7 +250,7 @@ static void cuda_timer1(void *opaque) cuda_update_irq(s); } -static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr) +static uint32_t cuda_readb(void *opaque, a_target_phys_addr addr) { CUDAState *s = opaque; uint32_t val; @@ -321,7 +321,7 @@ static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr) return val; } -static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) +static void cuda_writeb(void *opaque, a_target_phys_addr addr, uint32_t val) { CUDAState *s = opaque; @@ -612,20 +612,20 @@ static void cuda_receive_packet_from_host(CUDAState *s, } } -static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value) +static void cuda_writew (void *opaque, a_target_phys_addr addr, uint32_t value) { } -static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value) +static void cuda_writel (void *opaque, a_target_phys_addr addr, uint32_t value) { } -static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr) +static uint32_t cuda_readw (void *opaque, a_target_phys_addr addr) { return 0; } -static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr) +static uint32_t cuda_readl (void *opaque, a_target_phys_addr addr) { return 0; } @@ -401,7 +401,7 @@ void DMA_register_channel (int nchan, int DMA_read_memory (int nchan, void *buf, int pos, int len) { struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3]; - target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; + a_target_phys_addr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; if (r->mode & 0x20) { int i; @@ -423,7 +423,7 @@ int DMA_read_memory (int nchan, void *buf, int pos, int len) int DMA_write_memory (int nchan, void *buf, int pos, int len) { struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3]; - target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; + a_target_phys_addr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; if (r->mode & 0x20) { int i; diff --git a/hw/dp8393x.c b/hw/dp8393x.c index 067831d1dc..a972970b71 100644 --- a/hw/dp8393x.c +++ b/hw/dp8393x.c @@ -166,7 +166,7 @@ typedef struct dp8393xState { int loopback_packet; /* Memory access */ - void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write); + void (*memory_rw)(void *opaque, a_target_phys_addr addr, uint8_t *buf, int len, int is_write); void* mem_opaque; } dp8393xState; @@ -601,7 +601,7 @@ static void dp8393x_watchdog(void *opaque) dp8393x_update_irq(s); } -static uint32_t dp8393x_readw(void *opaque, target_phys_addr_t addr) +static uint32_t dp8393x_readw(void *opaque, a_target_phys_addr addr) { dp8393xState *s = opaque; int reg; @@ -614,13 +614,13 @@ static uint32_t dp8393x_readw(void *opaque, target_phys_addr_t addr) return read_register(s, reg); } -static uint32_t dp8393x_readb(void *opaque, target_phys_addr_t addr) +static uint32_t dp8393x_readb(void *opaque, a_target_phys_addr addr) { uint16_t v = dp8393x_readw(opaque, addr & ~0x1); return (v >> (8 * (addr & 0x1))) & 0xff; } -static uint32_t dp8393x_readl(void *opaque, target_phys_addr_t addr) +static uint32_t dp8393x_readl(void *opaque, a_target_phys_addr addr) { uint32_t v; v = dp8393x_readw(opaque, addr); @@ -628,7 +628,7 @@ static uint32_t dp8393x_readl(void *opaque, target_phys_addr_t addr) return v; } -static void dp8393x_writew(void *opaque, target_phys_addr_t addr, uint32_t val) +static void dp8393x_writew(void *opaque, a_target_phys_addr addr, uint32_t val) { dp8393xState *s = opaque; int reg; @@ -642,7 +642,7 @@ static void dp8393x_writew(void *opaque, target_phys_addr_t addr, uint32_t val) write_register(s, reg, (uint16_t)val); } -static void dp8393x_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) +static void dp8393x_writeb(void *opaque, a_target_phys_addr addr, uint32_t val) { uint16_t old_val = dp8393x_readw(opaque, addr & ~0x1); @@ -657,7 +657,7 @@ static void dp8393x_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) dp8393x_writew(opaque, addr & ~0x1, val); } -static void dp8393x_writel(void *opaque, target_phys_addr_t addr, uint32_t val) +static void dp8393x_writel(void *opaque, a_target_phys_addr addr, uint32_t val) { dp8393x_writew(opaque, addr, val & 0xffff); dp8393x_writew(opaque, addr + 2, (val >> 16) & 0xffff); @@ -872,9 +872,9 @@ static void nic_cleanup(VLANClientState *vc) qemu_free(s); } -void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift, +void dp83932_init(NICInfo *nd, a_target_phys_addr base, int it_shift, qemu_irq irq, void* mem_opaque, - void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write)) + void (*memory_rw)(void *opaque, a_target_phys_addr addr, uint8_t *buf, int len, int is_write)) { dp8393xState *s; diff --git a/hw/ds1225y.c b/hw/ds1225y.c index 009d127455..b3dbc46c81 100644 --- a/hw/ds1225y.c +++ b/hw/ds1225y.c @@ -34,12 +34,12 @@ typedef struct ds1225y_t QEMUFile *file; uint8_t *contents; uint8_t protection; -} ds1225y_t; +} a_ds1225y; -static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr) +static uint32_t nvram_readb (void *opaque, a_target_phys_addr addr) { - ds1225y_t *s = opaque; + a_ds1225y *s = opaque; uint32_t val; val = s->contents[addr]; @@ -50,7 +50,7 @@ static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr) return val; } -static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr) +static uint32_t nvram_readw (void *opaque, a_target_phys_addr addr) { uint32_t v; v = nvram_readb(opaque, addr); @@ -58,7 +58,7 @@ static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr) return v; } -static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr) +static uint32_t nvram_readl (void *opaque, a_target_phys_addr addr) { uint32_t v; v = nvram_readb(opaque, addr); @@ -68,9 +68,9 @@ static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr) return v; } -static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t val) +static void nvram_writeb (void *opaque, a_target_phys_addr addr, uint32_t val) { - ds1225y_t *s = opaque; + a_ds1225y *s = opaque; #ifdef DEBUG_NVRAM printf("nvram: write 0x%x at " TARGET_FMT_lx "\n", val, addr); @@ -84,13 +84,13 @@ static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t val) } } -static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t val) +static void nvram_writew (void *opaque, a_target_phys_addr addr, uint32_t val) { nvram_writeb(opaque, addr, val & 0xff); nvram_writeb(opaque, addr + 1, (val >> 8) & 0xff); } -static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t val) +static void nvram_writel (void *opaque, a_target_phys_addr addr, uint32_t val) { nvram_writeb(opaque, addr, val & 0xff); nvram_writeb(opaque, addr + 1, (val >> 8) & 0xff); @@ -98,9 +98,9 @@ static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t val) nvram_writeb(opaque, addr + 3, (val >> 24) & 0xff); } -static void nvram_writeb_protected (void *opaque, target_phys_addr_t addr, uint32_t val) +static void nvram_writeb_protected (void *opaque, a_target_phys_addr addr, uint32_t val) { - ds1225y_t *s = opaque; + a_ds1225y *s = opaque; if (s->protection != 7) { #ifdef DEBUG_NVRAM @@ -112,13 +112,13 @@ static void nvram_writeb_protected (void *opaque, target_phys_addr_t addr, uint3 nvram_writeb(opaque, addr, val); } -static void nvram_writew_protected (void *opaque, target_phys_addr_t addr, uint32_t val) +static void nvram_writew_protected (void *opaque, a_target_phys_addr addr, uint32_t val) { nvram_writeb_protected(opaque, addr, val & 0xff); nvram_writeb_protected(opaque, addr + 1, (val >> 8) & 0xff); } -static void nvram_writel_protected (void *opaque, target_phys_addr_t addr, uint32_t val) +static void nvram_writel_protected (void *opaque, a_target_phys_addr addr, uint32_t val) { nvram_writeb_protected(opaque, addr, val & 0xff); nvram_writeb_protected(opaque, addr + 1, (val >> 8) & 0xff); @@ -145,13 +145,13 @@ static CPUWriteMemoryFunc * const nvram_write_protected[] = { }; /* Initialisation routine */ -void *ds1225y_init(target_phys_addr_t mem_base, const char *filename) +void *ds1225y_init(a_target_phys_addr mem_base, const char *filename) { - ds1225y_t *s; + a_ds1225y *s; int mem_indexRW, mem_indexRP; QEMUFile *file; - s = qemu_mallocz(sizeof(ds1225y_t)); + s = qemu_mallocz(sizeof(a_ds1225y)); s->chip_size = 0x2000; /* Fixed for ds1225y chip: 8 KiB */ s->contents = qemu_mallocz(s->chip_size); s->protection = 7; diff --git a/hw/dummy_m68k.c b/hw/dummy_m68k.c index ce45a597db..10e5741d46 100644 --- a/hw/dummy_m68k.c +++ b/hw/dummy_m68k.c @@ -16,7 +16,7 @@ /* Board init. */ -static void dummy_m68k_init(ram_addr_t ram_size, +static void dummy_m68k_init(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -24,7 +24,7 @@ static void dummy_m68k_init(ram_addr_t ram_size, CPUState *env; int kernel_size; uint64_t elf_entry; - target_phys_addr_t entry; + a_target_phys_addr entry; if (!cpu_model) cpu_model = "cfv4e"; diff --git a/hw/e1000.c b/hw/e1000.c index 95c471c625..e4a241f4e0 100644 --- a/hw/e1000.c +++ b/hw/e1000.c @@ -478,7 +478,7 @@ process_tx_desc(E1000State *s, struct e1000_tx_desc *dp) } static uint32_t -txdesc_writeback(target_phys_addr_t base, struct e1000_tx_desc *dp) +txdesc_writeback(a_target_phys_addr base, struct e1000_tx_desc *dp) { uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data); @@ -495,7 +495,7 @@ txdesc_writeback(target_phys_addr_t base, struct e1000_tx_desc *dp) static void start_xmit(E1000State *s) { - target_phys_addr_t base; + a_target_phys_addr base; struct e1000_tx_desc desc; uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE; @@ -613,7 +613,7 @@ e1000_receive(VLANClientState *vc, const uint8_t *buf, size_t size) { E1000State *s = vc->opaque; struct e1000_rx_desc desc; - target_phys_addr_t base; + a_target_phys_addr base; unsigned int n, rdt; uint32_t rdh_start; uint16_t vlan_special = 0; @@ -814,7 +814,7 @@ static void (*macreg_writeops[])(E1000State *, int, uint32_t) = { enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) }; static void -e1000_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) +e1000_mmio_writel(void *opaque, a_target_phys_addr addr, uint32_t val) { E1000State *s = opaque; unsigned int index = (addr & 0x1ffff) >> 2; @@ -832,7 +832,7 @@ e1000_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) } static void -e1000_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) +e1000_mmio_writew(void *opaque, a_target_phys_addr addr, uint32_t val) { // emulate hw without byte enables: no RMW e1000_mmio_writel(opaque, addr & ~3, @@ -840,7 +840,7 @@ e1000_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) } static void -e1000_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) +e1000_mmio_writeb(void *opaque, a_target_phys_addr addr, uint32_t val) { // emulate hw without byte enables: no RMW e1000_mmio_writel(opaque, addr & ~3, @@ -848,7 +848,7 @@ e1000_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) } static uint32_t -e1000_mmio_readl(void *opaque, target_phys_addr_t addr) +e1000_mmio_readl(void *opaque, a_target_phys_addr addr) { E1000State *s = opaque; unsigned int index = (addr & 0x1ffff) >> 2; @@ -866,14 +866,14 @@ e1000_mmio_readl(void *opaque, target_phys_addr_t addr) } static uint32_t -e1000_mmio_readb(void *opaque, target_phys_addr_t addr) +e1000_mmio_readb(void *opaque, a_target_phys_addr addr) { return ((e1000_mmio_readl(opaque, addr & ~3)) >> (8 * (addr & 3))) & 0xff; } static uint32_t -e1000_mmio_readw(void *opaque, target_phys_addr_t addr) +e1000_mmio_readw(void *opaque, a_target_phys_addr addr) { return ((e1000_mmio_readl(opaque, addr & ~3)) >> (8 * (addr & 3))) & 0xffff; diff --git a/hw/eccmemctl.c b/hw/eccmemctl.c index 12c386b058..7eaa1e5831 100644 --- a/hw/eccmemctl.c +++ b/hw/eccmemctl.c @@ -133,7 +133,7 @@ typedef struct ECCState { uint32_t version; } ECCState; -static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) +static void ecc_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val) { ECCState *s = opaque; @@ -175,7 +175,7 @@ static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) } } -static uint32_t ecc_mem_readl(void *opaque, target_phys_addr_t addr) +static uint32_t ecc_mem_readl(void *opaque, a_target_phys_addr addr) { ECCState *s = opaque; uint32_t ret = 0; @@ -233,7 +233,7 @@ static CPUWriteMemoryFunc * const ecc_mem_write[3] = { ecc_mem_writel, }; -static void ecc_diag_mem_writeb(void *opaque, target_phys_addr_t addr, +static void ecc_diag_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val) { ECCState *s = opaque; @@ -242,7 +242,7 @@ static void ecc_diag_mem_writeb(void *opaque, target_phys_addr_t addr, s->diag[addr & ECC_DIAG_MASK] = val; } -static uint32_t ecc_diag_mem_readb(void *opaque, target_phys_addr_t addr) +static uint32_t ecc_diag_mem_readb(void *opaque, a_target_phys_addr addr) { ECCState *s = opaque; uint32_t ret = s->diag[(int)addr]; diff --git a/hw/eepro100.c b/hw/eepro100.c index 3f84e26f5d..aac7bdc221 100644 --- a/hw/eepro100.c +++ b/hw/eepro100.c @@ -144,7 +144,7 @@ typedef struct { //~ int32_t tx_buf_size0; /* Length of Tx hdr. */ //~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */ //~ int32_t tx_buf_size1; /* Length of Tx data. */ -} eepro100_tx_t; +} a_eepro100_tx; /* Receive frame descriptor. */ typedef struct { @@ -155,7 +155,7 @@ typedef struct { uint16_t count; uint16_t size; char packet[MAX_ETH_FRAME_SIZE + 4]; -} eepro100_rx_t; +} a_eepro100_rx; typedef struct { uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions, @@ -167,7 +167,7 @@ typedef struct { uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported; uint16_t xmt_tco_frames, rcv_tco_frames; uint32_t complete; -} eepro100_stats_t; +} a_eepro100_stats; typedef enum { cu_idle = 0, @@ -175,14 +175,14 @@ typedef enum { cu_active = 2, cu_lpq_active = 2, cu_hqp_active = 3 -} cu_state_t; +} a_cu_state; typedef enum { ru_idle = 0, ru_suspended = 1, ru_no_resources = 2, ru_ready = 4 -} ru_state_t; +} a_ru_state; typedef struct { PCIDevice dev; @@ -213,7 +213,7 @@ typedef struct { uint8_t macaddr[6]; uint32_t statcounter[19]; uint16_t mdimem[32]; - eeprom_t *eeprom; + a_eeprom *eeprom; uint32_t device; /* device variant */ uint32_t pointer; /* (cu_base + cu_offset) address the next command block in the command block list. */ @@ -222,8 +222,8 @@ typedef struct { /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */ uint32_t ru_base; /* RU base address */ uint32_t ru_offset; /* RU address offset */ - uint32_t statsaddr; /* pointer to eepro100_stats_t */ - eepro100_stats_t statistics; /* statistical counters */ + uint32_t statsaddr; /* pointer to a_eepro100_stats */ + a_eepro100_stats statistics; /* statistical counters */ #if 0 uint16_t status; #endif @@ -600,22 +600,22 @@ enum commands { CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */ }; -static cu_state_t get_cu_state(EEPRO100State * s) +static a_cu_state get_cu_state(EEPRO100State * s) { return ((s->mem[SCBStatus] >> 6) & 0x03); } -static void set_cu_state(EEPRO100State * s, cu_state_t state) +static void set_cu_state(EEPRO100State * s, a_cu_state state) { s->mem[SCBStatus] = (s->mem[SCBStatus] & 0x3f) + (state << 6); } -static ru_state_t get_ru_state(EEPRO100State * s) +static a_ru_state get_ru_state(EEPRO100State * s) { return ((s->mem[SCBStatus] >> 2) & 0x0f); } -static void set_ru_state(EEPRO100State * s, ru_state_t state) +static void set_ru_state(EEPRO100State * s, a_ru_state state) { s->mem[SCBStatus] = (s->mem[SCBStatus] & 0xc3) + (state << 2); } @@ -639,7 +639,7 @@ static void dump_statistics(EEPRO100State * s) static void eepro100_cu_command(EEPRO100State * s, uint8_t val) { - eepro100_tx_t tx; + a_eepro100_tx tx; uint32_t cb_address; switch (val) { case CU_NOP: @@ -915,7 +915,7 @@ static uint16_t eepro100_read_eeprom(EEPRO100State * s) return val; } -static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val) +static void eepro100_write_eeprom(a_eeprom * eeprom, uint8_t val) { TRACE(EEPROM, logout("val=0x%02x\n", val)); @@ -1099,7 +1099,7 @@ static void eepro100_write_mdi(EEPRO100State * s, uint32_t val) typedef struct { uint32_t st_sign; /* Self Test Signature */ uint32_t st_result; /* Self Test Results */ -} eepro100_selftest_t; +} a_eepro100_selftest; static uint32_t eepro100_read_port(EEPRO100State * s) { @@ -1117,7 +1117,7 @@ static void eepro100_write_port(EEPRO100State * s, uint32_t val) break; case PORT_SELFTEST: TRACE(OTHER, logout("selftest address=0x%08x\n", address)); - eepro100_selftest_t data; + a_eepro100_selftest data; cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data)); data.st_sign = 0xffffffff; data.st_result = 0; @@ -1398,42 +1398,42 @@ static void pci_map(PCIDevice * pci_dev, int region_num, * ****************************************************************************/ -static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) +static void pci_mmio_writeb(void *opaque, a_target_phys_addr addr, uint32_t val) { EEPRO100State *s = opaque; //~ logout("addr=%s val=0x%02x\n", regname(addr), val); eepro100_write1(s, addr, val); } -static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) +static void pci_mmio_writew(void *opaque, a_target_phys_addr addr, uint32_t val) { EEPRO100State *s = opaque; //~ logout("addr=%s val=0x%02x\n", regname(addr), val); eepro100_write2(s, addr, val); } -static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) +static void pci_mmio_writel(void *opaque, a_target_phys_addr addr, uint32_t val) { EEPRO100State *s = opaque; //~ logout("addr=%s val=0x%02x\n", regname(addr), val); eepro100_write4(s, addr, val); } -static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr) +static uint32_t pci_mmio_readb(void *opaque, a_target_phys_addr addr) { EEPRO100State *s = opaque; //~ logout("addr=%s\n", regname(addr)); return eepro100_read1(s, addr); } -static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr) +static uint32_t pci_mmio_readw(void *opaque, a_target_phys_addr addr) { EEPRO100State *s = opaque; //~ logout("addr=%s\n", regname(addr)); return eepro100_read2(s, addr); } -static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr) +static uint32_t pci_mmio_readl(void *opaque, a_target_phys_addr addr) { EEPRO100State *s = opaque; //~ logout("addr=%s\n", regname(addr)); @@ -1541,9 +1541,9 @@ static ssize_t nic_receive(VLANClientState *vc, const uint8_t * buf, size_t size } //~ !!! //~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}} - eepro100_rx_t rx; + a_eepro100_rx rx; cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx, - offsetof(eepro100_rx_t, packet)); + offsetof(a_eepro100_rx, packet)); uint16_t rfd_command = le16_to_cpu(rx.command); uint16_t rfd_size = le16_to_cpu(rx.size); assert(size <= rfd_size); @@ -1552,9 +1552,9 @@ static ssize_t nic_receive(VLANClientState *vc, const uint8_t * buf, size_t size } TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n", rfd_command, rx.link, rx.rx_buf_addr, rfd_size)); - stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status), + stw_phys(s->ru_base + s->ru_offset + offsetof(a_eepro100_rx, status), rfd_status); - stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size); + stw_phys(s->ru_base + s->ru_offset + offsetof(a_eepro100_rx, count), size); /* Early receive interrupt not supported. */ //~ eepro100_er_interrupt(s); /* Receive CRC Transfer not supported. */ @@ -1562,7 +1562,7 @@ static ssize_t nic_receive(VLANClientState *vc, const uint8_t * buf, size_t size /* TODO: check stripping enable bit. */ //~ assert(!(s->configuration[17] & 1)); cpu_physical_memory_write(s->ru_base + s->ru_offset + - offsetof(eepro100_rx_t, packet), buf, size); + offsetof(a_eepro100_rx, packet), buf, size); s->statistics.rx_good_frames++; eepro100_fr_interrupt(s); s->ru_offset = le32_to_cpu(rx.link); diff --git a/hw/eeprom93xx.c b/hw/eeprom93xx.c index 66dfc43d50..f3ac81611f 100644 --- a/hw/eeprom93xx.c +++ b/hw/eeprom93xx.c @@ -71,7 +71,7 @@ static const char *opstring[] = { }; #endif -struct _eeprom_t { +struct eeprom { uint8_t tick; uint8_t address; uint8_t command; @@ -93,7 +93,7 @@ static void eeprom_save(QEMUFile *f, void *opaque) { /* Save EEPROM data. */ unsigned address; - eeprom_t *eeprom = (eeprom_t *)opaque; + a_eeprom *eeprom = (a_eeprom *)opaque; qemu_put_byte(f, eeprom->tick); qemu_put_byte(f, eeprom->address); @@ -116,7 +116,7 @@ static int eeprom_load(QEMUFile *f, void *opaque, int version_id) { /* Load EEPROM data from saved data if version and EEPROM size of data and current EEPROM are identical. */ - eeprom_t *eeprom = (eeprom_t *)opaque; + a_eeprom *eeprom = (a_eeprom *)opaque; int result = -EINVAL; if (version_id >= OLD_EEPROM_VERSION) { unsigned address; @@ -150,7 +150,7 @@ static int eeprom_load(QEMUFile *f, void *opaque, int version_id) return result; } -void eeprom93xx_write(eeprom_t *eeprom, int eecs, int eesk, int eedi) +void eeprom93xx_write(a_eeprom *eeprom, int eecs, int eesk, int eedi) { uint8_t tick = eeprom->tick; uint8_t eedo = eeprom->eedo; @@ -275,7 +275,7 @@ void eeprom93xx_write(eeprom_t *eeprom, int eecs, int eesk, int eedi) eeprom->command = command; } -uint16_t eeprom93xx_read(eeprom_t *eeprom) +uint16_t eeprom93xx_read(a_eeprom *eeprom) { /* Return status of pin DO (0 or 1). */ logout("CS=%u DO=%u\n", eeprom->eecs, eeprom->eedo); @@ -292,10 +292,10 @@ void eeprom93xx_reset(eeprom_t *eeprom) } #endif -eeprom_t *eeprom93xx_new(uint16_t nwords) +a_eeprom *eeprom93xx_new(uint16_t nwords) { /* Add a new EEPROM (with 16, 64 or 256 words). */ - eeprom_t *eeprom; + a_eeprom *eeprom; uint8_t addrbits; switch (nwords) { @@ -313,7 +313,7 @@ eeprom_t *eeprom93xx_new(uint16_t nwords) addrbits = 6; } - eeprom = (eeprom_t *)qemu_mallocz(sizeof(*eeprom) + nwords * 2); + eeprom = (a_eeprom *)qemu_mallocz(sizeof(*eeprom) + nwords * 2); eeprom->size = nwords; eeprom->addrbits = addrbits; /* Output DO is tristate, read results in 1. */ @@ -324,7 +324,7 @@ eeprom_t *eeprom93xx_new(uint16_t nwords) return eeprom; } -void eeprom93xx_free(eeprom_t *eeprom) +void eeprom93xx_free(a_eeprom *eeprom) { /* Destroy EEPROM. */ logout("eeprom = 0x%p\n", eeprom); @@ -332,7 +332,7 @@ void eeprom93xx_free(eeprom_t *eeprom) qemu_free(eeprom); } -uint16_t *eeprom93xx_data(eeprom_t *eeprom) +uint16_t *eeprom93xx_data(a_eeprom *eeprom) { /* Get EEPROM data array. */ return &eeprom->contents[0]; diff --git a/hw/eeprom93xx.h b/hw/eeprom93xx.h index 47282d381e..72a7c81efc 100644 --- a/hw/eeprom93xx.h +++ b/hw/eeprom93xx.h @@ -20,21 +20,21 @@ #ifndef EEPROM93XX_H #define EEPROM93XX_H -typedef struct _eeprom_t eeprom_t; +typedef struct eeprom a_eeprom; /* Create a new EEPROM with (nwords * 2) bytes. */ -eeprom_t *eeprom93xx_new(uint16_t nwords); +a_eeprom *eeprom93xx_new(uint16_t nwords); /* Destroy an existing EEPROM. */ -void eeprom93xx_free(eeprom_t *eeprom); +void eeprom93xx_free(a_eeprom *eeprom); /* Read from the EEPROM. */ -uint16_t eeprom93xx_read(eeprom_t *eeprom); +uint16_t eeprom93xx_read(a_eeprom *eeprom); /* Write to the EEPROM. */ -void eeprom93xx_write(eeprom_t *eeprom, int eecs, int eesk, int eedi); +void eeprom93xx_write(a_eeprom *eeprom, int eecs, int eesk, int eedi); /* Get EEPROM data array. */ -uint16_t *eeprom93xx_data(eeprom_t *eeprom); +uint16_t *eeprom93xx_data(a_eeprom *eeprom); #endif /* EEPROM93XX_H */ diff --git a/hw/elf_ops.h b/hw/elf_ops.h index 8376465a10..7eac22552b 100644 --- a/hw/elf_ops.h +++ b/hw/elf_ops.h @@ -74,7 +74,7 @@ static int glue(symfind, SZ)(const void *s0, const void *s1) } static const char *glue(lookup_symbol, SZ)(struct syminfo *s, - target_phys_addr_t orig_addr) + a_target_phys_addr orig_addr) { struct elf_sym *syms = glue(s->disas_symtab.elf, SZ); struct elf_sym key; @@ -84,13 +84,13 @@ typedef enum { chn_a, chn_b, -} chn_id_t; +} e_chn_id; #define CHN_C(s) ((s)->chn == chn_b? 'b' : 'a') typedef enum { ser, kbd, mouse, -} chn_type_t; +} e_chn_type; #define SERIO_QUEUE_SIZE 256 @@ -104,8 +104,8 @@ typedef struct ChannelState { qemu_irq irq; uint32_t reg; uint32_t rxint, txint, rxint_under_svc, txint_under_svc; - chn_id_t chn; // this channel, A (base+4) or B (base+0) - chn_type_t type; + e_chn_id chn; // this channel, A (base+4) or B (base+0) + e_chn_type type; struct ChannelState *otherchn; uint8_t rx, tx, wregs[SERIAL_REGS], rregs[SERIAL_REGS]; SERIOQueue queue; @@ -481,7 +481,7 @@ static void escc_update_parameters(ChannelState *s) qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); } -static void escc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) +static void escc_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val) { SerialState *serial = opaque; ChannelState *s; @@ -578,7 +578,7 @@ static void escc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) } } -static uint32_t escc_mem_readb(void *opaque, target_phys_addr_t addr) +static uint32_t escc_mem_readb(void *opaque, a_target_phys_addr addr) { SerialState *serial = opaque; ChannelState *s; @@ -725,7 +725,7 @@ static int escc_load(QEMUFile *f, void *opaque, int version_id) } -int escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB, +int escc_init(a_target_phys_addr base, qemu_irq irqA, qemu_irq irqB, CharDriverState *chrA, CharDriverState *chrB, int clock, int it_shift) { @@ -890,7 +890,7 @@ static void sunmouse_event(void *opaque, put_queue(s, 0); } -void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq, +void slavio_serial_ms_kbd_init(a_target_phys_addr base, qemu_irq irq, int disabled, int clock, int it_shift) { DeviceState *dev; @@ -1,8 +1,8 @@ /* escc.c */ #define ESCC_SIZE 4 -int escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB, +int escc_init(a_target_phys_addr base, qemu_irq irqA, qemu_irq irqB, CharDriverState *chrA, CharDriverState *chrB, int clock, int it_shift); -void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq, +void slavio_serial_ms_kbd_init(a_target_phys_addr base, qemu_irq irq, int disabled, int clock, int it_shift); @@ -439,7 +439,7 @@ static void parent_esp_reset(void *opaque, int irq, int level) esp_reset(opaque); } -static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) +static uint32_t esp_mem_readb(void *opaque, a_target_phys_addr addr) { ESPState *s = opaque; uint32_t saddr, old_val; @@ -480,7 +480,7 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) return s->rregs[saddr]; } -static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) +static void esp_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val) { ESPState *s = opaque; uint32_t saddr; @@ -632,7 +632,7 @@ static const VMStateDescription vmstate_esp = { } }; -void esp_init(target_phys_addr_t espaddr, int it_shift, +void esp_init(a_target_phys_addr espaddr, int it_shift, espdma_memory_read_write dma_memory_read, espdma_memory_read_write dma_memory_write, void *dma_opaque, qemu_irq irq, qemu_irq *reset) diff --git a/hw/etraxfs.c b/hw/etraxfs.c index 4f451c54c9..50d9eb3e33 100644 --- a/hw/etraxfs.c +++ b/hw/etraxfs.c @@ -45,7 +45,7 @@ static void main_cpu_reset(void *opaque) } static -void bareetraxfs_init (ram_addr_t ram_size, +void bareetraxfs_init (a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -59,9 +59,9 @@ void bareetraxfs_init (ram_addr_t ram_size, int kernel_size; DriveInfo *dinfo; int i; - ram_addr_t phys_ram; - ram_addr_t phys_flash; - ram_addr_t phys_intmem; + a_ram_addr phys_ram; + a_ram_addr phys_flash; + a_ram_addr phys_intmem; /* init CPUs */ if (cpu_model == NULL) { diff --git a/hw/etraxfs.h b/hw/etraxfs.h index 01fb9d3e82..b3b1222222 100644 --- a/hw/etraxfs.h +++ b/hw/etraxfs.h @@ -25,4 +25,4 @@ #include "etraxfs_dma.h" qemu_irq *cris_pic_init_cpu(CPUState *env); -void *etraxfs_eth_init(NICInfo *nd, target_phys_addr_t base, int phyaddr); +void *etraxfs_eth_init(NICInfo *nd, a_target_phys_addr base, int phyaddr); diff --git a/hw/etraxfs_dma.c b/hw/etraxfs_dma.c index 15c8ad3dc5..4b96cf815c 100644 --- a/hw/etraxfs_dma.c +++ b/hw/etraxfs_dma.c @@ -211,7 +211,7 @@ static inline int channel_en(struct fs_dma_ctrl *ctrl, int c) && ctrl->channels[c].client; } -static inline int fs_channel(target_phys_addr_t addr) +static inline int fs_channel(a_target_phys_addr addr) { /* Every channel has a 0x2000 ctrl register map. */ return addr >> 13; @@ -220,7 +220,7 @@ static inline int fs_channel(target_phys_addr_t addr) #ifdef USE_THIS_DEAD_CODE static void channel_load_g(struct fs_dma_ctrl *ctrl, int c) { - target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP); + a_target_phys_addr addr = channel_reg(ctrl, c, RW_GROUP); /* Load and decode. FIXME: handle endianness. */ cpu_physical_memory_read (addr, @@ -252,7 +252,7 @@ static void dump_d(int ch, struct dma_descr_data *d) static void channel_load_c(struct fs_dma_ctrl *ctrl, int c) { - target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN); + a_target_phys_addr addr = channel_reg(ctrl, c, RW_GROUP_DOWN); /* Load and decode. FIXME: handle endianness. */ cpu_physical_memory_read (addr, @@ -269,7 +269,7 @@ static void channel_load_c(struct fs_dma_ctrl *ctrl, int c) static void channel_load_d(struct fs_dma_ctrl *ctrl, int c) { - target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA); + a_target_phys_addr addr = channel_reg(ctrl, c, RW_SAVED_DATA); /* Load and decode. FIXME: handle endianness. */ D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); @@ -283,7 +283,7 @@ static void channel_load_d(struct fs_dma_ctrl *ctrl, int c) static void channel_store_c(struct fs_dma_ctrl *ctrl, int c) { - target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN); + a_target_phys_addr addr = channel_reg(ctrl, c, RW_GROUP_DOWN); /* Encode and store. FIXME: handle endianness. */ D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); @@ -295,7 +295,7 @@ static void channel_store_c(struct fs_dma_ctrl *ctrl, int c) static void channel_store_d(struct fs_dma_ctrl *ctrl, int c) { - target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA); + a_target_phys_addr addr = channel_reg(ctrl, c, RW_SAVED_DATA); /* Encode and store. FIXME: handle endianness. */ D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); @@ -556,14 +556,14 @@ static inline int channel_in_run(struct fs_dma_ctrl *ctrl, int c) return 0; } -static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr) +static uint32_t dma_rinvalid (void *opaque, a_target_phys_addr addr) { hw_error("Unsupported short raccess. reg=" TARGET_FMT_plx "\n", addr); return 0; } static uint32_t -dma_readl (void *opaque, target_phys_addr_t addr) +dma_readl (void *opaque, a_target_phys_addr addr) { struct fs_dma_ctrl *ctrl = opaque; int c; @@ -591,7 +591,7 @@ dma_readl (void *opaque, target_phys_addr_t addr) } static void -dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value) +dma_winvalid (void *opaque, a_target_phys_addr addr, uint32_t value) { hw_error("Unsupported short waccess. reg=" TARGET_FMT_plx "\n", addr); } @@ -608,7 +608,7 @@ dma_update_state(struct fs_dma_ctrl *ctrl, int c) } static void -dma_writel (void *opaque, target_phys_addr_t addr, uint32_t value) +dma_writel (void *opaque, a_target_phys_addr addr, uint32_t value) { struct fs_dma_ctrl *ctrl = opaque; int c; @@ -739,7 +739,7 @@ static void DMA_run(void *opaque) qemu_bh_schedule_idle(etraxfs_dmac->bh); } -void *etraxfs_dmac_init(target_phys_addr_t base, int nr_channels) +void *etraxfs_dmac_init(a_target_phys_addr base, int nr_channels) { struct fs_dma_ctrl *ctrl = NULL; diff --git a/hw/etraxfs_dma.h b/hw/etraxfs_dma.h index 96408abab3..4bca2d2d6f 100644 --- a/hw/etraxfs_dma.h +++ b/hw/etraxfs_dma.h @@ -13,7 +13,7 @@ struct etraxfs_dma_client } client; }; -void *etraxfs_dmac_init(target_phys_addr_t base, int nr_channels); +void *etraxfs_dmac_init(a_target_phys_addr base, int nr_channels); void etraxfs_dmac_connect(void *opaque, int channel, qemu_irq *line, int input); void etraxfs_dmac_connect_client(void *opaque, int c, diff --git a/hw/etraxfs_eth.c b/hw/etraxfs_eth.c index 54786c5e97..8537528750 100644 --- a/hw/etraxfs_eth.c +++ b/hw/etraxfs_eth.c @@ -365,7 +365,7 @@ static void eth_validate_duplex(struct fs_eth *eth) } } -static uint32_t eth_readl (void *opaque, target_phys_addr_t addr) +static uint32_t eth_readl (void *opaque, a_target_phys_addr addr) { struct fs_eth *eth = opaque; uint32_t r = 0; @@ -409,7 +409,7 @@ static void eth_update_ma(struct fs_eth *eth, int ma) } static void -eth_writel (void *opaque, target_phys_addr_t addr, uint32_t value) +eth_writel (void *opaque, a_target_phys_addr addr, uint32_t value) { struct fs_eth *eth = opaque; @@ -564,7 +564,7 @@ static void eth_cleanup(VLANClientState *vc) qemu_free(eth); } -void *etraxfs_eth_init(NICInfo *nd, target_phys_addr_t base, int phyaddr) +void *etraxfs_eth_init(NICInfo *nd, a_target_phys_addr base, int phyaddr) { struct etraxfs_dma_client *dma = NULL; struct fs_eth *eth = NULL; diff --git a/hw/etraxfs_pic.c b/hw/etraxfs_pic.c index b2c4859949..9140caad83 100644 --- a/hw/etraxfs_pic.c +++ b/hw/etraxfs_pic.c @@ -77,7 +77,7 @@ static void pic_update(struct etrax_pic *fs) qemu_set_irq(fs->parent_irq, !!vector); } -static uint32_t pic_readl (void *opaque, target_phys_addr_t addr) +static uint32_t pic_readl (void *opaque, a_target_phys_addr addr) { struct etrax_pic *fs = opaque; uint32_t rval; @@ -88,7 +88,7 @@ static uint32_t pic_readl (void *opaque, target_phys_addr_t addr) } static void -pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value) +pic_writel (void *opaque, a_target_phys_addr addr, uint32_t value) { struct etrax_pic *fs = opaque; D(printf("%s addr=%x val=%x\n", __func__, addr, value)); diff --git a/hw/etraxfs_ser.c b/hw/etraxfs_ser.c index e1f96158fd..9bfbc12a9f 100644 --- a/hw/etraxfs_ser.c +++ b/hw/etraxfs_ser.c @@ -65,7 +65,7 @@ static void ser_update_irq(struct etrax_serial *s) s->regs[RW_ACK_INTR] = 0; } -static uint32_t ser_readl (void *opaque, target_phys_addr_t addr) +static uint32_t ser_readl (void *opaque, a_target_phys_addr addr) { struct etrax_serial *s = opaque; D(CPUState *env = s->env); @@ -91,7 +91,7 @@ static uint32_t ser_readl (void *opaque, target_phys_addr_t addr) } static void -ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value) +ser_writel (void *opaque, a_target_phys_addr addr, uint32_t value) { struct etrax_serial *s = opaque; unsigned char ch = value; diff --git a/hw/etraxfs_timer.c b/hw/etraxfs_timer.c index 87700d4cdf..272b3e675e 100644 --- a/hw/etraxfs_timer.c +++ b/hw/etraxfs_timer.c @@ -72,7 +72,7 @@ struct etrax_timer { uint32_t r_masked_intr; }; -static uint32_t timer_readl (void *opaque, target_phys_addr_t addr) +static uint32_t timer_readl (void *opaque, a_target_phys_addr addr) { struct etrax_timer *t = opaque; uint32_t r = 0; @@ -243,7 +243,7 @@ static inline void timer_watchdog_update(struct etrax_timer *t, uint32_t value) } static void -timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value) +timer_writel (void *opaque, a_target_phys_addr addr, uint32_t value) { struct etrax_timer *t = opaque; @@ -61,43 +61,43 @@ #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */ /* Floppy disk drive emulation */ -typedef enum fdisk_type_t { +typedef enum fdisk_type { FDRIVE_DISK_288 = 0x01, /* 2.88 MB disk */ FDRIVE_DISK_144 = 0x02, /* 1.44 MB disk */ FDRIVE_DISK_720 = 0x03, /* 720 kB disk */ FDRIVE_DISK_USER = 0x04, /* User defined geometry */ FDRIVE_DISK_NONE = 0x05, /* No disk */ -} fdisk_type_t; +} e_fdisk_type; -typedef enum fdrive_type_t { +typedef enum fdrive_type { FDRIVE_DRV_144 = 0x00, /* 1.44 MB 3"5 drive */ FDRIVE_DRV_288 = 0x01, /* 2.88 MB 3"5 drive */ FDRIVE_DRV_120 = 0x02, /* 1.2 MB 5"25 drive */ FDRIVE_DRV_NONE = 0x03, /* No drive connected */ -} fdrive_type_t; +} e_fdrive_type; -typedef enum fdisk_flags_t { +typedef enum fdisk_flags { FDISK_DBL_SIDES = 0x01, -} fdisk_flags_t; +} e_fdisk_flags; -typedef struct fdrive_t { +typedef struct fdrive { BlockDriverState *bs; /* Drive status */ - fdrive_type_t drive; + e_fdrive_type drive; uint8_t perpendicular; /* 2.88 MB access mode */ /* Position */ uint8_t head; uint8_t track; uint8_t sect; /* Media */ - fdisk_flags_t flags; + e_fdisk_flags flags; uint8_t last_sect; /* Nb sector per track */ uint8_t max_track; /* Nb of tracks */ uint16_t bps; /* Bytes per sector */ uint8_t ro; /* Is read-only */ -} fdrive_t; +} a_fdrive; -static void fd_init (fdrive_t *drv, BlockDriverState *bs) +static void fd_init (a_fdrive *drv, BlockDriverState *bs) { /* Drive */ drv->bs = bs; @@ -115,7 +115,7 @@ static int _fd_sector (uint8_t head, uint8_t track, } /* Returns current position, in sectors, for given drive */ -static int fd_sector (fdrive_t *drv) +static int fd_sector (a_fdrive *drv) { return _fd_sector(drv->head, drv->track, drv->sect, drv->last_sect); } @@ -127,7 +127,7 @@ static int fd_sector (fdrive_t *drv) * returns 3 if sector is invalid * returns 4 if seek is disabled */ -static int fd_seek (fdrive_t *drv, uint8_t head, uint8_t track, uint8_t sect, +static int fd_seek (a_fdrive *drv, uint8_t head, uint8_t track, uint8_t sect, int enable_seek) { uint32_t sector; @@ -169,7 +169,7 @@ static int fd_seek (fdrive_t *drv, uint8_t head, uint8_t track, uint8_t sect, } /* Set drive back to track 0 */ -static void fd_recalibrate (fdrive_t *drv) +static void fd_recalibrate (a_fdrive *drv) { FLOPPY_DPRINTF("recalibrate\n"); drv->head = 0; @@ -178,16 +178,16 @@ static void fd_recalibrate (fdrive_t *drv) } /* Recognize floppy formats */ -typedef struct fd_format_t { - fdrive_type_t drive; - fdisk_type_t disk; +typedef struct fd_format { + e_fdrive_type drive; + e_fdisk_type disk; uint8_t last_sect; uint8_t max_track; uint8_t max_head; const char *str; -} fd_format_t; +} a_fd_format; -static const fd_format_t fd_formats[] = { +static const a_fd_format fd_formats[] = { /* First entry is default format */ /* 1.44 MB 3"1/2 floppy disks */ { FDRIVE_DRV_144, FDRIVE_DISK_144, 18, 80, 1, "1.44 MB 3\"1/2", }, @@ -235,9 +235,9 @@ static const fd_format_t fd_formats[] = { }; /* Revalidate a disk drive after a disk change */ -static void fd_revalidate (fdrive_t *drv) +static void fd_revalidate (a_fdrive *drv) { - const fd_format_t *parse; + const a_fd_format *parse; uint64_t nb_sectors, size; int i, first_match, match; int nb_heads, max_track, last_sect, ro; @@ -302,23 +302,23 @@ static void fd_revalidate (fdrive_t *drv) /********************************************************/ /* Intel 82078 floppy disk controller emulation */ -static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq); -static void fdctrl_reset_fifo (fdctrl_t *fdctrl); +static void fdctrl_reset (a_fdctrl *fdctrl, int do_irq); +static void fdctrl_reset_fifo (a_fdctrl *fdctrl); static int fdctrl_transfer_handler (void *opaque, int nchan, - int dma_pos, int dma_len); -static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0); - -static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl); -static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl); -static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl); -static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value); -static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl); -static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value); -static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl); -static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value); -static uint32_t fdctrl_read_data (fdctrl_t *fdctrl); -static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value); -static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl); + int dma_pos, int dma_len); +static void fdctrl_raise_irq (a_fdctrl *fdctrl, uint8_t status0); + +static uint32_t fdctrl_read_statusA (a_fdctrl *fdctrl); +static uint32_t fdctrl_read_statusB (a_fdctrl *fdctrl); +static uint32_t fdctrl_read_dor (a_fdctrl *fdctrl); +static void fdctrl_write_dor (a_fdctrl *fdctrl, uint32_t value); +static uint32_t fdctrl_read_tape (a_fdctrl *fdctrl); +static void fdctrl_write_tape (a_fdctrl *fdctrl, uint32_t value); +static uint32_t fdctrl_read_main_status (a_fdctrl *fdctrl); +static void fdctrl_write_rate (a_fdctrl *fdctrl, uint32_t value); +static uint32_t fdctrl_read_data (a_fdctrl *fdctrl); +static void fdctrl_write_data (a_fdctrl *fdctrl, uint32_t value); +static uint32_t fdctrl_read_dir (a_fdctrl *fdctrl); enum { FD_DIR_WRITE = 0, @@ -470,7 +470,7 @@ enum { #define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK) #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT) -struct fdctrl_t { +struct fdctrl { /* Controller's identification */ uint8_t version; /* HW */ @@ -511,23 +511,23 @@ struct fdctrl_t { int sun4m; /* Floppy drives */ uint8_t num_floppies; - fdrive_t drives[MAX_FD]; + a_fdrive drives[MAX_FD]; int reset_sensei; }; -typedef struct fdctrl_sysbus_t { +typedef struct fdctrl_sysbus { SysBusDevice busdev; - struct fdctrl_t state; -} fdctrl_sysbus_t; + struct fdctrl state; +} a_fdctrl_sysbus; -typedef struct fdctrl_isabus_t { +typedef struct fdctrl_isabus { ISADevice busdev; - struct fdctrl_t state; -} fdctrl_isabus_t; + struct fdctrl state; +} a_fdctrl_isabus; static uint32_t fdctrl_read (void *opaque, uint32_t reg) { - fdctrl_t *fdctrl = opaque; + a_fdctrl *fdctrl = opaque; uint32_t retval; switch (reg) { @@ -563,7 +563,7 @@ static uint32_t fdctrl_read (void *opaque, uint32_t reg) static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value) { - fdctrl_t *fdctrl = opaque; + a_fdctrl *fdctrl = opaque; FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value); @@ -595,13 +595,13 @@ static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value) fdctrl_write(opaque, reg & 7, value); } -static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg) +static uint32_t fdctrl_read_mem (void *opaque, a_target_phys_addr reg) { return fdctrl_read(opaque, (uint32_t)reg); } static void fdctrl_write_mem (void *opaque, - target_phys_addr_t reg, uint32_t value) + a_target_phys_addr reg, uint32_t value) { fdctrl_write(opaque, (uint32_t)reg, value); } @@ -636,23 +636,23 @@ static const VMStateDescription vmstate_fdrive = { .minimum_version_id = 1, .minimum_version_id_old = 1, .fields = (VMStateField []) { - VMSTATE_UINT8(head, fdrive_t), - VMSTATE_UINT8(track, fdrive_t), - VMSTATE_UINT8(sect, fdrive_t), + VMSTATE_UINT8(head, a_fdrive), + VMSTATE_UINT8(track, a_fdrive), + VMSTATE_UINT8(sect, a_fdrive), VMSTATE_END_OF_LIST() } }; static void fdc_pre_save(const void *opaque) { - fdctrl_t *s = (void *)opaque; + a_fdctrl *s = (void *)opaque; s->dor_vmstate = s->dor | GET_CUR_DRV(s); } static int fdc_post_load(void *opaque) { - fdctrl_t *s = opaque; + a_fdctrl *s = opaque; SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK); s->dor = s->dor_vmstate & ~FD_DOR_SELMASK; @@ -668,46 +668,46 @@ static const VMStateDescription vmstate_fdc = { .post_load = fdc_post_load, .fields = (VMStateField []) { /* Controller State */ - VMSTATE_UINT8(sra, fdctrl_t), - VMSTATE_UINT8(srb, fdctrl_t), - VMSTATE_UINT8(dor_vmstate, fdctrl_t), - VMSTATE_UINT8(tdr, fdctrl_t), - VMSTATE_UINT8(dsr, fdctrl_t), - VMSTATE_UINT8(msr, fdctrl_t), - VMSTATE_UINT8(status0, fdctrl_t), - VMSTATE_UINT8(status1, fdctrl_t), - VMSTATE_UINT8(status2, fdctrl_t), + VMSTATE_UINT8(sra, a_fdctrl), + VMSTATE_UINT8(srb, a_fdctrl), + VMSTATE_UINT8(dor_vmstate, a_fdctrl), + VMSTATE_UINT8(tdr, a_fdctrl), + VMSTATE_UINT8(dsr, a_fdctrl), + VMSTATE_UINT8(msr, a_fdctrl), + VMSTATE_UINT8(status0, a_fdctrl), + VMSTATE_UINT8(status1, a_fdctrl), + VMSTATE_UINT8(status2, a_fdctrl), /* Command FIFO */ - VMSTATE_VARRAY(fifo, fdctrl_t, fifo_size, 0, vmstate_info_uint8, uint8), - VMSTATE_UINT32(data_pos, fdctrl_t), - VMSTATE_UINT32(data_len, fdctrl_t), - VMSTATE_UINT8(data_state, fdctrl_t), - VMSTATE_UINT8(data_dir, fdctrl_t), - VMSTATE_UINT8(eot, fdctrl_t), + VMSTATE_VARRAY(fifo, a_fdctrl, fifo_size, 0, vmstate_info_uint8, uint8), + VMSTATE_UINT32(data_pos, a_fdctrl), + VMSTATE_UINT32(data_len, a_fdctrl), + VMSTATE_UINT8(data_state, a_fdctrl), + VMSTATE_UINT8(data_dir, a_fdctrl), + VMSTATE_UINT8(eot, a_fdctrl), /* States kept only to be returned back */ - VMSTATE_UINT8(timer0, fdctrl_t), - VMSTATE_UINT8(timer1, fdctrl_t), - VMSTATE_UINT8(precomp_trk, fdctrl_t), - VMSTATE_UINT8(config, fdctrl_t), - VMSTATE_UINT8(lock, fdctrl_t), - VMSTATE_UINT8(pwrd, fdctrl_t), - VMSTATE_UINT8_EQUAL(num_floppies, fdctrl_t), - VMSTATE_STRUCT_ARRAY(drives, fdctrl_t, MAX_FD, 1, - vmstate_fdrive, fdrive_t), + VMSTATE_UINT8(timer0, a_fdctrl), + VMSTATE_UINT8(timer1, a_fdctrl), + VMSTATE_UINT8(precomp_trk, a_fdctrl), + VMSTATE_UINT8(config, a_fdctrl), + VMSTATE_UINT8(lock, a_fdctrl), + VMSTATE_UINT8(pwrd, a_fdctrl), + VMSTATE_UINT8_EQUAL(num_floppies, a_fdctrl), + VMSTATE_STRUCT_ARRAY(drives, a_fdctrl, MAX_FD, 1, + vmstate_fdrive, a_fdrive), VMSTATE_END_OF_LIST() } }; static void fdctrl_external_reset(void *opaque) { - fdctrl_t *s = opaque; + a_fdctrl *s = opaque; fdctrl_reset(s, 0); } static void fdctrl_handle_tc(void *opaque, int irq, int level) { - //fdctrl_t *s = opaque; + //a_fdctrl *s = opaque; if (level) { // XXX @@ -716,13 +716,13 @@ static void fdctrl_handle_tc(void *opaque, int irq, int level) } /* XXX: may change if moved to bdrv */ -int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num) +int fdctrl_get_drive_type(a_fdctrl *fdctrl, int drive_num) { return fdctrl->drives[drive_num].drive; } /* Change IRQ state */ -static void fdctrl_reset_irq (fdctrl_t *fdctrl) +static void fdctrl_reset_irq (a_fdctrl *fdctrl) { if (!(fdctrl->sra & FD_SRA_INTPEND)) return; @@ -731,7 +731,7 @@ static void fdctrl_reset_irq (fdctrl_t *fdctrl) fdctrl->sra &= ~FD_SRA_INTPEND; } -static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0) +static void fdctrl_raise_irq (a_fdctrl *fdctrl, uint8_t status0) { /* Sparc mutation */ if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) { @@ -751,7 +751,7 @@ static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0) } /* Reset controller */ -static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq) +static void fdctrl_reset (a_fdctrl *fdctrl, int do_irq) { int i; @@ -780,12 +780,12 @@ static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq) } } -static inline fdrive_t *drv0 (fdctrl_t *fdctrl) +static inline a_fdrive *drv0 (a_fdctrl *fdctrl) { return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2]; } -static inline fdrive_t *drv1 (fdctrl_t *fdctrl) +static inline a_fdrive *drv1 (a_fdctrl *fdctrl) { if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2)) return &fdctrl->drives[1]; @@ -794,7 +794,7 @@ static inline fdrive_t *drv1 (fdctrl_t *fdctrl) } #if MAX_FD == 4 -static inline fdrive_t *drv2 (fdctrl_t *fdctrl) +static inline a_fdrive *drv2 (a_fdctrl *fdctrl) { if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2)) return &fdctrl->drives[2]; @@ -802,7 +802,7 @@ static inline fdrive_t *drv2 (fdctrl_t *fdctrl) return &fdctrl->drives[1]; } -static inline fdrive_t *drv3 (fdctrl_t *fdctrl) +static inline a_fdrive *drv3 (a_fdctrl *fdctrl) { if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2)) return &fdctrl->drives[3]; @@ -811,7 +811,7 @@ static inline fdrive_t *drv3 (fdctrl_t *fdctrl) } #endif -static fdrive_t *get_cur_drv (fdctrl_t *fdctrl) +static a_fdrive *get_cur_drv (a_fdctrl *fdctrl) { switch (fdctrl->cur_drv) { case 0: return drv0(fdctrl); @@ -825,7 +825,7 @@ static fdrive_t *get_cur_drv (fdctrl_t *fdctrl) } /* Status A register : 0x00 (read-only) */ -static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl) +static uint32_t fdctrl_read_statusA (a_fdctrl *fdctrl) { uint32_t retval = fdctrl->sra; @@ -835,7 +835,7 @@ static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl) } /* Status B register : 0x01 (read-only) */ -static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl) +static uint32_t fdctrl_read_statusB (a_fdctrl *fdctrl) { uint32_t retval = fdctrl->srb; @@ -845,7 +845,7 @@ static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl) } /* Digital output register : 0x02 */ -static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl) +static uint32_t fdctrl_read_dor (a_fdctrl *fdctrl) { uint32_t retval = fdctrl->dor; @@ -856,7 +856,7 @@ static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl) return retval; } -static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value) +static void fdctrl_write_dor (a_fdctrl *fdctrl, uint32_t value) { FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value); @@ -895,7 +895,7 @@ static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value) } /* Tape drive register : 0x03 */ -static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl) +static uint32_t fdctrl_read_tape (a_fdctrl *fdctrl) { uint32_t retval = fdctrl->tdr; @@ -904,7 +904,7 @@ static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl) return retval; } -static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value) +static void fdctrl_write_tape (a_fdctrl *fdctrl, uint32_t value) { /* Reset mode */ if (!(fdctrl->dor & FD_DOR_nRESET)) { @@ -918,7 +918,7 @@ static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value) } /* Main status register : 0x04 (read) */ -static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl) +static uint32_t fdctrl_read_main_status (a_fdctrl *fdctrl) { uint32_t retval = fdctrl->msr; @@ -931,7 +931,7 @@ static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl) } /* Data select rate register : 0x04 (write) */ -static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value) +static void fdctrl_write_rate (a_fdctrl *fdctrl, uint32_t value) { /* Reset mode */ if (!(fdctrl->dor & FD_DOR_nRESET)) { @@ -951,7 +951,7 @@ static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value) fdctrl->dsr = value; } -static int fdctrl_media_changed(fdrive_t *drv) +static int fdctrl_media_changed(a_fdrive *drv) { int ret; @@ -965,7 +965,7 @@ static int fdctrl_media_changed(fdrive_t *drv) } /* Digital input register : 0x07 (read-only) */ -static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl) +static uint32_t fdctrl_read_dir (a_fdctrl *fdctrl) { uint32_t retval = 0; @@ -984,7 +984,7 @@ static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl) } /* FIFO state control */ -static void fdctrl_reset_fifo (fdctrl_t *fdctrl) +static void fdctrl_reset_fifo (a_fdctrl *fdctrl) { fdctrl->data_dir = FD_DIR_WRITE; fdctrl->data_pos = 0; @@ -992,7 +992,7 @@ static void fdctrl_reset_fifo (fdctrl_t *fdctrl) } /* Set FIFO status for the host to read */ -static void fdctrl_set_fifo (fdctrl_t *fdctrl, int fifo_len, int do_irq) +static void fdctrl_set_fifo (a_fdctrl *fdctrl, int fifo_len, int do_irq) { fdctrl->data_dir = FD_DIR_READ; fdctrl->data_len = fifo_len; @@ -1003,7 +1003,7 @@ static void fdctrl_set_fifo (fdctrl_t *fdctrl, int fifo_len, int do_irq) } /* Set an error: unimplemented/unknown command */ -static void fdctrl_unimplemented (fdctrl_t *fdctrl, int direction) +static void fdctrl_unimplemented (a_fdctrl *fdctrl, int direction) { FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]); fdctrl->fifo[0] = FD_SR0_INVCMD; @@ -1011,7 +1011,7 @@ static void fdctrl_unimplemented (fdctrl_t *fdctrl, int direction) } /* Seek to next sector */ -static int fdctrl_seek_to_next_sect (fdctrl_t *fdctrl, fdrive_t *cur_drv) +static int fdctrl_seek_to_next_sect (a_fdctrl *fdctrl, a_fdrive *cur_drv) { FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n", cur_drv->head, cur_drv->track, cur_drv->sect, @@ -1045,10 +1045,10 @@ static int fdctrl_seek_to_next_sect (fdctrl_t *fdctrl, fdrive_t *cur_drv) } /* Callback for transfer end (stop or abort) */ -static void fdctrl_stop_transfer (fdctrl_t *fdctrl, uint8_t status0, +static void fdctrl_stop_transfer (a_fdctrl *fdctrl, uint8_t status0, uint8_t status1, uint8_t status2) { - fdrive_t *cur_drv; + a_fdrive *cur_drv; cur_drv = get_cur_drv(fdctrl); FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n", @@ -1071,9 +1071,9 @@ static void fdctrl_stop_transfer (fdctrl_t *fdctrl, uint8_t status0, } /* Prepare a data transfer (either DMA or FIFO) */ -static void fdctrl_start_transfer (fdctrl_t *fdctrl, int direction) +static void fdctrl_start_transfer (a_fdctrl *fdctrl, int direction) { - fdrive_t *cur_drv; + a_fdrive *cur_drv; uint8_t kh, kt, ks; int did_seek = 0; @@ -1173,7 +1173,7 @@ static void fdctrl_start_transfer (fdctrl_t *fdctrl, int direction) } /* Prepare a transfer of deleted data */ -static void fdctrl_start_transfer_del (fdctrl_t *fdctrl, int direction) +static void fdctrl_start_transfer_del (a_fdctrl *fdctrl, int direction) { FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n"); @@ -1187,8 +1187,8 @@ static void fdctrl_start_transfer_del (fdctrl_t *fdctrl, int direction) static int fdctrl_transfer_handler (void *opaque, int nchan, int dma_pos, int dma_len) { - fdctrl_t *fdctrl; - fdrive_t *cur_drv; + a_fdctrl *fdctrl; + a_fdrive *cur_drv; int len, start_pos, rel_pos; uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00; @@ -1294,9 +1294,9 @@ static int fdctrl_transfer_handler (void *opaque, int nchan, } /* Data register : 0x05 */ -static uint32_t fdctrl_read_data (fdctrl_t *fdctrl) +static uint32_t fdctrl_read_data (a_fdctrl *fdctrl) { - fdrive_t *cur_drv; + a_fdrive *cur_drv; uint32_t retval = 0; int pos; @@ -1342,9 +1342,9 @@ static uint32_t fdctrl_read_data (fdctrl_t *fdctrl) return retval; } -static void fdctrl_format_sector (fdctrl_t *fdctrl) +static void fdctrl_format_sector (a_fdctrl *fdctrl) { - fdrive_t *cur_drv; + a_fdrive *cur_drv; uint8_t kh, kt, ks; SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); @@ -1404,16 +1404,16 @@ static void fdctrl_format_sector (fdctrl_t *fdctrl) } } -static void fdctrl_handle_lock (fdctrl_t *fdctrl, int direction) +static void fdctrl_handle_lock (a_fdctrl *fdctrl, int direction) { fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0; fdctrl->fifo[0] = fdctrl->lock << 4; fdctrl_set_fifo(fdctrl, 1, fdctrl->lock); } -static void fdctrl_handle_dumpreg (fdctrl_t *fdctrl, int direction) +static void fdctrl_handle_dumpreg (a_fdctrl *fdctrl, int direction) { - fdrive_t *cur_drv = get_cur_drv(fdctrl); + a_fdrive *cur_drv = get_cur_drv(fdctrl); /* Drives position */ fdctrl->fifo[0] = drv0(fdctrl)->track; @@ -1436,22 +1436,22 @@ static void fdctrl_handle_dumpreg (fdctrl_t *fdctrl, int direction) fdctrl_set_fifo(fdctrl, 10, 0); } -static void fdctrl_handle_version (fdctrl_t *fdctrl, int direction) +static void fdctrl_handle_version (a_fdctrl *fdctrl, int direction) { /* Controller's version */ fdctrl->fifo[0] = fdctrl->version; fdctrl_set_fifo(fdctrl, 1, 1); } -static void fdctrl_handle_partid (fdctrl_t *fdctrl, int direction) +static void fdctrl_handle_partid (a_fdctrl *fdctrl, int direction) { fdctrl->fifo[0] = 0x41; /* Stepping 1 */ fdctrl_set_fifo(fdctrl, 1, 0); } -static void fdctrl_handle_restore (fdctrl_t *fdctrl, int direction) +static void fdctrl_handle_restore (a_fdctrl *fdctrl, int direction) { - fdrive_t *cur_drv = get_cur_drv(fdctrl); + a_fdrive *cur_drv = get_cur_drv(fdctrl); /* Drives position */ drv0(fdctrl)->track = fdctrl->fifo[3]; @@ -1472,9 +1472,9 @@ static void fdctrl_handle_restore (fdctrl_t *fdctrl, int direction) fdctrl_reset_fifo(fdctrl); } -static void fdctrl_handle_save (fdctrl_t *fdctrl, int direction) +static void fdctrl_handle_save (a_fdctrl *fdctrl, int direction) { - fdrive_t *cur_drv = get_cur_drv(fdctrl); + a_fdrive *cur_drv = get_cur_drv(fdctrl); fdctrl->fifo[0] = 0; fdctrl->fifo[1] = 0; @@ -1502,9 +1502,9 @@ static void fdctrl_handle_save (fdctrl_t *fdctrl, int direction) fdctrl_set_fifo(fdctrl, 15, 1); } -static void fdctrl_handle_readid (fdctrl_t *fdctrl, int direction) +static void fdctrl_handle_readid (a_fdctrl *fdctrl, int direction) { - fdrive_t *cur_drv = get_cur_drv(fdctrl); + a_fdrive *cur_drv = get_cur_drv(fdctrl); /* XXX: should set main status register to busy */ cur_drv->head = (fdctrl->fifo[1] >> 2) & 1; @@ -1512,9 +1512,9 @@ static void fdctrl_handle_readid (fdctrl_t *fdctrl, int direction) qemu_get_clock(vm_clock) + (get_ticks_per_sec() / 50)); } -static void fdctrl_handle_format_track (fdctrl_t *fdctrl, int direction) +static void fdctrl_handle_format_track (a_fdctrl *fdctrl, int direction) { - fdrive_t *cur_drv; + a_fdrive *cur_drv; SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); cur_drv = get_cur_drv(fdctrl); @@ -1541,7 +1541,7 @@ static void fdctrl_handle_format_track (fdctrl_t *fdctrl, int direction) fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); } -static void fdctrl_handle_specify (fdctrl_t *fdctrl, int direction) +static void fdctrl_handle_specify (a_fdctrl *fdctrl, int direction) { fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF; fdctrl->timer1 = fdctrl->fifo[2] >> 1; @@ -1553,9 +1553,9 @@ static void fdctrl_handle_specify (fdctrl_t *fdctrl, int direction) fdctrl_reset_fifo(fdctrl); } -static void fdctrl_handle_sense_drive_status (fdctrl_t *fdctrl, int direction) +static void fdctrl_handle_sense_drive_status (a_fdctrl *fdctrl, int direction) { - fdrive_t *cur_drv; + a_fdrive *cur_drv; SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); cur_drv = get_cur_drv(fdctrl); @@ -1569,9 +1569,9 @@ static void fdctrl_handle_sense_drive_status (fdctrl_t *fdctrl, int direction) fdctrl_set_fifo(fdctrl, 1, 0); } -static void fdctrl_handle_recalibrate (fdctrl_t *fdctrl, int direction) +static void fdctrl_handle_recalibrate (a_fdctrl *fdctrl, int direction) { - fdrive_t *cur_drv; + a_fdrive *cur_drv; SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); cur_drv = get_cur_drv(fdctrl); @@ -1581,9 +1581,9 @@ static void fdctrl_handle_recalibrate (fdctrl_t *fdctrl, int direction) fdctrl_raise_irq(fdctrl, FD_SR0_SEEK); } -static void fdctrl_handle_sense_interrupt_status (fdctrl_t *fdctrl, int direction) +static void fdctrl_handle_sense_interrupt_status (a_fdctrl *fdctrl, int direction) { - fdrive_t *cur_drv = get_cur_drv(fdctrl); + a_fdrive *cur_drv = get_cur_drv(fdctrl); if(fdctrl->reset_sensei > 0) { fdctrl->fifo[0] = @@ -1603,9 +1603,9 @@ static void fdctrl_handle_sense_interrupt_status (fdctrl_t *fdctrl, int directio fdctrl->status0 = FD_SR0_RDYCHG; } -static void fdctrl_handle_seek (fdctrl_t *fdctrl, int direction) +static void fdctrl_handle_seek (a_fdctrl *fdctrl, int direction) { - fdrive_t *cur_drv; + a_fdrive *cur_drv; SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); cur_drv = get_cur_drv(fdctrl); @@ -1619,9 +1619,9 @@ static void fdctrl_handle_seek (fdctrl_t *fdctrl, int direction) } } -static void fdctrl_handle_perpendicular_mode (fdctrl_t *fdctrl, int direction) +static void fdctrl_handle_perpendicular_mode (a_fdctrl *fdctrl, int direction) { - fdrive_t *cur_drv = get_cur_drv(fdctrl); + a_fdrive *cur_drv = get_cur_drv(fdctrl); if (fdctrl->fifo[1] & 0x80) cur_drv->perpendicular = fdctrl->fifo[1] & 0x7; @@ -1629,7 +1629,7 @@ static void fdctrl_handle_perpendicular_mode (fdctrl_t *fdctrl, int direction) fdctrl_reset_fifo(fdctrl); } -static void fdctrl_handle_configure (fdctrl_t *fdctrl, int direction) +static void fdctrl_handle_configure (a_fdctrl *fdctrl, int direction) { fdctrl->config = fdctrl->fifo[2]; fdctrl->precomp_trk = fdctrl->fifo[3]; @@ -1637,22 +1637,22 @@ static void fdctrl_handle_configure (fdctrl_t *fdctrl, int direction) fdctrl_reset_fifo(fdctrl); } -static void fdctrl_handle_powerdown_mode (fdctrl_t *fdctrl, int direction) +static void fdctrl_handle_powerdown_mode (a_fdctrl *fdctrl, int direction) { fdctrl->pwrd = fdctrl->fifo[1]; fdctrl->fifo[0] = fdctrl->fifo[1]; fdctrl_set_fifo(fdctrl, 1, 1); } -static void fdctrl_handle_option (fdctrl_t *fdctrl, int direction) +static void fdctrl_handle_option (a_fdctrl *fdctrl, int direction) { /* No result back */ fdctrl_reset_fifo(fdctrl); } -static void fdctrl_handle_drive_specification_command (fdctrl_t *fdctrl, int direction) +static void fdctrl_handle_drive_specification_command (a_fdctrl *fdctrl, int direction) { - fdrive_t *cur_drv = get_cur_drv(fdctrl); + a_fdrive *cur_drv = get_cur_drv(fdctrl); if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) { /* Command parameters done */ @@ -1672,9 +1672,9 @@ static void fdctrl_handle_drive_specification_command (fdctrl_t *fdctrl, int dir } } -static void fdctrl_handle_relative_seek_out (fdctrl_t *fdctrl, int direction) +static void fdctrl_handle_relative_seek_out (a_fdctrl *fdctrl, int direction) { - fdrive_t *cur_drv; + a_fdrive *cur_drv; SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); cur_drv = get_cur_drv(fdctrl); @@ -1688,9 +1688,9 @@ static void fdctrl_handle_relative_seek_out (fdctrl_t *fdctrl, int direction) fdctrl_raise_irq(fdctrl, FD_SR0_SEEK); } -static void fdctrl_handle_relative_seek_in (fdctrl_t *fdctrl, int direction) +static void fdctrl_handle_relative_seek_in (a_fdctrl *fdctrl, int direction) { - fdrive_t *cur_drv; + a_fdrive *cur_drv; SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); cur_drv = get_cur_drv(fdctrl); @@ -1709,7 +1709,7 @@ static const struct { uint8_t mask; const char* name; int parameters; - void (*handler)(fdctrl_t *fdctrl, int direction); + void (*handler)(a_fdctrl *fdctrl, int direction); int direction; } handlers[] = { { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ }, @@ -1748,9 +1748,9 @@ static const struct { /* Associate command to an index in the 'handlers' array */ static uint8_t command_to_handler[256]; -static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value) +static void fdctrl_write_data (a_fdctrl *fdctrl, uint32_t value) { - fdrive_t *cur_drv; + a_fdrive *cur_drv; int pos; /* Reset mode */ @@ -1815,8 +1815,8 @@ static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value) static void fdctrl_result_timer(void *opaque) { - fdctrl_t *fdctrl = opaque; - fdrive_t *cur_drv = get_cur_drv(fdctrl); + a_fdctrl *fdctrl = opaque; + a_fdrive *cur_drv = get_cur_drv(fdctrl); /* Pretend we are spinning. * This is needed for Coherent, which uses READ ID to check for @@ -1829,7 +1829,7 @@ static void fdctrl_result_timer(void *opaque) } /* Init functions */ -static void fdctrl_connect_drives(fdctrl_t *fdctrl, BlockDriverState **fds) +static void fdctrl_connect_drives(a_fdctrl *fdctrl, BlockDriverState **fds) { unsigned int i; @@ -1839,14 +1839,14 @@ static void fdctrl_connect_drives(fdctrl_t *fdctrl, BlockDriverState **fds) } } -fdctrl_t *fdctrl_init_isa(BlockDriverState **fds) +a_fdctrl *fdctrl_init_isa(BlockDriverState **fds) { - fdctrl_t *fdctrl; + a_fdctrl *fdctrl; ISADevice *dev; int dma_chann = 2; dev = isa_create_simple("isa-fdc"); - fdctrl = &(DO_UPCAST(fdctrl_isabus_t, busdev, dev)->state); + fdctrl = &(DO_UPCAST(a_fdctrl_isabus, busdev, dev)->state); fdctrl->dma_chann = dma_chann; DMA_register_channel(dma_chann, &fdctrl_transfer_handler, fdctrl); @@ -1856,17 +1856,17 @@ fdctrl_t *fdctrl_init_isa(BlockDriverState **fds) return fdctrl; } -fdctrl_t *fdctrl_init_sysbus(qemu_irq irq, int dma_chann, - target_phys_addr_t mmio_base, +a_fdctrl *fdctrl_init_sysbus(qemu_irq irq, int dma_chann, + a_target_phys_addr mmio_base, BlockDriverState **fds) { - fdctrl_t *fdctrl; + a_fdctrl *fdctrl; DeviceState *dev; - fdctrl_sysbus_t *sys; + a_fdctrl_sysbus *sys; dev = qdev_create(NULL, "sysbus-fdc"); qdev_init(dev); - sys = DO_UPCAST(fdctrl_sysbus_t, busdev.qdev, dev); + sys = DO_UPCAST(a_fdctrl_sysbus, busdev.qdev, dev); fdctrl = &sys->state; sysbus_connect_irq(&sys->busdev, 0, irq); sysbus_mmio_map(&sys->busdev, 0, mmio_base); @@ -1878,16 +1878,16 @@ fdctrl_t *fdctrl_init_sysbus(qemu_irq irq, int dma_chann, return fdctrl; } -fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base, +a_fdctrl *sun4m_fdctrl_init (qemu_irq irq, a_target_phys_addr io_base, BlockDriverState **fds, qemu_irq *fdc_tc) { DeviceState *dev; - fdctrl_sysbus_t *sys; - fdctrl_t *fdctrl; + a_fdctrl_sysbus *sys; + a_fdctrl *fdctrl; dev = qdev_create(NULL, "SUNW,fdtwo"); qdev_init(dev); - sys = DO_UPCAST(fdctrl_sysbus_t, busdev.qdev, dev); + sys = DO_UPCAST(a_fdctrl_sysbus, busdev.qdev, dev); fdctrl = &sys->state; sysbus_connect_irq(&sys->busdev, 0, irq); sysbus_mmio_map(&sys->busdev, 0, io_base); @@ -1900,7 +1900,7 @@ fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base, return fdctrl; } -static int fdctrl_init_common(fdctrl_t *fdctrl) +static int fdctrl_init_common(a_fdctrl *fdctrl) { int i, j; static int command_tables_inited = 0; @@ -1935,8 +1935,8 @@ static int fdctrl_init_common(fdctrl_t *fdctrl) static int isabus_fdc_init1(ISADevice *dev) { - fdctrl_isabus_t *isa = DO_UPCAST(fdctrl_isabus_t, busdev, dev); - fdctrl_t *fdctrl = &isa->state; + a_fdctrl_isabus *isa = DO_UPCAST(a_fdctrl_isabus, busdev, dev); + a_fdctrl *fdctrl = &isa->state; int iobase = 0x3f0; int isairq = 6; @@ -1955,7 +1955,7 @@ static int isabus_fdc_init1(ISADevice *dev) static int sysbus_fdc_init1(SysBusDevice *dev) { - fdctrl_t *fdctrl = &(FROM_SYSBUS(fdctrl_sysbus_t, dev)->state); + a_fdctrl *fdctrl = &(FROM_SYSBUS(a_fdctrl_sysbus, dev)->state); int io; io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl); @@ -1968,7 +1968,7 @@ static int sysbus_fdc_init1(SysBusDevice *dev) static int sun4m_fdc_init1(SysBusDevice *dev) { - fdctrl_t *fdctrl = &(FROM_SYSBUS(fdctrl_sysbus_t, dev)->state); + a_fdctrl *fdctrl = &(FROM_SYSBUS(a_fdctrl_sysbus, dev)->state); int io; io = cpu_register_io_memory(fdctrl_mem_read_strict, @@ -1984,19 +1984,19 @@ static int sun4m_fdc_init1(SysBusDevice *dev) static ISADeviceInfo isa_fdc_info = { .init = isabus_fdc_init1, .qdev.name = "isa-fdc", - .qdev.size = sizeof(fdctrl_isabus_t), + .qdev.size = sizeof(a_fdctrl_isabus), }; static SysBusDeviceInfo sysbus_fdc_info = { .init = sysbus_fdc_init1, .qdev.name = "sysbus-fdc", - .qdev.size = sizeof(fdctrl_sysbus_t), + .qdev.size = sizeof(a_fdctrl_sysbus), }; static SysBusDeviceInfo sun4m_fdc_info = { .init = sun4m_fdc_init1, .qdev.name = "SUNW,fdtwo", - .qdev.size = sizeof(fdctrl_sysbus_t), + .qdev.size = sizeof(a_fdctrl_sysbus), }; static void fdc_register_devices(void) @@ -1,12 +1,12 @@ /* fdc.c */ #define MAX_FD 2 -typedef struct fdctrl_t fdctrl_t; +typedef struct fdctrl a_fdctrl; -fdctrl_t *fdctrl_init_isa(BlockDriverState **fds); -fdctrl_t *fdctrl_init_sysbus(qemu_irq irq, int dma_chann, - target_phys_addr_t mmio_base, +a_fdctrl *fdctrl_init_isa(BlockDriverState **fds); +a_fdctrl *fdctrl_init_sysbus(qemu_irq irq, int dma_chann, + a_target_phys_addr mmio_base, BlockDriverState **fds); -fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base, +a_fdctrl *sun4m_fdctrl_init (qemu_irq irq, a_target_phys_addr io_base, BlockDriverState **fds, qemu_irq *fdc_tc); -int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num); +int fdctrl_get_drive_type(a_fdctrl *fdctrl, int drive_num); diff --git a/hw/flash.h b/hw/flash.h index 69aef8ce29..ac1c325ec7 100644 --- a/hw/flash.h +++ b/hw/flash.h @@ -1,15 +1,15 @@ /* NOR flash devices */ -typedef struct pflash_t pflash_t; +typedef struct pflash a_pflash; /* pflash_cfi01.c */ -pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off, +a_pflash *pflash_cfi01_register(a_target_phys_addr base, a_ram_addr off, BlockDriverState *bs, uint32_t sector_len, int nb_blocs, int width, uint16_t id0, uint16_t id1, uint16_t id2, uint16_t id3); /* pflash_cfi02.c */ -pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off, +a_pflash *pflash_cfi02_register(a_target_phys_addr base, a_ram_addr off, BlockDriverState *bs, uint32_t sector_len, int nb_blocs, int nb_mappings, int width, uint16_t id0, uint16_t id1, @@ -36,7 +36,7 @@ uint8_t nand_getio(NANDFlashState *s); #define NAND_MFR_MICRON 0x2c /* onenand.c */ -void onenand_base_update(void *opaque, target_phys_addr_t new); +void onenand_base_update(void *opaque, a_target_phys_addr new); void onenand_base_unmap(void *opaque); void *onenand_init(uint32_t id, int regshift, qemu_irq irq); void *onenand_raw_otp(void *opaque); diff --git a/hw/framebuffer.c b/hw/framebuffer.c index 24cdf25d0b..f60beff643 100644 --- a/hw/framebuffer.c +++ b/hw/framebuffer.c @@ -22,7 +22,7 @@ void framebuffer_update_display( DisplayState *ds, - target_phys_addr_t base, + a_target_phys_addr base, int cols, /* Width in pixels. */ int rows, /* Leight in pixels. */ int src_width, /* Length of source line, in bytes. */ @@ -34,16 +34,16 @@ void framebuffer_update_display( int *first_row, /* Input and output. */ int *last_row /* Output only */) { - target_phys_addr_t src_len; + a_target_phys_addr src_len; uint8_t *dest; uint8_t *src; uint8_t *src_base; int first, last = 0; int dirty; int i; - ram_addr_t addr; - ram_addr_t pd; - ram_addr_t pd2; + a_ram_addr addr; + a_ram_addr pd; + a_ram_addr pd2; i = *first_row; *first_row = -1; @@ -86,7 +86,7 @@ void framebuffer_update_display( dest += i * dest_row_pitch; for (; i < rows; i++) { - target_phys_addr_t dirty_offset; + a_target_phys_addr dirty_offset; dirty = 0; dirty_offset = 0; while (addr + dirty_offset < TARGET_PAGE_ALIGN(addr + src_width)) { diff --git a/hw/framebuffer.h b/hw/framebuffer.h index a3a214649d..22d57350d6 100644 --- a/hw/framebuffer.h +++ b/hw/framebuffer.h @@ -7,7 +7,7 @@ typedef void (*drawfn)(void *, uint8_t *, const uint8_t *, int, int); void framebuffer_update_display( DisplayState *ds, - target_phys_addr_t base, + a_target_phys_addr base, int cols, int rows, int src_width, diff --git a/hw/fw_cfg.c b/hw/fw_cfg.c index 37fe3b3580..bd57416f90 100644 --- a/hw/fw_cfg.c +++ b/hw/fw_cfg.c @@ -116,18 +116,18 @@ static void fw_cfg_io_writew(void *opaque, uint32_t addr, uint32_t value) fw_cfg_select(opaque, (uint16_t)value); } -static uint32_t fw_cfg_mem_readb(void *opaque, target_phys_addr_t addr) +static uint32_t fw_cfg_mem_readb(void *opaque, a_target_phys_addr addr) { return fw_cfg_read(opaque); } -static void fw_cfg_mem_writeb(void *opaque, target_phys_addr_t addr, +static void fw_cfg_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t value) { fw_cfg_write(opaque, (uint8_t)value); } -static void fw_cfg_mem_writew(void *opaque, target_phys_addr_t addr, +static void fw_cfg_mem_writew(void *opaque, a_target_phys_addr addr, uint32_t value) { fw_cfg_select(opaque, (uint16_t)value); @@ -242,7 +242,7 @@ int fw_cfg_add_callback(void *opaque, uint16_t key, FWCfgCallback callback, } void *fw_cfg_init(uint32_t ctl_port, uint32_t data_port, - target_phys_addr_t ctl_addr, target_phys_addr_t data_addr) + a_target_phys_addr ctl_addr, a_target_phys_addr data_addr) { FWCfgState *s; int io_ctl_memory, io_data_memory; diff --git a/hw/fw_cfg.h b/hw/fw_cfg.h index 30dfec7c6c..db835d04bd 100644 --- a/hw/fw_cfg.h +++ b/hw/fw_cfg.h @@ -35,7 +35,7 @@ int fw_cfg_add_i64(void *opaque, uint16_t key, uint64_t value); int fw_cfg_add_callback(void *opaque, uint16_t key, FWCfgCallback callback, void *callback_opaque, uint8_t *data, size_t len); void *fw_cfg_init(uint32_t ctl_port, uint32_t data_port, - target_phys_addr_t crl_addr, target_phys_addr_t data_addr); + a_target_phys_addr crl_addr, a_target_phys_addr data_addr); #endif /* NO_QEMU_PROTOS */ diff --git a/hw/g364fb.c b/hw/g364fb.c index d1d2c12d6c..548f675779 100644 --- a/hw/g364fb.c +++ b/hw/g364fb.c @@ -36,7 +36,7 @@ do { fprintf(stderr, "g364 ERROR: " fmt , ## __VA_ARGS__);} while (0) typedef struct G364State { /* hardware */ uint8_t *vram; - ram_addr_t vram_offset; + a_ram_addr vram_offset; int vram_size; qemu_irq irq; /* registers */ @@ -68,13 +68,13 @@ typedef struct G364State { #define CTLA_FORCE_BLANK 0x00000400 #define CTLA_NO_CURSOR 0x00800000 -static inline int check_dirty(ram_addr_t page) +static inline int check_dirty(a_ram_addr page) { return cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG); } static inline void reset_dirty(G364State *s, - ram_addr_t page_min, ram_addr_t page_max) + a_ram_addr page_min, a_ram_addr page_max) { cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE - 1, VGA_DIRTY_FLAG); @@ -85,7 +85,7 @@ static void g364fb_draw_graphic8(G364State *s) int i, w; uint8_t *vram; uint8_t *data_display, *dd; - ram_addr_t page, page_min, page_max; + a_ram_addr page, page_min, page_max; int x, y; int xmin, xmax; int ymin, ymax; @@ -115,7 +115,7 @@ static void g364fb_draw_graphic8(G364State *s) } page = s->vram_offset; - page_min = (ram_addr_t)-1; + page_min = (a_ram_addr)-1; page_max = 0; x = y = 0; @@ -138,7 +138,7 @@ static void g364fb_draw_graphic8(G364State *s) if (check_dirty(page)) { if (y < ymin) ymin = ymax = y; - if (page_min == (ram_addr_t)-1) + if (page_min == (a_ram_addr)-1) page_min = page; page_max = page; if (x < xmin) @@ -197,9 +197,9 @@ static void g364fb_draw_graphic8(G364State *s) ymax = y; } else { int dy; - if (page_min != (ram_addr_t)-1) { + if (page_min != (a_ram_addr)-1) { reset_dirty(s, page_min, page_max); - page_min = (ram_addr_t)-1; + page_min = (a_ram_addr)-1; page_max = 0; dpy_update(s->ds, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1); xmin = s->width; @@ -219,7 +219,7 @@ static void g364fb_draw_graphic8(G364State *s) } done: - if (page_min != (ram_addr_t)-1) { + if (page_min != (a_ram_addr)-1) { dpy_update(s->ds, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1); reset_dirty(s, page_min, page_max); } @@ -336,7 +336,7 @@ static void g364fb_screen_dump(void *opaque, const char *filename) } /* called for accesses to io ports */ -static uint32_t g364fb_ctrl_readl(void *opaque, target_phys_addr_t addr) +static uint32_t g364fb_ctrl_readl(void *opaque, a_target_phys_addr addr) { G364State *s = opaque; uint32_t val; @@ -379,7 +379,7 @@ static uint32_t g364fb_ctrl_readl(void *opaque, target_phys_addr_t addr) return val; } -static uint32_t g364fb_ctrl_readw(void *opaque, target_phys_addr_t addr) +static uint32_t g364fb_ctrl_readw(void *opaque, a_target_phys_addr addr) { uint32_t v = g364fb_ctrl_readl(opaque, addr & ~0x3); if (addr & 0x2) @@ -388,7 +388,7 @@ static uint32_t g364fb_ctrl_readw(void *opaque, target_phys_addr_t addr) return v & 0xffff; } -static uint32_t g364fb_ctrl_readb(void *opaque, target_phys_addr_t addr) +static uint32_t g364fb_ctrl_readb(void *opaque, a_target_phys_addr addr) { uint32_t v = g364fb_ctrl_readl(opaque, addr & ~0x3); return (v >> (8 * (addr & 0x3))) & 0xff; @@ -415,7 +415,7 @@ static void g364_invalidate_cursor_position(G364State *s) } } -static void g364fb_ctrl_writel(void *opaque, target_phys_addr_t addr, uint32_t val) +static void g364fb_ctrl_writel(void *opaque, a_target_phys_addr addr, uint32_t val) { G364State *s = opaque; @@ -490,7 +490,7 @@ static void g364fb_ctrl_writel(void *opaque, target_phys_addr_t addr, uint32_t v qemu_irq_lower(s->irq); } -static void g364fb_ctrl_writew(void *opaque, target_phys_addr_t addr, uint32_t val) +static void g364fb_ctrl_writew(void *opaque, a_target_phys_addr addr, uint32_t val) { uint32_t old_val = g364fb_ctrl_readl(opaque, addr & ~0x3); @@ -501,7 +501,7 @@ static void g364fb_ctrl_writew(void *opaque, target_phys_addr_t addr, uint32_t v g364fb_ctrl_writel(opaque, addr & ~0x3, val); } -static void g364fb_ctrl_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) +static void g364fb_ctrl_writeb(void *opaque, a_target_phys_addr addr, uint32_t val) { uint32_t old_val = g364fb_ctrl_readl(opaque, addr & ~0x3); @@ -583,8 +583,8 @@ static void g364fb_save(QEMUFile *f, void *opaque) qemu_put_be32(f, s->height); } -int g364fb_mm_init(target_phys_addr_t vram_base, - target_phys_addr_t ctrl_base, int it_shift, +int g364fb_mm_init(a_target_phys_addr vram_base, + a_target_phys_addr ctrl_base, int it_shift, qemu_irq irq) { G364State *s; diff --git a/hw/grackle_pci.c b/hw/grackle_pci.c index d878cf6748..555abd5c45 100644 --- a/hw/grackle_pci.c +++ b/hw/grackle_pci.c @@ -37,7 +37,7 @@ #define GRACKLE_DPRINTF(fmt, ...) #endif -typedef target_phys_addr_t pci_addr_t; +typedef a_target_phys_addr a_pci_addr; #include "pci_host.h" typedef struct GrackleState { @@ -45,7 +45,7 @@ typedef struct GrackleState { PCIHostState host_state; } GrackleState; -static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr, +static void pci_grackle_config_writel (void *opaque, a_target_phys_addr addr, uint32_t val) { GrackleState *s = opaque; @@ -58,7 +58,7 @@ static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr, s->host_state.config_reg = val; } -static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr) +static uint32_t pci_grackle_config_readl (void *opaque, a_target_phys_addr addr) { GrackleState *s = opaque; uint32_t val; diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c index 8f9ae4a20c..87d13f9981 100644 --- a/hw/gt64xxx.c +++ b/hw/gt64xxx.c @@ -27,7 +27,7 @@ #include "pci.h" #include "pc.h" -typedef target_phys_addr_t pci_addr_t; +typedef a_target_phys_addr a_pci_addr; #include "pci_host.h" //#define DEBUG @@ -229,8 +229,8 @@ typedef target_phys_addr_t pci_addr_t; typedef PCIHostState GT64120PCIState; #define PCI_MAPPING_ENTRY(regname) \ - target_phys_addr_t regname ##_start; \ - target_phys_addr_t regname ##_length; \ + a_target_phys_addr regname ##_start; \ + a_target_phys_addr regname ##_length; \ int regname ##_handle typedef struct GT64120State { @@ -243,11 +243,11 @@ typedef struct GT64120State { /* Adjust range to avoid touching space which isn't mappable via PCI */ /* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000 0x1fc00000 - 0x1fd00000 */ -static void check_reserved_space (target_phys_addr_t *start, - target_phys_addr_t *length) +static void check_reserved_space (a_target_phys_addr *start, + a_target_phys_addr *length) { - target_phys_addr_t begin = *start; - target_phys_addr_t end = *start + *length; + a_target_phys_addr begin = *start; + a_target_phys_addr end = *start + *length; if (end >= 0x1e000000LL && end < 0x1f100000LL) end = 0x1e000000LL; @@ -269,8 +269,8 @@ static void check_reserved_space (target_phys_addr_t *start, static void gt64120_isd_mapping(GT64120State *s) { - target_phys_addr_t start = s->regs[GT_ISD] << 21; - target_phys_addr_t length = 0x1000; + a_target_phys_addr start = s->regs[GT_ISD] << 21; + a_target_phys_addr length = 0x1000; if (s->ISD_length) cpu_register_physical_memory(s->ISD_start, s->ISD_length, @@ -303,7 +303,7 @@ static void gt64120_pci_mapping(GT64120State *s) } } -static void gt64120_writel (void *opaque, target_phys_addr_t addr, +static void gt64120_writel (void *opaque, a_target_phys_addr addr, uint32_t val) { GT64120State *s = opaque; @@ -583,7 +583,7 @@ static void gt64120_writel (void *opaque, target_phys_addr_t addr, } static uint32_t gt64120_readl (void *opaque, - target_phys_addr_t addr) + a_target_phys_addr addr) { GT64120State *s = opaque; uint32_t val; diff --git a/hw/gumstix.c b/hw/gumstix.c index 8fbf64c0f3..c3f214859b 100644 --- a/hw/gumstix.c +++ b/hw/gumstix.c @@ -41,7 +41,7 @@ static const int sector_len = 128 * 1024; -static void connex_init(ram_addr_t ram_size, +static void connex_init(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -75,7 +75,7 @@ static void connex_init(ram_addr_t ram_size, pxa2xx_gpio_in_get(cpu->gpio)[36]); } -static void verdex_init(ram_addr_t ram_size, +static void verdex_init(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) diff --git a/hw/heathrow_pic.c b/hw/heathrow_pic.c index 500b9f19bf..c3c8db615f 100644 --- a/hw/heathrow_pic.c +++ b/hw/heathrow_pic.c @@ -62,7 +62,7 @@ static void heathrow_pic_update(HeathrowPICS *s) } } -static void pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value) +static void pic_writel (void *opaque, a_target_phys_addr addr, uint32_t value) { HeathrowPICS *s = opaque; HeathrowPIC *pic; @@ -92,7 +92,7 @@ static void pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value) } } -static uint32_t pic_readl (void *opaque, target_phys_addr_t addr) +static uint32_t pic_readl (void *opaque, a_target_phys_addr addr) { HeathrowPICS *s = opaque; HeathrowPIC *pic; @@ -270,20 +270,20 @@ static void hpet_del_timer(HPETTimer *t) } #ifdef HPET_DEBUG -static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr) +static uint32_t hpet_ram_readb(void *opaque, a_target_phys_addr addr) { printf("qemu: hpet_read b at %" PRIx64 "\n", addr); return 0; } -static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr) +static uint32_t hpet_ram_readw(void *opaque, a_target_phys_addr addr) { printf("qemu: hpet_read w at %" PRIx64 "\n", addr); return 0; } #endif -static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr) +static uint32_t hpet_ram_readl(void *opaque, a_target_phys_addr addr) { HPETState *s = (HPETState *)opaque; uint64_t cur_tick, index; @@ -350,14 +350,14 @@ static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr) } #ifdef HPET_DEBUG -static void hpet_ram_writeb(void *opaque, target_phys_addr_t addr, +static void hpet_ram_writeb(void *opaque, a_target_phys_addr addr, uint32_t value) { printf("qemu: invalid hpet_write b at %" PRIx64 " = %#x\n", addr, value); } -static void hpet_ram_writew(void *opaque, target_phys_addr_t addr, +static void hpet_ram_writew(void *opaque, a_target_phys_addr addr, uint32_t value) { printf("qemu: invalid hpet_write w at %" PRIx64 " = %#x\n", @@ -365,7 +365,7 @@ static void hpet_ram_writew(void *opaque, target_phys_addr_t addr, } #endif -static void hpet_ram_writel(void *opaque, target_phys_addr_t addr, +static void hpet_ram_writel(void *opaque, a_target_phys_addr addr, uint32_t value) { int i; @@ -18,7 +18,7 @@ int pmac_ide_init (DriveInfo **hd_table, qemu_irq irq, void *dbdma, int channel, qemu_irq dma_irq); /* ide-mmio.c */ -void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2, +void mmio_ide_init (a_target_phys_addr membase, a_target_phys_addr membase2, qemu_irq irq, int shift, DriveInfo *hd0, DriveInfo *hd1); diff --git a/hw/ide/macio.c b/hw/ide/macio.c index a11223e6f0..692023d42d 100644 --- a/hw/ide/macio.c +++ b/hw/ide/macio.c @@ -178,7 +178,7 @@ static void pmac_ide_flush(DBDMA_io *io) /* PowerMac IDE memory IO */ static void pmac_ide_writeb (void *opaque, - target_phys_addr_t addr, uint32_t val) + a_target_phys_addr addr, uint32_t val) { MACIOIDEState *d = opaque; @@ -196,7 +196,7 @@ static void pmac_ide_writeb (void *opaque, } } -static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr) +static uint32_t pmac_ide_readb (void *opaque,a_target_phys_addr addr) { uint8_t retval; MACIOIDEState *d = opaque; @@ -218,7 +218,7 @@ static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr) } static void pmac_ide_writew (void *opaque, - target_phys_addr_t addr, uint32_t val) + a_target_phys_addr addr, uint32_t val) { MACIOIDEState *d = opaque; @@ -231,7 +231,7 @@ static void pmac_ide_writew (void *opaque, } } -static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr) +static uint32_t pmac_ide_readw (void *opaque,a_target_phys_addr addr) { uint16_t retval; MACIOIDEState *d = opaque; @@ -249,7 +249,7 @@ static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr) } static void pmac_ide_writel (void *opaque, - target_phys_addr_t addr, uint32_t val) + a_target_phys_addr addr, uint32_t val) { MACIOIDEState *d = opaque; @@ -262,7 +262,7 @@ static void pmac_ide_writel (void *opaque, } } -static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr) +static uint32_t pmac_ide_readl (void *opaque,a_target_phys_addr addr) { uint32_t retval; MACIOIDEState *d = opaque; diff --git a/hw/ide/mmio.c b/hw/ide/mmio.c index acaa900c89..a1a7606299 100644 --- a/hw/ide/mmio.c +++ b/hw/ide/mmio.c @@ -41,7 +41,7 @@ typedef struct { int shift; } MMIOState; -static uint32_t mmio_ide_read (void *opaque, target_phys_addr_t addr) +static uint32_t mmio_ide_read (void *opaque, a_target_phys_addr addr) { MMIOState *s = (MMIOState*)opaque; IDEBus *bus = s->bus; @@ -52,7 +52,7 @@ static uint32_t mmio_ide_read (void *opaque, target_phys_addr_t addr) return ide_data_readw(bus, 0); } -static void mmio_ide_write (void *opaque, target_phys_addr_t addr, +static void mmio_ide_write (void *opaque, a_target_phys_addr addr, uint32_t val) { MMIOState *s = (MMIOState*)opaque; @@ -76,14 +76,14 @@ static CPUWriteMemoryFunc * const mmio_ide_writes[] = { mmio_ide_write, }; -static uint32_t mmio_ide_status_read (void *opaque, target_phys_addr_t addr) +static uint32_t mmio_ide_status_read (void *opaque, a_target_phys_addr addr) { MMIOState *s= (MMIOState*)opaque; IDEBus *bus = s->bus; return ide_status_read(bus, 0); } -static void mmio_ide_cmd_write (void *opaque, target_phys_addr_t addr, +static void mmio_ide_cmd_write (void *opaque, a_target_phys_addr addr, uint32_t val) { MMIOState *s = (MMIOState*)opaque; @@ -122,7 +122,7 @@ static int mmio_ide_load(QEMUFile* f, void *opaque, int version_id) return 0; } -void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2, +void mmio_ide_init (a_target_phys_addr membase, a_target_phys_addr membase2, qemu_irq irq, int shift, DriveInfo *hd0, DriveInfo *hd1) { diff --git a/hw/integratorcp.c b/hw/integratorcp.c index 21e7712a6d..2f3e44d4db 100644 --- a/hw/integratorcp.c +++ b/hw/integratorcp.c @@ -37,7 +37,7 @@ static uint8_t integrator_spd[128] = { 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40 }; -static uint32_t integratorcm_read(void *opaque, target_phys_addr_t offset) +static uint32_t integratorcm_read(void *opaque, a_target_phys_addr offset) { integratorcm_state *s = (integratorcm_state *)opaque; if (offset >= 0x100 && offset < 0x200) { @@ -138,7 +138,7 @@ static void integratorcm_update(integratorcm_state *s) hw_error("Core module interrupt\n"); } -static void integratorcm_write(void *opaque, target_phys_addr_t offset, +static void integratorcm_write(void *opaque, a_target_phys_addr offset, uint32_t value) { integratorcm_state *s = (integratorcm_state *)opaque; @@ -296,7 +296,7 @@ static void icp_pic_set_irq(void *opaque, int irq, int level) icp_pic_update(s); } -static uint32_t icp_pic_read(void *opaque, target_phys_addr_t offset) +static uint32_t icp_pic_read(void *opaque, a_target_phys_addr offset) { icp_pic_state *s = (icp_pic_state *)opaque; @@ -324,7 +324,7 @@ static uint32_t icp_pic_read(void *opaque, target_phys_addr_t offset) } } -static void icp_pic_write(void *opaque, target_phys_addr_t offset, +static void icp_pic_write(void *opaque, a_target_phys_addr offset, uint32_t value) { icp_pic_state *s = (icp_pic_state *)opaque; @@ -388,7 +388,7 @@ static int icp_pic_init(SysBusDevice *dev) } /* CP control registers. */ -static uint32_t icp_control_read(void *opaque, target_phys_addr_t offset) +static uint32_t icp_control_read(void *opaque, a_target_phys_addr offset) { switch (offset >> 2) { case 0: /* CP_IDFIELD */ @@ -405,7 +405,7 @@ static uint32_t icp_control_read(void *opaque, target_phys_addr_t offset) } } -static void icp_control_write(void *opaque, target_phys_addr_t offset, +static void icp_control_write(void *opaque, a_target_phys_addr offset, uint32_t value) { switch (offset >> 2) { @@ -448,13 +448,13 @@ static struct arm_boot_info integrator_binfo = { .board_id = 0x113, }; -static void integratorcp_init(ram_addr_t ram_size, +static void integratorcp_init(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { CPUState *env; - ram_addr_t ram_offset; + a_ram_addr ram_offset; qemu_irq pic[32]; qemu_irq *cpu_pic; DeviceState *dev; diff --git a/hw/ioapic.c b/hw/ioapic.c index b0ad78f241..1186a18bb2 100644 --- a/hw/ioapic.c +++ b/hw/ioapic.c @@ -119,7 +119,7 @@ void ioapic_set_irq(void *opaque, int vector, int level) } } -static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr) +static uint32_t ioapic_mem_readl(void *opaque, a_target_phys_addr addr) { IOAPICState *s = opaque; int index; @@ -155,7 +155,7 @@ static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr) return val; } -static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) +static void ioapic_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val) { IOAPICState *s = opaque; int index; diff --git a/hw/iommu.c b/hw/iommu.c index 20da7ab969..3fe0397005 100644 --- a/hw/iommu.c +++ b/hw/iommu.c @@ -130,15 +130,15 @@ typedef struct IOMMUState { SysBusDevice busdev; uint32_t regs[IOMMU_NREGS]; - target_phys_addr_t iostart; + a_target_phys_addr iostart; uint32_t version; qemu_irq irq; } IOMMUState; -static uint32_t iommu_mem_readl(void *opaque, target_phys_addr_t addr) +static uint32_t iommu_mem_readl(void *opaque, a_target_phys_addr addr) { IOMMUState *s = opaque; - target_phys_addr_t saddr; + a_target_phys_addr saddr; uint32_t ret; saddr = addr >> 2; @@ -156,11 +156,11 @@ static uint32_t iommu_mem_readl(void *opaque, target_phys_addr_t addr) return ret; } -static void iommu_mem_writel(void *opaque, target_phys_addr_t addr, +static void iommu_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val) { IOMMUState *s = opaque; - target_phys_addr_t saddr; + a_target_phys_addr saddr; saddr = addr >> 2; DPRINTF("write reg[%d] = %x\n", (int)saddr, val); @@ -250,12 +250,12 @@ static CPUWriteMemoryFunc * const iommu_mem_write[3] = { iommu_mem_writel, }; -static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr) +static uint32_t iommu_page_get_flags(IOMMUState *s, a_target_phys_addr addr) { uint32_t ret; - target_phys_addr_t iopte; + a_target_phys_addr iopte; #ifdef DEBUG_IOMMU - target_phys_addr_t pa = addr; + a_target_phys_addr pa = addr; #endif iopte = s->regs[IOMMU_BASE] << 4; @@ -269,11 +269,11 @@ static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr) return ret; } -static target_phys_addr_t iommu_translate_pa(target_phys_addr_t addr, +static a_target_phys_addr iommu_translate_pa(a_target_phys_addr addr, uint32_t pte) { uint32_t tmppte; - target_phys_addr_t pa; + a_target_phys_addr pa; tmppte = pte; pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK); @@ -283,7 +283,7 @@ static target_phys_addr_t iommu_translate_pa(target_phys_addr_t addr, return pa; } -static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr, +static void iommu_bad_addr(IOMMUState *s, a_target_phys_addr addr, int is_write) { DPRINTF("bad addr " TARGET_FMT_plx "\n", addr); @@ -295,12 +295,12 @@ static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr, qemu_irq_raise(s->irq); } -void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr, +void sparc_iommu_memory_rw(void *opaque, a_target_phys_addr addr, uint8_t *buf, int len, int is_write) { int l; uint32_t flags; - target_phys_addr_t page, phys_addr; + a_target_phys_addr page, phys_addr; while (len > 0) { page = addr & IOMMU_PAGE_MASK; @@ -30,9 +30,9 @@ void isa_qdev_register(ISADeviceInfo *info); ISADevice *isa_create(const char *name); ISADevice *isa_create_simple(const char *name); -extern target_phys_addr_t isa_mem_base; +extern a_target_phys_addr isa_mem_base; -void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size); +void isa_mmio_init(a_target_phys_addr base, a_target_phys_addr size); /* dma.c */ int DMA_get_channel_mode (int nchan); diff --git a/hw/isa_mmio.c b/hw/isa_mmio.c index ed0e189c8c..6a1967bab6 100644 --- a/hw/isa_mmio.c +++ b/hw/isa_mmio.c @@ -25,13 +25,13 @@ #include "hw.h" #include "isa.h" -static void isa_mmio_writeb (void *opaque, target_phys_addr_t addr, +static void isa_mmio_writeb (void *opaque, a_target_phys_addr addr, uint32_t val) { cpu_outb(addr & IOPORTS_MASK, val); } -static void isa_mmio_writew (void *opaque, target_phys_addr_t addr, +static void isa_mmio_writew (void *opaque, a_target_phys_addr addr, uint32_t val) { #ifdef TARGET_WORDS_BIGENDIAN @@ -40,7 +40,7 @@ static void isa_mmio_writew (void *opaque, target_phys_addr_t addr, cpu_outw(addr & IOPORTS_MASK, val); } -static void isa_mmio_writel (void *opaque, target_phys_addr_t addr, +static void isa_mmio_writel (void *opaque, a_target_phys_addr addr, uint32_t val) { #ifdef TARGET_WORDS_BIGENDIAN @@ -49,7 +49,7 @@ static void isa_mmio_writel (void *opaque, target_phys_addr_t addr, cpu_outl(addr & IOPORTS_MASK, val); } -static uint32_t isa_mmio_readb (void *opaque, target_phys_addr_t addr) +static uint32_t isa_mmio_readb (void *opaque, a_target_phys_addr addr) { uint32_t val; @@ -57,7 +57,7 @@ static uint32_t isa_mmio_readb (void *opaque, target_phys_addr_t addr) return val; } -static uint32_t isa_mmio_readw (void *opaque, target_phys_addr_t addr) +static uint32_t isa_mmio_readw (void *opaque, a_target_phys_addr addr) { uint32_t val; @@ -68,7 +68,7 @@ static uint32_t isa_mmio_readw (void *opaque, target_phys_addr_t addr) return val; } -static uint32_t isa_mmio_readl (void *opaque, target_phys_addr_t addr) +static uint32_t isa_mmio_readl (void *opaque, a_target_phys_addr addr) { uint32_t val; @@ -93,7 +93,7 @@ static CPUReadMemoryFunc * const isa_mmio_read[] = { static int isa_mmio_iomemtype = 0; -void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size) +void isa_mmio_init(a_target_phys_addr base, a_target_phys_addr size) { if (!isa_mmio_iomemtype) { isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read, diff --git a/hw/jazz_led.c b/hw/jazz_led.c index 18780e9371..2df0e7f44e 100644 --- a/hw/jazz_led.c +++ b/hw/jazz_led.c @@ -31,15 +31,15 @@ typedef enum { REDRAW_NONE = 0, REDRAW_SEGMENTS = 1, REDRAW_BACKGROUND = 2, -} screen_state_t; +} e_screen_state; typedef struct LedState { uint8_t segments; DisplayState *ds; - screen_state_t state; + e_screen_state state; } LedState; -static uint32_t led_readb(void *opaque, target_phys_addr_t addr) +static uint32_t led_readb(void *opaque, a_target_phys_addr addr) { LedState *s = opaque; uint32_t val; @@ -58,7 +58,7 @@ static uint32_t led_readb(void *opaque, target_phys_addr_t addr) return val; } -static uint32_t led_readw(void *opaque, target_phys_addr_t addr) +static uint32_t led_readw(void *opaque, a_target_phys_addr addr) { uint32_t v; #ifdef TARGET_WORDS_BIGENDIAN @@ -71,7 +71,7 @@ static uint32_t led_readw(void *opaque, target_phys_addr_t addr) return v; } -static uint32_t led_readl(void *opaque, target_phys_addr_t addr) +static uint32_t led_readl(void *opaque, a_target_phys_addr addr) { uint32_t v; #ifdef TARGET_WORDS_BIGENDIAN @@ -88,7 +88,7 @@ static uint32_t led_readl(void *opaque, target_phys_addr_t addr) return v; } -static void led_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) +static void led_writeb(void *opaque, a_target_phys_addr addr, uint32_t val) { LedState *s = opaque; @@ -105,7 +105,7 @@ static void led_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) } } -static void led_writew(void *opaque, target_phys_addr_t addr, uint32_t val) +static void led_writew(void *opaque, a_target_phys_addr addr, uint32_t val) { #ifdef TARGET_WORDS_BIGENDIAN led_writeb(opaque, addr, (val >> 8) & 0xff); @@ -116,7 +116,7 @@ static void led_writew(void *opaque, target_phys_addr_t addr, uint32_t val) #endif } -static void led_writel(void *opaque, target_phys_addr_t addr, uint32_t val) +static void led_writel(void *opaque, a_target_phys_addr addr, uint32_t val) { #ifdef TARGET_WORDS_BIGENDIAN led_writeb(opaque, addr, (val >> 24) & 0xff); @@ -282,7 +282,7 @@ static void jazz_led_screen_dump(void *opaque, const char *filename) printf("jazz_led_screen_dump() not implemented\n"); } -static void jazz_led_text_update(void *opaque, console_ch_t *chardata) +static void jazz_led_text_update(void *opaque, a_console_ch *chardata) { LedState *s = opaque; char buf[2]; @@ -298,7 +298,7 @@ static void jazz_led_text_update(void *opaque, console_ch_t *chardata) dpy_update(s->ds, 0, 0, 2, 1); } -void jazz_led_init(target_phys_addr_t base) +void jazz_led_init(a_target_phys_addr base) { LedState *s; int io; diff --git a/hw/loader.c b/hw/loader.c index 5d83a66041..16ea3f6481 100644 --- a/hw/loader.c +++ b/hw/loader.c @@ -81,10 +81,10 @@ int load_image(const char *filename, uint8_t *addr) } /* return the amount read, just like fread. 0 may mean error or eof */ -int fread_targphys(target_phys_addr_t dst_addr, size_t nbytes, FILE *f) +int fread_targphys(a_target_phys_addr dst_addr, size_t nbytes, FILE *f) { uint8_t buf[4096]; - target_phys_addr_t dst_begin = dst_addr; + a_target_phys_addr dst_begin = dst_addr; size_t want, did; while (nbytes) { @@ -101,16 +101,16 @@ int fread_targphys(target_phys_addr_t dst_addr, size_t nbytes, FILE *f) } /* returns 0 on error, 1 if ok */ -int fread_targphys_ok(target_phys_addr_t dst_addr, size_t nbytes, FILE *f) +int fread_targphys_ok(a_target_phys_addr dst_addr, size_t nbytes, FILE *f) { return fread_targphys(dst_addr, nbytes, f) == nbytes; } /* read()-like version */ -int read_targphys(int fd, target_phys_addr_t dst_addr, size_t nbytes) +int read_targphys(int fd, a_target_phys_addr dst_addr, size_t nbytes) { uint8_t buf[4096]; - target_phys_addr_t dst_begin = dst_addr; + a_target_phys_addr dst_begin = dst_addr; size_t want, did; while (nbytes) { @@ -127,7 +127,7 @@ int read_targphys(int fd, target_phys_addr_t dst_addr, size_t nbytes) /* return the size or -1 if error */ int load_image_targphys(const char *filename, - target_phys_addr_t addr, int max_sz) + a_target_phys_addr addr, int max_sz) { FILE *f; size_t got; @@ -142,7 +142,7 @@ int load_image_targphys(const char *filename, return got; } -void pstrcpy_targphys(target_phys_addr_t dest, int buf_size, +void pstrcpy_targphys(a_target_phys_addr dest, int buf_size, const char *source) { static const uint8_t nul_byte = 0; @@ -204,8 +204,8 @@ static void bswap_ahdr(struct exec *e) : (_N_SEGMENT_ROUND (_N_TXTENDADDR(x, target_page_size), target_page_size))) -int load_aout(const char *filename, target_phys_addr_t addr, int max_sz, - int bswap_needed, target_phys_addr_t target_page_size) +int load_aout(const char *filename, a_target_phys_addr addr, int max_sz, + int bswap_needed, a_target_phys_addr target_page_size) { int fd, size, ret; struct exec e; @@ -358,7 +358,7 @@ int load_elf(const char *filename, int64_t address_offset, return -1; } -static void bswap_uboot_header(uboot_image_header_t *hdr) +static void bswap_uboot_header(an_uboot_image_header *hdr) { #ifndef HOST_WORDS_BIGENDIAN bswap32s(&hdr->ih_magic); @@ -457,13 +457,13 @@ static ssize_t gunzip(void *dst, size_t dstlen, uint8_t *src, } /* Load a U-Boot image. */ -int load_uimage(const char *filename, target_phys_addr_t *ep, - target_phys_addr_t *loadaddr, int *is_linux) +int load_uimage(const char *filename, a_target_phys_addr *ep, + a_target_phys_addr *loadaddr, int *is_linux) { int fd; int size; - uboot_image_header_t h; - uboot_image_header_t *hdr = &h; + an_uboot_image_header h; + an_uboot_image_header *hdr = &h; uint8_t *data = NULL; int ret = -1; @@ -471,7 +471,7 @@ int load_uimage(const char *filename, target_phys_addr_t *ep, if (fd < 0) return -1; - size = read(fd, hdr, sizeof(uboot_image_header_t)); + size = read(fd, hdr, sizeof(an_uboot_image_header)); if (size < 0) goto out; diff --git a/hw/loader.h b/hw/loader.h index 3632008928..23443b2840 100644 --- a/hw/loader.h +++ b/hw/loader.h @@ -4,18 +4,18 @@ /* loader.c */ int get_image_size(const char *filename); int load_image(const char *filename, uint8_t *addr); /* deprecated */ -int load_image_targphys(const char *filename, target_phys_addr_t, int max_sz); +int load_image_targphys(const char *filename, a_target_phys_addr, int max_sz); int load_elf(const char *filename, int64_t address_offset, uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr, int big_endian, int elf_machine, int clear_lsb); -int load_aout(const char *filename, target_phys_addr_t addr, int max_sz, - int bswap_needed, target_phys_addr_t target_page_size); -int load_uimage(const char *filename, target_phys_addr_t *ep, - target_phys_addr_t *loadaddr, int *is_linux); +int load_aout(const char *filename, a_target_phys_addr addr, int max_sz, + int bswap_needed, a_target_phys_addr target_page_size); +int load_uimage(const char *filename, a_target_phys_addr *ep, + a_target_phys_addr *loadaddr, int *is_linux); -int fread_targphys(target_phys_addr_t dst_addr, size_t nbytes, FILE *f); -int fread_targphys_ok(target_phys_addr_t dst_addr, size_t nbytes, FILE *f); -int read_targphys(int fd, target_phys_addr_t dst_addr, size_t nbytes); -void pstrcpy_targphys(target_phys_addr_t dest, int buf_size, +int fread_targphys(a_target_phys_addr dst_addr, size_t nbytes, FILE *f); +int fread_targphys_ok(a_target_phys_addr dst_addr, size_t nbytes, FILE *f); +int read_targphys(int fd, a_target_phys_addr dst_addr, size_t nbytes); +void pstrcpy_targphys(a_target_phys_addr dest, int buf_size, const char *source); #endif diff --git a/hw/lsi53c895a.c b/hw/lsi53c895a.c index 62bdca8032..e47c164817 100644 --- a/hw/lsi53c895a.c +++ b/hw/lsi53c895a.c @@ -484,7 +484,7 @@ static void lsi_resume_script(LSIState *s) static void lsi_do_dma(LSIState *s, int out) { uint32_t count; - target_phys_addr_t addr; + a_target_phys_addr addr; if (!s->current_dma_len) { /* Wait until data is available. */ @@ -1723,14 +1723,14 @@ static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val) #undef CASE_SET_REG32 } -static void lsi_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) +static void lsi_mmio_writeb(void *opaque, a_target_phys_addr addr, uint32_t val) { LSIState *s = opaque; lsi_reg_writeb(s, addr & 0xff, val); } -static void lsi_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) +static void lsi_mmio_writew(void *opaque, a_target_phys_addr addr, uint32_t val) { LSIState *s = opaque; @@ -1739,7 +1739,7 @@ static void lsi_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff); } -static void lsi_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) +static void lsi_mmio_writel(void *opaque, a_target_phys_addr addr, uint32_t val) { LSIState *s = opaque; @@ -1750,14 +1750,14 @@ static void lsi_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff); } -static uint32_t lsi_mmio_readb(void *opaque, target_phys_addr_t addr) +static uint32_t lsi_mmio_readb(void *opaque, a_target_phys_addr addr) { LSIState *s = opaque; return lsi_reg_readb(s, addr & 0xff); } -static uint32_t lsi_mmio_readw(void *opaque, target_phys_addr_t addr) +static uint32_t lsi_mmio_readw(void *opaque, a_target_phys_addr addr) { LSIState *s = opaque; uint32_t val; @@ -1768,7 +1768,7 @@ static uint32_t lsi_mmio_readw(void *opaque, target_phys_addr_t addr) return val; } -static uint32_t lsi_mmio_readl(void *opaque, target_phys_addr_t addr) +static uint32_t lsi_mmio_readl(void *opaque, a_target_phys_addr addr) { LSIState *s = opaque; uint32_t val; @@ -1792,7 +1792,7 @@ static CPUWriteMemoryFunc * const lsi_mmio_writefn[3] = { lsi_mmio_writel, }; -static void lsi_ram_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) +static void lsi_ram_writeb(void *opaque, a_target_phys_addr addr, uint32_t val) { LSIState *s = opaque; uint32_t newval; @@ -1806,7 +1806,7 @@ static void lsi_ram_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) s->script_ram[addr >> 2] = newval; } -static void lsi_ram_writew(void *opaque, target_phys_addr_t addr, uint32_t val) +static void lsi_ram_writew(void *opaque, a_target_phys_addr addr, uint32_t val) { LSIState *s = opaque; uint32_t newval; @@ -1822,7 +1822,7 @@ static void lsi_ram_writew(void *opaque, target_phys_addr_t addr, uint32_t val) } -static void lsi_ram_writel(void *opaque, target_phys_addr_t addr, uint32_t val) +static void lsi_ram_writel(void *opaque, a_target_phys_addr addr, uint32_t val) { LSIState *s = opaque; @@ -1830,7 +1830,7 @@ static void lsi_ram_writel(void *opaque, target_phys_addr_t addr, uint32_t val) s->script_ram[addr >> 2] = val; } -static uint32_t lsi_ram_readb(void *opaque, target_phys_addr_t addr) +static uint32_t lsi_ram_readb(void *opaque, a_target_phys_addr addr) { LSIState *s = opaque; uint32_t val; @@ -1841,7 +1841,7 @@ static uint32_t lsi_ram_readb(void *opaque, target_phys_addr_t addr) return val & 0xff; } -static uint32_t lsi_ram_readw(void *opaque, target_phys_addr_t addr) +static uint32_t lsi_ram_readw(void *opaque, a_target_phys_addr addr) { LSIState *s = opaque; uint32_t val; @@ -1853,7 +1853,7 @@ static uint32_t lsi_ram_readw(void *opaque, target_phys_addr_t addr) return le16_to_cpu(val); } -static uint32_t lsi_ram_readl(void *opaque, target_phys_addr_t addr) +static uint32_t lsi_ram_readl(void *opaque, a_target_phys_addr addr) { LSIState *s = opaque; diff --git a/hw/m48t59.c b/hw/m48t59.c index b9892cc1f8..b8ad5b8a09 100644 --- a/hw/m48t59.c +++ b/hw/m48t59.c @@ -41,7 +41,7 @@ * alarm and a watchdog timer and related control registers. In the * PPC platform there is also a nvram lock function. */ -struct m48t59_t { +struct m48t59 { /* Model parameters */ uint32_t type; // 2 = m48t02, 8 = m48t08, 59 = m48t59 /* Hardware parameters */ @@ -63,12 +63,12 @@ struct m48t59_t { typedef struct M48t59ISAState { ISADevice busdev; - m48t59_t state; + a_m48t59 state; } M48t59ISAState; typedef struct M48t59SysBusState { SysBusDevice busdev; - m48t59_t state; + a_m48t59 state; } M48t59SysBusState; /* Fake timer functions */ @@ -88,7 +88,7 @@ static void alarm_cb (void *opaque) { struct tm tm; uint64_t next_time; - m48t59_t *NVRAM = opaque; + a_m48t59 *NVRAM = opaque; qemu_set_irq(NVRAM->IRQ, 1); if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 && @@ -130,7 +130,7 @@ static void alarm_cb (void *opaque) qemu_set_irq(NVRAM->IRQ, 0); } -static void set_alarm (m48t59_t *NVRAM) +static void set_alarm (a_m48t59 *NVRAM) { int diff; if (NVRAM->alrm_timer != NULL) { @@ -142,12 +142,12 @@ static void set_alarm (m48t59_t *NVRAM) } /* RTC management helpers */ -static inline void get_time (m48t59_t *NVRAM, struct tm *tm) +static inline void get_time (a_m48t59 *NVRAM, struct tm *tm) { qemu_get_timedate(tm, NVRAM->time_offset); } -static void set_time (m48t59_t *NVRAM, struct tm *tm) +static void set_time (a_m48t59 *NVRAM, struct tm *tm) { NVRAM->time_offset = qemu_timedate_diff(tm); set_alarm(NVRAM); @@ -156,7 +156,7 @@ static void set_time (m48t59_t *NVRAM, struct tm *tm) /* Watchdog management */ static void watchdog_cb (void *opaque) { - m48t59_t *NVRAM = opaque; + a_m48t59 *NVRAM = opaque; NVRAM->buffer[0x1FF0] |= 0x80; if (NVRAM->buffer[0x1FF7] & 0x80) { @@ -170,7 +170,7 @@ static void watchdog_cb (void *opaque) } } -static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value) +static void set_up_watchdog (a_m48t59 *NVRAM, uint8_t value) { uint64_t interval; /* in 1/16 seconds */ @@ -188,7 +188,7 @@ static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value) /* Direct access to NVRAM */ void m48t59_write (void *opaque, uint32_t addr, uint32_t val) { - m48t59_t *NVRAM = opaque; + a_m48t59 *NVRAM = opaque; struct tm tm; int tmp; @@ -356,7 +356,7 @@ void m48t59_write (void *opaque, uint32_t addr, uint32_t val) uint32_t m48t59_read (void *opaque, uint32_t addr) { - m48t59_t *NVRAM = opaque; + a_m48t59 *NVRAM = opaque; struct tm tm; uint32_t retval = 0xFF; @@ -463,14 +463,14 @@ uint32_t m48t59_read (void *opaque, uint32_t addr) void m48t59_set_addr (void *opaque, uint32_t addr) { - m48t59_t *NVRAM = opaque; + a_m48t59 *NVRAM = opaque; NVRAM->addr = addr; } void m48t59_toggle_lock (void *opaque, int lock) { - m48t59_t *NVRAM = opaque; + a_m48t59 *NVRAM = opaque; NVRAM->lock ^= 1 << lock; } @@ -478,7 +478,7 @@ void m48t59_toggle_lock (void *opaque, int lock) /* IO access to NVRAM */ static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val) { - m48t59_t *NVRAM = opaque; + a_m48t59 *NVRAM = opaque; addr -= NVRAM->io_base; NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val); @@ -502,7 +502,7 @@ static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val) static uint32_t NVRAM_readb (void *opaque, uint32_t addr) { - m48t59_t *NVRAM = opaque; + a_m48t59 *NVRAM = opaque; uint32_t retval; addr -= NVRAM->io_base; @@ -519,24 +519,24 @@ static uint32_t NVRAM_readb (void *opaque, uint32_t addr) return retval; } -static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) +static void nvram_writeb (void *opaque, a_target_phys_addr addr, uint32_t value) { - m48t59_t *NVRAM = opaque; + a_m48t59 *NVRAM = opaque; m48t59_write(NVRAM, addr, value & 0xff); } -static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value) +static void nvram_writew (void *opaque, a_target_phys_addr addr, uint32_t value) { - m48t59_t *NVRAM = opaque; + a_m48t59 *NVRAM = opaque; m48t59_write(NVRAM, addr, (value >> 8) & 0xff); m48t59_write(NVRAM, addr + 1, value & 0xff); } -static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value) +static void nvram_writel (void *opaque, a_target_phys_addr addr, uint32_t value) { - m48t59_t *NVRAM = opaque; + a_m48t59 *NVRAM = opaque; m48t59_write(NVRAM, addr, (value >> 24) & 0xff); m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff); @@ -544,18 +544,18 @@ static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value) m48t59_write(NVRAM, addr + 3, value & 0xff); } -static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr) +static uint32_t nvram_readb (void *opaque, a_target_phys_addr addr) { - m48t59_t *NVRAM = opaque; + a_m48t59 *NVRAM = opaque; uint32_t retval; retval = m48t59_read(NVRAM, addr); return retval; } -static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr) +static uint32_t nvram_readw (void *opaque, a_target_phys_addr addr) { - m48t59_t *NVRAM = opaque; + a_m48t59 *NVRAM = opaque; uint32_t retval; retval = m48t59_read(NVRAM, addr) << 8; @@ -563,9 +563,9 @@ static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr) return retval; } -static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr) +static uint32_t nvram_readl (void *opaque, a_target_phys_addr addr) { - m48t59_t *NVRAM = opaque; + a_m48t59 *NVRAM = opaque; uint32_t retval; retval = m48t59_read(NVRAM, addr) << 24; @@ -589,7 +589,7 @@ static CPUReadMemoryFunc * const nvram_read[] = { static void m48t59_save(QEMUFile *f, void *opaque) { - m48t59_t *s = opaque; + a_m48t59 *s = opaque; qemu_put_8s(f, &s->lock); qemu_put_be16s(f, &s->addr); @@ -598,7 +598,7 @@ static void m48t59_save(QEMUFile *f, void *opaque) static int m48t59_load(QEMUFile *f, void *opaque, int version_id) { - m48t59_t *s = opaque; + a_m48t59 *s = opaque; if (version_id != 1) return -EINVAL; @@ -612,7 +612,7 @@ static int m48t59_load(QEMUFile *f, void *opaque, int version_id) static void m48t59_reset(void *opaque) { - m48t59_t *NVRAM = opaque; + a_m48t59 *NVRAM = opaque; NVRAM->addr = 0; NVRAM->lock = 0; @@ -624,7 +624,7 @@ static void m48t59_reset(void *opaque) } /* Initialisation routine */ -m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base, +a_m48t59 *m48t59_init (qemu_irq IRQ, a_target_phys_addr mem_base, uint32_t io_base, uint16_t size, int type) { @@ -652,11 +652,11 @@ m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base, return &d->state; } -m48t59_t *m48t59_init_isa(uint32_t io_base, uint16_t size, int type) +a_m48t59 *m48t59_init_isa(uint32_t io_base, uint16_t size, int type) { M48t59ISAState *d; ISADevice *dev; - m48t59_t *s; + a_m48t59 *s; dev = isa_create("m48t59_isa"); qdev_prop_set_uint32(&dev->qdev, "type", type); @@ -674,7 +674,7 @@ m48t59_t *m48t59_init_isa(uint32_t io_base, uint16_t size, int type) return s; } -static void m48t59_init_common(m48t59_t *s) +static void m48t59_init_common(a_m48t59 *s) { s->buffer = qemu_mallocz(s->size); if (s->type == 59) { @@ -690,7 +690,7 @@ static void m48t59_init_common(m48t59_t *s) static int m48t59_init_isa1(ISADevice *dev) { M48t59ISAState *d = DO_UPCAST(M48t59ISAState, busdev, dev); - m48t59_t *s = &d->state; + a_m48t59 *s = &d->state; isa_init_irq(dev, &s->IRQ, 8); m48t59_init_common(s); @@ -701,7 +701,7 @@ static int m48t59_init_isa1(ISADevice *dev) static int m48t59_init1(SysBusDevice *dev) { M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev); - m48t59_t *s = &d->state; + a_m48t59 *s = &d->state; int mem_index; sysbus_init_irq(dev, &s->IRQ); diff --git a/hw/mac_dbdma.c b/hw/mac_dbdma.c index c88ba2b8da..f44b90b33e 100644 --- a/hw/mac_dbdma.c +++ b/hw/mac_dbdma.c @@ -693,7 +693,7 @@ dbdma_control_write(DBDMA_channel *ch) } static void dbdma_writel (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { int channel = addr >> DBDMA_CHANNEL_SHIFT; DBDMA_channel *ch = (DBDMA_channel *)opaque + channel; @@ -741,7 +741,7 @@ static void dbdma_writel (void *opaque, } } -static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr) +static uint32_t dbdma_readl (void *opaque, a_target_phys_addr addr) { uint32_t value; int channel = addr >> DBDMA_CHANNEL_SHIFT; diff --git a/hw/mac_dbdma.h b/hw/mac_dbdma.h index d236c5b3f2..c8c82af2d3 100644 --- a/hw/mac_dbdma.h +++ b/hw/mac_dbdma.h @@ -28,7 +28,7 @@ typedef void (*DBDMA_end)(DBDMA_io *io); struct DBDMA_io { void *opaque; void *channel; - target_phys_addr_t addr; + a_target_phys_addr addr; int len; int is_last; int is_dma_out; diff --git a/hw/mac_nvram.c b/hw/mac_nvram.c index 0c91b3f1ba..60cc56ef38 100644 --- a/hw/mac_nvram.c +++ b/hw/mac_nvram.c @@ -38,7 +38,7 @@ #endif struct MacIONVRAMState { - target_phys_addr_t size; + a_target_phys_addr size; int mem_index; unsigned int it_shift; uint8_t *data; @@ -72,7 +72,7 @@ void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val) /* macio style NVRAM device */ static void macio_nvram_writeb (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { MacIONVRAMState *s = opaque; @@ -81,7 +81,7 @@ static void macio_nvram_writeb (void *opaque, NVR_DPRINTF("writeb addr %04x val %x\n", (int)addr, value); } -static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr) +static uint32_t macio_nvram_readb (void *opaque, a_target_phys_addr addr) { MacIONVRAMState *s = opaque; uint32_t value; @@ -128,7 +128,7 @@ static void macio_nvram_reset(void *opaque) { } -MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size, +MacIONVRAMState *macio_nvram_init (int *mem_index, a_target_phys_addr size, unsigned int it_shift) { MacIONVRAMState *s; @@ -148,7 +148,7 @@ MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size, return s; } -void macio_nvram_map (void *opaque, target_phys_addr_t mem_base) +void macio_nvram_map (void *opaque, a_target_phys_addr mem_base) { MacIONVRAMState *s; diff --git a/hw/macio.c b/hw/macio.c index 8cfadfc5e0..52d05d8e79 100644 --- a/hw/macio.c +++ b/hw/macio.c @@ -27,8 +27,8 @@ #include "pci.h" #include "escc.h" -typedef struct macio_state_t macio_state_t; -struct macio_state_t { +typedef struct macio_state a_macio_state; +struct macio_state { int is_oldworld; int pic_mem_index; int dbdma_mem_index; @@ -42,10 +42,10 @@ struct macio_state_t { static void macio_map (PCIDevice *pci_dev, int region_num, uint32_t addr, uint32_t size, int type) { - macio_state_t *macio_state; + a_macio_state *macio_state; int i; - macio_state = (macio_state_t *)(pci_dev + 1); + macio_state = (a_macio_state *)(pci_dev + 1); if (macio_state->pic_mem_index >= 0) { if (macio_state->is_oldworld) { /* Heathrow PIC */ @@ -84,13 +84,13 @@ void macio_init (PCIBus *bus, int device_id, int is_oldworld, int pic_mem_index, int nb_ide, int *ide_mem_index, int escc_mem_index) { PCIDevice *d; - macio_state_t *macio_state; + a_macio_state *macio_state; int i; d = pci_register_device(bus, "macio", - sizeof(PCIDevice) + sizeof(macio_state_t), + sizeof(PCIDevice) + sizeof(a_macio_state), -1, NULL, NULL); - macio_state = (macio_state_t *)(d + 1); + macio_state = (a_macio_state *)(d + 1); macio_state->is_oldworld = is_oldworld; macio_state->pic_mem_index = pic_mem_index; macio_state->dbdma_mem_index = dbdma_mem_index; diff --git a/hw/mainstone.c b/hw/mainstone.c index 3e517f0704..74d81021d9 100644 --- a/hw/mainstone.c +++ b/hw/mainstone.c @@ -68,13 +68,13 @@ static struct arm_boot_info mainstone_binfo = { .ram_size = 0x04000000, }; -static void mainstone_common_init(ram_addr_t ram_size, +static void mainstone_common_init(a_ram_addr ram_size, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model, enum mainstone_model_e model, int arm_id) { uint32_t sector_len = 256 * 1024; - target_phys_addr_t mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 }; + a_target_phys_addr mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 }; PXA2xxState *cpu; qemu_irq *mst_irq; DriveInfo *dinfo; @@ -127,7 +127,7 @@ static void mainstone_common_init(ram_addr_t ram_size, arm_load_kernel(cpu->env, &mainstone_binfo); } -static void mainstone_init(ram_addr_t ram_size, +static void mainstone_init(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) diff --git a/hw/marvell_88w8618_audio.c b/hw/marvell_88w8618_audio.c index 1c68da3c7b..a3777350e1 100644 --- a/hw/marvell_88w8618_audio.c +++ b/hw/marvell_88w8618_audio.c @@ -133,7 +133,7 @@ static void mv88w8618_audio_clock_update(mv88w8618_audio_state *s) wm8750_set_bclk_in(s->wm, rate); } -static uint32_t mv88w8618_audio_read(void *opaque, target_phys_addr_t offset) +static uint32_t mv88w8618_audio_read(void *opaque, a_target_phys_addr offset) { mv88w8618_audio_state *s = opaque; @@ -158,7 +158,7 @@ static uint32_t mv88w8618_audio_read(void *opaque, target_phys_addr_t offset) } } -static void mv88w8618_audio_write(void *opaque, target_phys_addr_t offset, +static void mv88w8618_audio_write(void *opaque, a_target_phys_addr offset, uint32_t value) { mv88w8618_audio_state *s = opaque; diff --git a/hw/mc146818rtc.c b/hw/mc146818rtc.c index 9d6a62751f..cef813eb1a 100644 --- a/hw/mc146818rtc.c +++ b/hw/mc146818rtc.c @@ -659,7 +659,7 @@ static void mc146818rtc_register(void) device_init(mc146818rtc_register) /* Memory mapped interface */ -static uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr) +static uint32_t cmos_mm_readb (void *opaque, a_target_phys_addr addr) { RTCState *s = opaque; @@ -667,14 +667,14 @@ static uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr) } static void cmos_mm_writeb (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { RTCState *s = opaque; cmos_ioport_write(s, addr >> s->it_shift, value & 0xFF); } -static uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr) +static uint32_t cmos_mm_readw (void *opaque, a_target_phys_addr addr) { RTCState *s = opaque; uint32_t val; @@ -687,7 +687,7 @@ static uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr) } static void cmos_mm_writew (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { RTCState *s = opaque; #ifdef TARGET_WORDS_BIGENDIAN @@ -696,7 +696,7 @@ static void cmos_mm_writew (void *opaque, cmos_ioport_write(s, addr >> s->it_shift, value & 0xFFFF); } -static uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr) +static uint32_t cmos_mm_readl (void *opaque, a_target_phys_addr addr) { RTCState *s = opaque; uint32_t val; @@ -709,7 +709,7 @@ static uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr) } static void cmos_mm_writel (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { RTCState *s = opaque; #ifdef TARGET_WORDS_BIGENDIAN @@ -730,7 +730,7 @@ static CPUWriteMemoryFunc * const rtc_mm_write[] = { &cmos_mm_writel, }; -RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, +RTCState *rtc_mm_init(a_target_phys_addr base, int it_shift, qemu_irq irq, int base_year) { RTCState *s; @@ -3,17 +3,17 @@ /* Motorola ColdFire device prototypes. */ /* mcf_uart.c */ -uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr); -void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val); +uint32_t mcf_uart_read(void *opaque, a_target_phys_addr addr); +void mcf_uart_write(void *opaque, a_target_phys_addr addr, uint32_t val); void *mcf_uart_init(qemu_irq irq, CharDriverState *chr); -void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq, +void mcf_uart_mm_init(a_target_phys_addr base, qemu_irq irq, CharDriverState *chr); /* mcf_intc.c */ -qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env); +qemu_irq *mcf_intc_init(a_target_phys_addr base, CPUState *env); /* mcf_fec.c */ -void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq); +void mcf_fec_init(NICInfo *nd, a_target_phys_addr base, qemu_irq *irq); /* mcf5206.c */ qemu_irq *mcf5206_init(uint32_t base, CPUState *env); diff --git a/hw/mcf5206.c b/hw/mcf5206.c index c107de8c61..b9930d87c8 100644 --- a/hw/mcf5206.c +++ b/hw/mcf5206.c @@ -367,10 +367,10 @@ static const int m5206_mbar_width[] = /* 1c0-200 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; -static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset); -static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset); +static uint32_t m5206_mbar_readw(void *opaque, a_target_phys_addr offset); +static uint32_t m5206_mbar_readl(void *opaque, a_target_phys_addr offset); -static uint32_t m5206_mbar_readb(void *opaque, target_phys_addr_t offset) +static uint32_t m5206_mbar_readb(void *opaque, a_target_phys_addr offset) { m5206_mbar_state *s = (m5206_mbar_state *)opaque; offset &= 0x3ff; @@ -388,7 +388,7 @@ static uint32_t m5206_mbar_readb(void *opaque, target_phys_addr_t offset) return m5206_mbar_read(s, offset); } -static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset) +static uint32_t m5206_mbar_readw(void *opaque, a_target_phys_addr offset) { m5206_mbar_state *s = (m5206_mbar_state *)opaque; int width; @@ -412,7 +412,7 @@ static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset) return m5206_mbar_read(s, offset); } -static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset) +static uint32_t m5206_mbar_readl(void *opaque, a_target_phys_addr offset) { m5206_mbar_state *s = (m5206_mbar_state *)opaque; int width; @@ -430,12 +430,12 @@ static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset) return m5206_mbar_read(s, offset); } -static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset, +static void m5206_mbar_writew(void *opaque, a_target_phys_addr offset, uint32_t value); -static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset, +static void m5206_mbar_writel(void *opaque, a_target_phys_addr offset, uint32_t value); -static void m5206_mbar_writeb(void *opaque, target_phys_addr_t offset, +static void m5206_mbar_writeb(void *opaque, a_target_phys_addr offset, uint32_t value) { m5206_mbar_state *s = (m5206_mbar_state *)opaque; @@ -459,7 +459,7 @@ static void m5206_mbar_writeb(void *opaque, target_phys_addr_t offset, m5206_mbar_write(s, offset, value); } -static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset, +static void m5206_mbar_writew(void *opaque, a_target_phys_addr offset, uint32_t value) { m5206_mbar_state *s = (m5206_mbar_state *)opaque; @@ -487,7 +487,7 @@ static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset, m5206_mbar_write(s, offset, value); } -static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset, +static void m5206_mbar_writel(void *opaque, a_target_phys_addr offset, uint32_t value) { m5206_mbar_state *s = (m5206_mbar_state *)opaque; diff --git a/hw/mcf5208.c b/hw/mcf5208.c index 5598611462..46bcfe75a6 100644 --- a/hw/mcf5208.c +++ b/hw/mcf5208.c @@ -42,7 +42,7 @@ static void m5208_timer_update(m5208_timer_state *s) qemu_irq_lower(s->irq); } -static void m5208_timer_write(void *opaque, target_phys_addr_t offset, +static void m5208_timer_write(void *opaque, a_target_phys_addr offset, uint32_t value) { m5208_timer_state *s = (m5208_timer_state *)opaque; @@ -104,7 +104,7 @@ static void m5208_timer_trigger(void *opaque) m5208_timer_update(s); } -static uint32_t m5208_timer_read(void *opaque, target_phys_addr_t addr) +static uint32_t m5208_timer_read(void *opaque, a_target_phys_addr addr) { m5208_timer_state *s = (m5208_timer_state *)opaque; switch (addr) { @@ -132,7 +132,7 @@ static CPUWriteMemoryFunc * const m5208_timer_writefn[] = { m5208_timer_write }; -static uint32_t m5208_sys_read(void *opaque, target_phys_addr_t addr) +static uint32_t m5208_sys_read(void *opaque, a_target_phys_addr addr) { switch (addr) { case 0x110: /* SDCS0 */ @@ -153,7 +153,7 @@ static uint32_t m5208_sys_read(void *opaque, target_phys_addr_t addr) } } -static void m5208_sys_write(void *opaque, target_phys_addr_t addr, +static void m5208_sys_write(void *opaque, a_target_phys_addr addr, uint32_t value) { hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr); @@ -195,7 +195,7 @@ static void mcf5208_sys_init(qemu_irq *pic) } } -static void mcf5208evb_init(ram_addr_t ram_size, +static void mcf5208evb_init(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -203,7 +203,7 @@ static void mcf5208evb_init(ram_addr_t ram_size, CPUState *env; int kernel_size; uint64_t elf_entry; - target_phys_addr_t entry; + a_target_phys_addr entry; qemu_irq *pic; if (!cpu_model) diff --git a/hw/mcf_fec.c b/hw/mcf_fec.c index f6d2bab12d..e21af42e3d 100644 --- a/hw/mcf_fec.c +++ b/hw/mcf_fec.c @@ -214,7 +214,7 @@ static void mcf_fec_reset(mcf_fec_state *s) s->rfsr = 0x500; } -static uint32_t mcf_fec_read(void *opaque, target_phys_addr_t addr) +static uint32_t mcf_fec_read(void *opaque, a_target_phys_addr addr) { mcf_fec_state *s = (mcf_fec_state *)opaque; switch (addr & 0x3ff) { @@ -251,7 +251,7 @@ static uint32_t mcf_fec_read(void *opaque, target_phys_addr_t addr) } } -static void mcf_fec_write(void *opaque, target_phys_addr_t addr, uint32_t value) +static void mcf_fec_write(void *opaque, a_target_phys_addr addr, uint32_t value) { mcf_fec_state *s = (mcf_fec_state *)opaque; switch (addr & 0x3ff) { @@ -450,7 +450,7 @@ static void mcf_fec_cleanup(VLANClientState *vc) qemu_free(s); } -void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq) +void mcf_fec_init(NICInfo *nd, a_target_phys_addr base, qemu_irq *irq) { mcf_fec_state *s; diff --git a/hw/mcf_intc.c b/hw/mcf_intc.c index f01bd320a4..35a42dc9b0 100644 --- a/hw/mcf_intc.c +++ b/hw/mcf_intc.c @@ -41,7 +41,7 @@ static void mcf_intc_update(mcf_intc_state *s) m68k_set_irq_level(s->env, best_level, s->active_vector); } -static uint32_t mcf_intc_read(void *opaque, target_phys_addr_t addr) +static uint32_t mcf_intc_read(void *opaque, a_target_phys_addr addr) { int offset; mcf_intc_state *s = (mcf_intc_state *)opaque; @@ -73,7 +73,7 @@ static uint32_t mcf_intc_read(void *opaque, target_phys_addr_t addr) } } -static void mcf_intc_write(void *opaque, target_phys_addr_t addr, uint32_t val) +static void mcf_intc_write(void *opaque, a_target_phys_addr addr, uint32_t val) { int offset; mcf_intc_state *s = (mcf_intc_state *)opaque; @@ -139,7 +139,7 @@ static CPUWriteMemoryFunc * const mcf_intc_writefn[] = { mcf_intc_write }; -qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env) +qemu_irq *mcf_intc_init(a_target_phys_addr base, CPUState *env) { mcf_intc_state *s; int iomemtype; diff --git a/hw/mcf_uart.c b/hw/mcf_uart.c index d16bac7337..68e6cf6a5d 100644 --- a/hw/mcf_uart.c +++ b/hw/mcf_uart.c @@ -64,7 +64,7 @@ static void mcf_uart_update(mcf_uart_state *s) qemu_set_irq(s->irq, (s->isr & s->imr) != 0); } -uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr) +uint32_t mcf_uart_read(void *opaque, a_target_phys_addr addr) { mcf_uart_state *s = (mcf_uart_state *)opaque; switch (addr & 0x3f) { @@ -182,7 +182,7 @@ static void mcf_do_command(mcf_uart_state *s, uint8_t cmd) } } -void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val) +void mcf_uart_write(void *opaque, a_target_phys_addr addr, uint32_t val) { mcf_uart_state *s = (mcf_uart_state *)opaque; switch (addr & 0x3f) { @@ -296,7 +296,7 @@ static CPUWriteMemoryFunc * const mcf_uart_writefn[] = { mcf_uart_write }; -void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq, +void mcf_uart_mm_init(a_target_phys_addr base, qemu_irq irq, CharDriverState *chr) { mcf_uart_state *s; @@ -6,19 +6,19 @@ PCIBus *pci_gt64120_init(qemu_irq *pic); /* ds1225y.c */ -void *ds1225y_init(target_phys_addr_t mem_base, const char *filename); +void *ds1225y_init(a_target_phys_addr mem_base, const char *filename); void ds1225y_set_protection(void *opaque, int protection); /* g364fb.c */ -int g364fb_mm_init(target_phys_addr_t vram_base, - target_phys_addr_t ctrl_base, int it_shift, +int g364fb_mm_init(a_target_phys_addr vram_base, + a_target_phys_addr ctrl_base, int it_shift, qemu_irq irq); /* mipsnet.c */ void mipsnet_init(int base, qemu_irq irq, NICInfo *nd); /* jazz_led.c */ -extern void jazz_led_init(target_phys_addr_t base); +extern void jazz_led_init(a_target_phys_addr base); /* mips_int.c */ extern void cpu_mips_irq_init_cpu(CPUState *env); @@ -28,7 +28,7 @@ extern void cpu_mips_clock_init(CPUState *); /* rc4030.c */ typedef struct rc4030DMAState *rc4030_dma; -void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write); +void rc4030_dma_memory_rw(void *opaque, a_target_phys_addr addr, uint8_t *buf, int len, int is_write); void rc4030_dma_read(void *dma, uint8_t *buf, int len); void rc4030_dma_write(void *dma, uint8_t *buf, int len); @@ -36,8 +36,8 @@ void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus, qemu_irq **irqs, rc4030_dma **dmas); /* dp8393x.c */ -void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift, +void dp83932_init(NICInfo *nd, a_target_phys_addr base, int it_shift, qemu_irq irq, void* mem_opaque, - void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write)); + void (*memory_rw)(void *opaque, a_target_phys_addr addr, uint8_t *buf, int len, int is_write)); #endif diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c index 2a70b8bec6..9d0f0ecc30 100644 --- a/hw/mips_jazz.c +++ b/hw/mips_jazz.c @@ -47,12 +47,12 @@ static void main_cpu_reset(void *opaque) cpu_reset(env); } -static uint32_t rtc_readb(void *opaque, target_phys_addr_t addr) +static uint32_t rtc_readb(void *opaque, a_target_phys_addr addr) { return cpu_inw(0x71); } -static void rtc_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) +static void rtc_writeb(void *opaque, a_target_phys_addr addr, uint32_t val) { cpu_outw(0x71, val & 0xff); } @@ -69,7 +69,7 @@ static CPUWriteMemoryFunc * const rtc_write[3] = { rtc_writeb, }; -static void dma_dummy_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) +static void dma_dummy_writeb(void *opaque, a_target_phys_addr addr, uint32_t val) { /* Nothing to do. That is only to ensure that * the current DMA acknowledge cycle is completed. */ @@ -113,7 +113,7 @@ static void audio_init(qemu_irq *pic) #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX) static -void mips_jazz_init (ram_addr_t ram_size, +void mips_jazz_init (a_ram_addr ram_size, const char *cpu_model, enum jazz_model_e jazz_model) { @@ -128,8 +128,8 @@ void mips_jazz_init (ram_addr_t ram_size, PITState *pit; BlockDriverState *fds[MAX_FD]; qemu_irq esp_reset; - ram_addr_t ram_offset; - ram_addr_t bios_offset; + a_ram_addr ram_offset; + a_ram_addr bios_offset; /* init CPUs */ if (cpu_model == NULL) { @@ -271,7 +271,7 @@ void mips_jazz_init (ram_addr_t ram_size, } static -void mips_magnum_init (ram_addr_t ram_size, +void mips_magnum_init (a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -280,7 +280,7 @@ void mips_magnum_init (ram_addr_t ram_size, } static -void mips_pica61_init (ram_addr_t ram_size, +void mips_pica61_init (a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) diff --git a/hw/mips_malta.c b/hw/mips_malta.c index e09e971b31..748c078970 100644 --- a/hw/mips_malta.c +++ b/hw/mips_malta.c @@ -117,7 +117,7 @@ static void malta_fpga_update_display(void *opaque) # define logout(fmt, ...) ((void)0) #endif -struct _eeprom24c0x_t { +struct eeprom24c0x { uint8_t tick; uint8_t address; uint8_t command; @@ -129,9 +129,9 @@ struct _eeprom24c0x_t { uint8_t contents[256]; }; -typedef struct _eeprom24c0x_t eeprom24c0x_t; +typedef struct eeprom24c0x a_eeprom24c0x; -static eeprom24c0x_t eeprom = { +static a_eeprom24c0x eeprom = { .contents = { /* 00000000: */ 0x80,0x08,0x04,0x0D,0x0A,0x01,0x40,0x00, /* 00000008: */ 0x01,0x75,0x54,0x00,0x82,0x08,0x00,0x01, @@ -217,7 +217,7 @@ static void eeprom24c0x_write(int scl, int sda) eeprom.sda = sda; } -static uint32_t malta_fpga_readl(void *opaque, target_phys_addr_t addr) +static uint32_t malta_fpga_readl(void *opaque, a_target_phys_addr addr) { MaltaFPGAState *s = opaque; uint32_t val = 0; @@ -304,7 +304,7 @@ static uint32_t malta_fpga_readl(void *opaque, target_phys_addr_t addr) return val; } -static void malta_fpga_writel(void *opaque, target_phys_addr_t addr, +static void malta_fpga_writel(void *opaque, a_target_phys_addr addr, uint32_t val) { MaltaFPGAState *s = opaque; @@ -431,7 +431,7 @@ static void malta_fpga_led_init(CharDriverState *chr) qemu_chr_printf(chr, "+--------+\r\n"); } -static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, qemu_irq uart_irq, CharDriverState *uart_chr) +static MaltaFPGAState *malta_fpga_init(a_target_phys_addr base, qemu_irq uart_irq, CharDriverState *uart_chr) { MaltaFPGAState *s; int malta; @@ -658,7 +658,7 @@ static void write_bootloader (CPUState *env, uint8_t *base, static void prom_set(int index, const char *string, ...) { char buf[ENVP_ENTRY_SIZE]; - target_phys_addr_t p; + a_target_phys_addr p; va_list ap; int32_t table_addr; @@ -688,7 +688,7 @@ static int64_t load_kernel (CPUState *env) int64_t kernel_entry, kernel_low, kernel_high; int index = 0; long initrd_size; - ram_addr_t initrd_offset; + a_ram_addr initrd_offset; int big_endian; #ifdef TARGET_WORDS_BIGENDIAN @@ -763,21 +763,21 @@ static void main_cpu_reset(void *opaque) } static -void mips_malta_init (ram_addr_t ram_size, +void mips_malta_init (a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { char *filename; - ram_addr_t ram_offset; - ram_addr_t bios_offset; + a_ram_addr ram_offset; + a_ram_addr bios_offset; target_long bios_size; int64_t kernel_entry; PCIBus *pci_bus; ISADevice *isa_dev; CPUState *env; RTCState *rtc_state; - fdctrl_t *floppy_controller; + a_fdctrl *floppy_controller; MaltaFPGAState *malta_fpga; qemu_irq *i8259; int piix4_devfn; diff --git a/hw/mips_mipssim.c b/hw/mips_mipssim.c index 9aed40e1bd..05751f1f51 100644 --- a/hw/mips_mipssim.c +++ b/hw/mips_mipssim.c @@ -55,7 +55,7 @@ static void load_kernel (CPUState *env) int64_t entry, kernel_low, kernel_high; long kernel_size; long initrd_size; - ram_addr_t initrd_offset; + a_ram_addr initrd_offset; int big_endian; #ifdef TARGET_WORDS_BIGENDIAN @@ -111,14 +111,14 @@ static void main_cpu_reset(void *opaque) } static void -mips_mipssim_init (ram_addr_t ram_size, +mips_mipssim_init (a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { char *filename; - ram_addr_t ram_offset; - ram_addr_t bios_offset; + a_ram_addr ram_offset; + a_ram_addr bios_offset; CPUState *env; int bios_size; diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c index b3abc61551..e10d5002dd 100644 --- a/hw/mips_r4k.c +++ b/hw/mips_r4k.c @@ -45,7 +45,7 @@ static struct _loaderparams { const char *initrd_filename; } loaderparams; -static void mips_qemu_writel (void *opaque, target_phys_addr_t addr, +static void mips_qemu_writel (void *opaque, a_target_phys_addr addr, uint32_t val) { if ((addr & 0xffff) == 0 && val == 42) @@ -54,7 +54,7 @@ static void mips_qemu_writel (void *opaque, target_phys_addr_t addr, qemu_system_shutdown_request (); } -static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr) +static uint32_t mips_qemu_readl (void *opaque, a_target_phys_addr addr) { return 0; } @@ -77,7 +77,7 @@ static void load_kernel (CPUState *env) { int64_t entry, kernel_low, kernel_high; long kernel_size, initrd_size; - ram_addr_t initrd_offset; + a_ram_addr initrd_offset; int ret; int big_endian; @@ -151,14 +151,14 @@ static void main_cpu_reset(void *opaque) static const int sector_len = 32 * 1024; static -void mips_r4k_init (ram_addr_t ram_size, +void mips_r4k_init (a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { char *filename; - ram_addr_t ram_offset; - ram_addr_t bios_offset; + a_ram_addr ram_offset; + a_ram_addr bios_offset; int bios_size; CPUState *env; RTCState *rtc_state; diff --git a/hw/mpcore.c b/hw/mpcore.c index 46c2b9d994..c8d307c579 100644 --- a/hw/mpcore.c +++ b/hw/mpcore.c @@ -155,7 +155,7 @@ static void mpcore_timer_init(mpcore_priv_state *mpcore, /* Per-CPU private memory mapped IO. */ -static uint32_t mpcore_priv_read(void *opaque, target_phys_addr_t offset) +static uint32_t mpcore_priv_read(void *opaque, a_target_phys_addr offset) { mpcore_priv_state *s = (mpcore_priv_state *)opaque; int id; @@ -199,7 +199,7 @@ bad_reg: return 0; } -static void mpcore_priv_write(void *opaque, target_phys_addr_t offset, +static void mpcore_priv_write(void *opaque, a_target_phys_addr offset, uint32_t value) { mpcore_priv_state *s = (mpcore_priv_state *)opaque; @@ -255,7 +255,7 @@ static CPUWriteMemoryFunc * const mpcore_priv_writefn[] = { mpcore_priv_write }; -static void mpcore_priv_map(SysBusDevice *dev, target_phys_addr_t base) +static void mpcore_priv_map(SysBusDevice *dev, a_target_phys_addr base) { mpcore_priv_state *s = FROM_SYSBUSGIC(mpcore_priv_state, dev); cpu_register_physical_memory(base, 0x1000, s->iomemtype); @@ -123,7 +123,7 @@ void msix_write_config(PCIDevice *dev, uint32_t addr, qemu_set_irq(dev->irq[0], 0); } -static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr) +static uint32_t msix_mmio_readl(void *opaque, a_target_phys_addr addr) { PCIDevice *dev = opaque; unsigned int offset = addr & (dev->msix_page_size - 1); @@ -135,7 +135,7 @@ static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr) return val; } -static uint32_t msix_mmio_read_unallowed(void *opaque, target_phys_addr_t addr) +static uint32_t msix_mmio_read_unallowed(void *opaque, a_target_phys_addr addr) { fprintf(stderr, "MSI-X: only dword read is allowed!\n"); return 0; @@ -172,7 +172,7 @@ static int msix_is_masked(PCIDevice *dev, int vector) return dev->msix_table_page[offset] & MSIX_VECTOR_MASK; } -static void msix_mmio_writel(void *opaque, target_phys_addr_t addr, +static void msix_mmio_writel(void *opaque, a_target_phys_addr addr, uint32_t val) { PCIDevice *dev = opaque; @@ -185,7 +185,7 @@ static void msix_mmio_writel(void *opaque, target_phys_addr_t addr, } } -static void msix_mmio_write_unallowed(void *opaque, target_phys_addr_t addr, +static void msix_mmio_write_unallowed(void *opaque, a_target_phys_addr addr, uint32_t val) { fprintf(stderr, "MSI-X: only dword write is allowed!\n"); @@ -221,7 +221,7 @@ void msix_mmio_map(PCIDevice *d, int region_num, /* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is * modified, it should be retrieved with msix_bar_size. */ int msix_init(struct PCIDevice *dev, unsigned short nentries, - unsigned bar_nr, unsigned bar_size, target_phys_addr_t page_size) + unsigned bar_nr, unsigned bar_size, a_target_phys_addr page_size) { int ret; /* Nothing to do if MSI is not supported by interrupt controller */ @@ -5,7 +5,7 @@ int msix_init(struct PCIDevice *dev, unsigned short nentries, unsigned bar_nr, unsigned bar_size, - target_phys_addr_t page_size); + a_target_phys_addr page_size); void msix_write_config(PCIDevice *pci_dev, uint32_t address, uint32_t val, int len); diff --git a/hw/mst_fpga.c b/hw/mst_fpga.c index 1b6cb77659..fc255b4eba 100644 --- a/hw/mst_fpga.c +++ b/hw/mst_fpga.c @@ -78,7 +78,7 @@ mst_fpga_set_irq(void *opaque, int irq, int level) static uint32_t -mst_fpga_readb(void *opaque, target_phys_addr_t addr) +mst_fpga_readb(void *opaque, a_target_phys_addr addr) { mst_irq_state *s = (mst_irq_state *) opaque; @@ -115,7 +115,7 @@ mst_fpga_readb(void *opaque, target_phys_addr_t addr) } static void -mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) +mst_fpga_writeb(void *opaque, a_target_phys_addr addr, uint32_t value) { mst_irq_state *s = (mst_irq_state *) opaque; value &= 0xffffffff; diff --git a/hw/musicpal.c b/hw/musicpal.c index 1c4f17cb90..230c7de96d 100644 --- a/hw/musicpal.c +++ b/hw/musicpal.c @@ -255,7 +255,7 @@ static void eth_send(mv88w8618_eth_state *s, int queue_index) } while (desc_addr != s->tx_queue[queue_index]); } -static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset) +static uint32_t mv88w8618_eth_read(void *opaque, a_target_phys_addr offset) { mv88w8618_eth_state *s = opaque; @@ -296,7 +296,7 @@ static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset) } } -static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset, +static void mv88w8618_eth_write(void *opaque, a_target_phys_addr offset, uint32_t value) { mv88w8618_eth_state *s = opaque; @@ -481,7 +481,7 @@ static void musicpal_lcd_gpio_brigthness_in(void *opaque, int irq, int level) s->brightness |= level << irq; } -static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset) +static uint32_t musicpal_lcd_read(void *opaque, a_target_phys_addr offset) { musicpal_lcd_state *s = opaque; @@ -494,7 +494,7 @@ static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset) } } -static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset, +static void musicpal_lcd_write(void *opaque, a_target_phys_addr offset, uint32_t value) { musicpal_lcd_state *s = opaque; @@ -594,7 +594,7 @@ static void mv88w8618_pic_set_irq(void *opaque, int irq, int level) mv88w8618_pic_update(s); } -static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset) +static uint32_t mv88w8618_pic_read(void *opaque, a_target_phys_addr offset) { mv88w8618_pic_state *s = opaque; @@ -607,7 +607,7 @@ static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset) } } -static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset, +static void mv88w8618_pic_write(void *opaque, a_target_phys_addr offset, uint32_t value) { mv88w8618_pic_state *s = opaque; @@ -705,7 +705,7 @@ static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s, s->ptimer = ptimer_init(bh); } -static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset) +static uint32_t mv88w8618_pit_read(void *opaque, a_target_phys_addr offset) { mv88w8618_pit_state *s = opaque; mv88w8618_timer_state *t; @@ -720,7 +720,7 @@ static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset) } } -static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset, +static void mv88w8618_pit_write(void *opaque, a_target_phys_addr offset, uint32_t value) { mv88w8618_pit_state *s = opaque; @@ -792,7 +792,7 @@ typedef struct mv88w8618_flashcfg_state { } mv88w8618_flashcfg_state; static uint32_t mv88w8618_flashcfg_read(void *opaque, - target_phys_addr_t offset) + a_target_phys_addr offset) { mv88w8618_flashcfg_state *s = opaque; @@ -805,7 +805,7 @@ static uint32_t mv88w8618_flashcfg_read(void *opaque, } } -static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset, +static void mv88w8618_flashcfg_write(void *opaque, a_target_phys_addr offset, uint32_t value) { mv88w8618_flashcfg_state *s = opaque; @@ -846,7 +846,7 @@ static int mv88w8618_flashcfg_init(SysBusDevice *dev) #define MP_BOARD_REVISION 0x31 -static uint32_t musicpal_misc_read(void *opaque, target_phys_addr_t offset) +static uint32_t musicpal_misc_read(void *opaque, a_target_phys_addr offset) { switch (offset) { case MP_MISC_BOARD_REVISION: @@ -857,7 +857,7 @@ static uint32_t musicpal_misc_read(void *opaque, target_phys_addr_t offset) } } -static void musicpal_misc_write(void *opaque, target_phys_addr_t offset, +static void musicpal_misc_write(void *opaque, a_target_phys_addr offset, uint32_t value) { } @@ -887,7 +887,7 @@ static void musicpal_misc_init(void) #define MP_WLAN_MAGIC1 0x11c #define MP_WLAN_MAGIC2 0x124 -static uint32_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset) +static uint32_t mv88w8618_wlan_read(void *opaque, a_target_phys_addr offset) { switch (offset) { /* Workaround to allow loading the binary-only wlandrv.ko crap @@ -902,7 +902,7 @@ static uint32_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset) } } -static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset, +static void mv88w8618_wlan_write(void *opaque, a_target_phys_addr offset, uint32_t value) { } @@ -1049,7 +1049,7 @@ static void musicpal_gpio_irq(void *opaque, int irq, int level) musicpal_gpio_keys_update(s); } -static uint32_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset) +static uint32_t musicpal_gpio_read(void *opaque, a_target_phys_addr offset) { musicpal_gpio_state *s = (musicpal_gpio_state *) opaque; @@ -1080,7 +1080,7 @@ static uint32_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset) } } -static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset, +static void musicpal_gpio_write(void *opaque, a_target_phys_addr offset, uint32_t value) { musicpal_gpio_state *s = (musicpal_gpio_state *) opaque; @@ -1275,7 +1275,7 @@ static struct arm_boot_info musicpal_binfo = { .board_id = 0x20e, }; -static void musicpal_init(ram_addr_t ram_size, +static void musicpal_init(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -1295,7 +1295,7 @@ static void musicpal_init(ram_addr_t ram_size, int i; unsigned long flash_size; DriveInfo *dinfo; - ram_addr_t sram_off; + a_ram_addr sram_off; if (!cpu_model) cpu_model = "arm926"; diff --git a/hw/nseries.c b/hw/nseries.c index 79f7387ffd..2b8e362da7 100644 --- a/hw/nseries.c +++ b/hw/nseries.c @@ -1094,7 +1094,7 @@ static struct omap_partition_info_s { { 0, 0, 0, NULL } }; -static bdaddr_t n8x0_bd_addr = {{ N8X0_BD_ADDR }}; +static a_bdaddr n8x0_bd_addr = {{ N8X0_BD_ADDR }}; static int n8x0_atag_setup(void *p, int model) { @@ -1265,7 +1265,7 @@ static int n810_atag_setup(struct arm_boot_info *info, void *p) return n8x0_atag_setup(p, 810); } -static void n8x0_init(ram_addr_t ram_size, const char *boot_device, +static void n8x0_init(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model, struct arm_boot_info *binfo, int model) @@ -1383,7 +1383,7 @@ static struct arm_boot_info n810_binfo = { .atag_board = n810_atag_setup, }; -static void n800_init(ram_addr_t ram_size, +static void n800_init(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -1393,7 +1393,7 @@ static void n800_init(ram_addr_t ram_size, cpu_model, &n800_binfo, 800); } -static void n810_init(ram_addr_t ram_size, +static void n810_init(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) diff --git a/hw/nvram.h b/hw/nvram.h index c63fd5f095..180de88550 100644 --- a/hw/nvram.h +++ b/hw/nvram.h @@ -2,26 +2,26 @@ #define NVRAM_H /* NVRAM helpers */ -typedef uint32_t (*nvram_read_t)(void *private, uint32_t addr); -typedef void (*nvram_write_t)(void *private, uint32_t addr, uint32_t val); -typedef struct nvram_t { +typedef uint32_t (*a_nvram_read)(void *private, uint32_t addr); +typedef void (*a_nvram_write)(void *private, uint32_t addr, uint32_t val); +typedef struct nvram { void *opaque; - nvram_read_t read_fn; - nvram_write_t write_fn; -} nvram_t; + a_nvram_read read_fn; + a_nvram_write write_fn; +} a_nvram; -void NVRAM_set_byte (nvram_t *nvram, uint32_t addr, uint8_t value); -uint8_t NVRAM_get_byte (nvram_t *nvram, uint32_t addr); -void NVRAM_set_word (nvram_t *nvram, uint32_t addr, uint16_t value); -uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr); -void NVRAM_set_lword (nvram_t *nvram, uint32_t addr, uint32_t value); -uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr); -void NVRAM_set_string (nvram_t *nvram, uint32_t addr, +void NVRAM_set_byte (a_nvram *nvram, uint32_t addr, uint8_t value); +uint8_t NVRAM_get_byte (a_nvram *nvram, uint32_t addr); +void NVRAM_set_word (a_nvram *nvram, uint32_t addr, uint16_t value); +uint16_t NVRAM_get_word (a_nvram *nvram, uint32_t addr); +void NVRAM_set_lword (a_nvram *nvram, uint32_t addr, uint32_t value); +uint32_t NVRAM_get_lword (a_nvram *nvram, uint32_t addr); +void NVRAM_set_string (a_nvram *nvram, uint32_t addr, const char *str, uint32_t max); -int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max); -void NVRAM_set_crc (nvram_t *nvram, uint32_t addr, +int NVRAM_get_string (a_nvram *nvram, uint8_t *dst, uint16_t addr, int max); +void NVRAM_set_crc (a_nvram *nvram, uint32_t addr, uint32_t start, uint32_t count); -int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size, +int PPC_NVRAM_set_params (a_nvram *nvram, uint16_t NVRAM_size, const char *arch, uint32_t RAM_size, int boot_device, uint32_t kernel_image, uint32_t kernel_size, @@ -29,13 +29,13 @@ int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size, uint32_t initrd_image, uint32_t initrd_size, uint32_t NVRAM_image, int width, int height, int depth); -typedef struct m48t59_t m48t59_t; +typedef struct m48t59 a_m48t59; void m48t59_write (void *private, uint32_t addr, uint32_t val); uint32_t m48t59_read (void *private, uint32_t addr); void m48t59_toggle_lock (void *private, int lock); -m48t59_t *m48t59_init_isa(uint32_t io_base, uint16_t size, int type); -m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base, +a_m48t59 *m48t59_init_isa(uint32_t io_base, uint16_t size, int type); +a_m48t59 *m48t59_init (qemu_irq IRQ, a_target_phys_addr mem_base, uint32_t io_base, uint16_t size, int type); void m48t59_set_addr (void *opaque, uint32_t addr); @@ -63,19 +63,19 @@ void omap_clk_reparent(omap_clk clk, omap_clk parent); /* omap[123].c */ struct omap_l4_s; -struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num); +struct omap_l4_s *omap_l4_init(a_target_phys_addr base, int ta_num); struct omap_target_agent_s; struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs); -target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region, +a_target_phys_addr omap_l4_attach(struct omap_target_agent_s *ta, int region, int iotype); # define l4_register_io_memory cpu_register_io_memory struct omap_intr_handler_s; -struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base, +struct omap_intr_handler_s *omap_inth_init(a_target_phys_addr base, unsigned long size, unsigned char nbanks, qemu_irq **pins, qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk); -struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base, +struct omap_intr_handler_s *omap2_inth_init(a_target_phys_addr base, int size, int nbanks, qemu_irq **pins, qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk fclk, omap_clk iclk); @@ -91,12 +91,12 @@ struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta, omap_clk iclk, struct omap_mpu_state_s *mpu); struct omap_sdrc_s; -struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base); +struct omap_sdrc_s *omap_sdrc_init(a_target_phys_addr base); struct omap_gpmc_s; -struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq); +struct omap_gpmc_s *omap_gpmc_init(a_target_phys_addr base, qemu_irq irq); void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype, - void (*base_upd)(void *opaque, target_phys_addr_t new), + void (*base_upd)(void *opaque, a_target_phys_addr new), void (*unmap)(void *opaque), void *opaque); /* @@ -416,10 +416,10 @@ enum omap_dma_model { }; struct soc_dma_s; -struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs, +struct soc_dma_s *omap_dma_init(a_target_phys_addr base, qemu_irq *irqs, qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk, enum omap_dma_model model); -struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs, +struct soc_dma_s *omap_dma4_init(a_target_phys_addr base, qemu_irq *irqs, struct omap_mpu_state_s *mpu, int fifo, int chans, omap_clk iclk, omap_clk fclk); void omap_dma_reset(struct soc_dma_s *s); @@ -445,15 +445,15 @@ typedef enum { post_incremented, single_index, double_index, -} omap_dma_addressing_t; +} e_omap_dma_addressing; /* Only used in OMAP DMA 3.x gigacells */ struct omap_dma_lcd_channel_s { enum omap_dma_port src; - target_phys_addr_t src_f1_top; - target_phys_addr_t src_f1_bottom; - target_phys_addr_t src_f2_top; - target_phys_addr_t src_f2_bottom; + a_target_phys_addr src_f1_top; + a_target_phys_addr src_f1_bottom; + a_target_phys_addr src_f2_top; + a_target_phys_addr src_f2_bottom; /* Used in OMAP DMA 3.2 gigacell */ unsigned char brust_f1; @@ -480,8 +480,8 @@ struct omap_dma_lcd_channel_s { uint16_t frames_f1; uint16_t elements_f2; uint16_t frames_f2; - omap_dma_addressing_t mode_f1; - omap_dma_addressing_t mode_f2; + e_omap_dma_addressing mode_f1; + e_omap_dma_addressing mode_f2; /* Destination port is fixed. */ int interrupts; @@ -489,7 +489,7 @@ struct omap_dma_lcd_channel_s { int dual; int current_frame; - target_phys_addr_t phys_framebuffer[2]; + a_target_phys_addr phys_framebuffer[2]; qemu_irq irq; struct omap_mpu_state_s *mpu; } *omap_dma_get_lcdch(struct soc_dma_s *s); @@ -628,7 +628,7 @@ struct omap_dma_lcd_channel_s { /* omap[123].c */ struct omap_mpu_timer_s; -struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base, +struct omap_mpu_timer_s *omap_mpu_timer_init(a_target_phys_addr base, qemu_irq irq, omap_clk clk); struct omap_gp_timer_s; @@ -636,22 +636,22 @@ struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta, qemu_irq irq, omap_clk fclk, omap_clk iclk); struct omap_watchdog_timer_s; -struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base, +struct omap_watchdog_timer_s *omap_wd_timer_init(a_target_phys_addr base, qemu_irq irq, omap_clk clk); struct omap_32khz_timer_s; -struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base, +struct omap_32khz_timer_s *omap_os_timer_init(a_target_phys_addr base, qemu_irq irq, omap_clk clk); void omap_synctimer_init(struct omap_target_agent_s *ta, struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk); struct omap_tipb_bridge_s; -struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base, +struct omap_tipb_bridge_s *omap_tipb_bridge_init(a_target_phys_addr base, qemu_irq abort_irq, omap_clk clk); struct omap_uart_s; -struct omap_uart_s *omap_uart_init(target_phys_addr_t base, +struct omap_uart_s *omap_uart_init(a_target_phys_addr base, qemu_irq irq, omap_clk fclk, omap_clk iclk, qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr); struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta, @@ -661,7 +661,7 @@ void omap_uart_reset(struct omap_uart_s *s); void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr); struct omap_mpuio_s; -struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base, +struct omap_mpuio_s *omap_mpuio_init(a_target_phys_addr base, qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup, omap_clk clk); qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s); @@ -669,7 +669,7 @@ void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler); void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down); struct omap_gpio_s; -struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base, +struct omap_gpio_s *omap_gpio_init(a_target_phys_addr base, qemu_irq irq, omap_clk clk); qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s); void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler); @@ -686,7 +686,7 @@ struct uWireSlave { void *opaque; }; struct omap_uwire_s; -struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base, +struct omap_uwire_s *omap_uwire_init(a_target_phys_addr base, qemu_irq *irq, qemu_irq dma, omap_clk clk); void omap_uwire_attach(struct omap_uwire_s *s, uWireSlave *slave, int chipselect); @@ -699,7 +699,7 @@ void omap_mcspi_attach(struct omap_mcspi_s *s, int chipselect); struct omap_rtc_s; -struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base, +struct omap_rtc_s *omap_rtc_init(a_target_phys_addr base, qemu_irq *irq, omap_clk clk); struct I2SCodec { @@ -727,12 +727,12 @@ struct I2SCodec { } in, out; }; struct omap_mcbsp_s; -struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base, +struct omap_mcbsp_s *omap_mcbsp_init(a_target_phys_addr base, qemu_irq *irq, qemu_irq *dma, omap_clk clk); void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave); struct omap_lpg_s; -struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk); +struct omap_lpg_s *omap_lpg_init(a_target_phys_addr base, omap_clk clk); void omap_tap_init(struct omap_target_agent_s *ta, struct omap_mpu_state_s *mpu); @@ -744,9 +744,9 @@ struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta, /* omap_lcdc.c */ struct omap_lcd_panel_s; void omap_lcdc_reset(struct omap_lcd_panel_s *s); -struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq, +struct omap_lcd_panel_s *omap_lcdc_init(a_target_phys_addr base, qemu_irq irq, struct omap_dma_lcd_channel_s *dma, - ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk); + a_ram_addr imif_base, a_ram_addr emiff_base, omap_clk clk); /* omap_dss.c */ struct rfbi_chip_s { @@ -758,7 +758,7 @@ struct rfbi_chip_s { struct omap_dss_s; void omap_dss_reset(struct omap_dss_s *s); struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta, - target_phys_addr_t l3_base, + a_target_phys_addr l3_base, qemu_irq irq, qemu_irq drq, omap_clk fck1, omap_clk fck2, omap_clk ck54m, omap_clk ick1, omap_clk ick2); @@ -766,7 +766,7 @@ void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip); /* omap_mmc.c */ struct omap_mmc_s; -struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base, +struct omap_mmc_s *omap_mmc_init(a_target_phys_addr base, BlockDriverState *bd, qemu_irq irq, qemu_irq dma[], omap_clk clk); struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta, @@ -778,7 +778,7 @@ void omap_mmc_enable(struct omap_mmc_s *s, int enable); /* omap_i2c.c */ struct omap_i2c_s; -struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base, +struct omap_i2c_s *omap_i2c_init(a_target_phys_addr base, qemu_irq irq, qemu_irq *dma, omap_clk clk); struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta, qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk); @@ -829,11 +829,11 @@ struct omap_mpu_state_s { struct omap_dma_port_if_s { uint32_t (*read[3])(struct omap_mpu_state_s *s, - target_phys_addr_t offset); + a_target_phys_addr offset); void (*write[3])(struct omap_mpu_state_s *s, - target_phys_addr_t offset, uint32_t value); + a_target_phys_addr offset, uint32_t value); int (*addr_valid)(struct omap_mpu_state_s *s, - target_phys_addr_t addr); + a_target_phys_addr addr); } port[__omap_dma_port_last]; unsigned long sdram_size; @@ -969,14 +969,14 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size, # error TARGET_PHYS_ADDR_BITS undefined # endif -uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr); -void omap_badwidth_write8(void *opaque, target_phys_addr_t addr, +uint32_t omap_badwidth_read8(void *opaque, a_target_phys_addr addr); +void omap_badwidth_write8(void *opaque, a_target_phys_addr addr, uint32_t value); -uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr); -void omap_badwidth_write16(void *opaque, target_phys_addr_t addr, +uint32_t omap_badwidth_read16(void *opaque, a_target_phys_addr addr); +void omap_badwidth_write16(void *opaque, a_target_phys_addr addr, uint32_t value); -uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr); -void omap_badwidth_write32(void *opaque, target_phys_addr_t addr, +uint32_t omap_badwidth_read32(void *opaque, a_target_phys_addr addr); +void omap_badwidth_write32(void *opaque, a_target_phys_addr addr, uint32_t value); void omap_mpu_wakeup(void *opaque, int irq, int req); @@ -1045,7 +1045,7 @@ struct io_fn { int in; }; -static uint32_t io_readb(void *opaque, target_phys_addr_t addr) +static uint32_t io_readb(void *opaque, a_target_phys_addr addr) { struct io_fn *s = opaque; uint32_t ret; @@ -1057,7 +1057,7 @@ static uint32_t io_readb(void *opaque, target_phys_addr_t addr) fprintf(stderr, "%08x ---> %02x\n", (uint32_t) addr, ret); return ret; } -static uint32_t io_readh(void *opaque, target_phys_addr_t addr) +static uint32_t io_readh(void *opaque, a_target_phys_addr addr) { struct io_fn *s = opaque; uint32_t ret; @@ -1069,7 +1069,7 @@ static uint32_t io_readh(void *opaque, target_phys_addr_t addr) fprintf(stderr, "%08x ---> %04x\n", (uint32_t) addr, ret); return ret; } -static uint32_t io_readw(void *opaque, target_phys_addr_t addr) +static uint32_t io_readw(void *opaque, a_target_phys_addr addr) { struct io_fn *s = opaque; uint32_t ret; @@ -1081,7 +1081,7 @@ static uint32_t io_readw(void *opaque, target_phys_addr_t addr) fprintf(stderr, "%08x ---> %08x\n", (uint32_t) addr, ret); return ret; } -static void io_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) +static void io_writeb(void *opaque, a_target_phys_addr addr, uint32_t value) { struct io_fn *s = opaque; @@ -1091,7 +1091,7 @@ static void io_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) s->mem_write[0](s->opaque, addr, value); s->in --; } -static void io_writeh(void *opaque, target_phys_addr_t addr, uint32_t value) +static void io_writeh(void *opaque, a_target_phys_addr addr, uint32_t value) { struct io_fn *s = opaque; @@ -1101,7 +1101,7 @@ static void io_writeh(void *opaque, target_phys_addr_t addr, uint32_t value) s->mem_write[1](s->opaque, addr, value); s->in --; } -static void io_writew(void *opaque, target_phys_addr_t addr, uint32_t value) +static void io_writew(void *opaque, a_target_phys_addr addr, uint32_t value) { struct io_fn *s = opaque; diff --git a/hw/omap1.c b/hw/omap1.c index e9676ecc88..79c976879e 100644 --- a/hw/omap1.c +++ b/hw/omap1.c @@ -27,7 +27,7 @@ #include "pc.h" /* Should signal the TCMI/GPMC */ -uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr) +uint32_t omap_badwidth_read8(void *opaque, a_target_phys_addr addr) { uint8_t ret; @@ -36,7 +36,7 @@ uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr) return ret; } -void omap_badwidth_write8(void *opaque, target_phys_addr_t addr, +void omap_badwidth_write8(void *opaque, a_target_phys_addr addr, uint32_t value) { uint8_t val8 = value; @@ -45,7 +45,7 @@ void omap_badwidth_write8(void *opaque, target_phys_addr_t addr, cpu_physical_memory_write(addr, (void *) &val8, 1); } -uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr) +uint32_t omap_badwidth_read16(void *opaque, a_target_phys_addr addr) { uint16_t ret; @@ -54,7 +54,7 @@ uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr) return ret; } -void omap_badwidth_write16(void *opaque, target_phys_addr_t addr, +void omap_badwidth_write16(void *opaque, a_target_phys_addr addr, uint32_t value) { uint16_t val16 = value; @@ -63,7 +63,7 @@ void omap_badwidth_write16(void *opaque, target_phys_addr_t addr, cpu_physical_memory_write(addr, (void *) &val16, 2); } -uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr) +uint32_t omap_badwidth_read32(void *opaque, a_target_phys_addr addr) { uint32_t ret; @@ -72,7 +72,7 @@ uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr) return ret; } -void omap_badwidth_write32(void *opaque, target_phys_addr_t addr, +void omap_badwidth_write32(void *opaque, a_target_phys_addr addr, uint32_t value) { OMAP_32B_REG(addr); @@ -196,7 +196,7 @@ static void omap_set_intr_noedge(void *opaque, int irq, int req) bank->irqs = (bank->inputs &= ~(1 << n)) | bank->swi; } -static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_inth_read(void *opaque, a_target_phys_addr addr) { struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; int i, offset = addr; @@ -273,7 +273,7 @@ static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_inth_write(void *opaque, target_phys_addr_t addr, +static void omap_inth_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; @@ -406,7 +406,7 @@ void omap_inth_reset(struct omap_intr_handler_s *s) qemu_set_irq(s->parent_intr[1], 0); } -struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base, +struct omap_intr_handler_s *omap_inth_init(a_target_phys_addr base, unsigned long size, unsigned char nbanks, qemu_irq **pins, qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk) { @@ -431,7 +431,7 @@ struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base, return s; } -static uint32_t omap2_inth_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap2_inth_read(void *opaque, a_target_phys_addr addr) { struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; int offset = addr; @@ -508,7 +508,7 @@ static uint32_t omap2_inth_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap2_inth_write(void *opaque, target_phys_addr_t addr, +static void omap2_inth_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; @@ -624,7 +624,7 @@ static CPUWriteMemoryFunc * const omap2_inth_writefn[] = { omap2_inth_write, }; -struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base, +struct omap_intr_handler_s *omap2_inth_init(a_target_phys_addr base, int size, int nbanks, qemu_irq **pins, qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk fclk, omap_clk iclk) @@ -748,7 +748,7 @@ static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer) timer->rate = omap_clk_getrate(timer->clk); } -static uint32_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_mpu_timer_read(void *opaque, a_target_phys_addr addr) { struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; @@ -767,7 +767,7 @@ static uint32_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr, +static void omap_mpu_timer_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; @@ -819,7 +819,7 @@ static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s) s->it_ena = 1; } -struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base, +struct omap_mpu_timer_s *omap_mpu_timer_init(a_target_phys_addr base, qemu_irq irq, omap_clk clk) { int iomemtype; @@ -849,7 +849,7 @@ struct omap_watchdog_timer_s { int reset; }; -static uint32_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_wd_timer_read(void *opaque, a_target_phys_addr addr) { struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; @@ -869,7 +869,7 @@ static uint32_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr, +static void omap_wd_timer_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; @@ -943,7 +943,7 @@ static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s) omap_timer_update(&s->timer); } -struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base, +struct omap_watchdog_timer_s *omap_wd_timer_init(a_target_phys_addr base, qemu_irq irq, omap_clk clk) { int iomemtype; @@ -968,7 +968,7 @@ struct omap_32khz_timer_s { struct omap_mpu_timer_s timer; }; -static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_os_timer_read(void *opaque, a_target_phys_addr addr) { struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; int offset = addr & OMAP_MPUI_REG_MASK; @@ -990,7 +990,7 @@ static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_os_timer_write(void *opaque, target_phys_addr_t addr, +static void omap_os_timer_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; @@ -1045,7 +1045,7 @@ static void omap_os_timer_reset(struct omap_32khz_timer_s *s) s->timer.ar = 1; } -struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base, +struct omap_32khz_timer_s *omap_os_timer_init(a_target_phys_addr base, qemu_irq irq, omap_clk clk) { int iomemtype; @@ -1066,7 +1066,7 @@ struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base, } /* Ultra Low-Power Device Module */ -static uint32_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_ulpd_pm_read(void *opaque, a_target_phys_addr addr) { struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; uint16_t ret; @@ -1128,7 +1128,7 @@ static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s, omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1); } -static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr, +static void omap_ulpd_pm_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; @@ -1282,7 +1282,7 @@ static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu) omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4")); } -static void omap_ulpd_pm_init(target_phys_addr_t base, +static void omap_ulpd_pm_init(a_target_phys_addr base, struct omap_mpu_state_s *mpu) { int iomemtype = cpu_register_io_memory(omap_ulpd_pm_readfn, @@ -1293,7 +1293,7 @@ static void omap_ulpd_pm_init(target_phys_addr_t base, } /* OMAP Pin Configuration */ -static uint32_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_pin_cfg_read(void *opaque, a_target_phys_addr addr) { struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; @@ -1395,7 +1395,7 @@ static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s, omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1); } -static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr, +static void omap_pin_cfg_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; @@ -1497,7 +1497,7 @@ static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu) memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl)); } -static void omap_pin_cfg_init(target_phys_addr_t base, +static void omap_pin_cfg_init(a_target_phys_addr base, struct omap_mpu_state_s *mpu) { int iomemtype = cpu_register_io_memory(omap_pin_cfg_readfn, @@ -1508,7 +1508,7 @@ static void omap_pin_cfg_init(target_phys_addr_t base, } /* Device Identification, Die Identification */ -static uint32_t omap_id_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_id_read(void *opaque, a_target_phys_addr addr) { struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; @@ -1550,7 +1550,7 @@ static uint32_t omap_id_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_id_write(void *opaque, target_phys_addr_t addr, +static void omap_id_write(void *opaque, a_target_phys_addr addr, uint32_t value) { OMAP_BAD_REG(addr); @@ -1579,7 +1579,7 @@ static void omap_id_init(struct omap_mpu_state_s *mpu) } /* MPUI Control (Dummy) */ -static uint32_t omap_mpui_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_mpui_read(void *opaque, a_target_phys_addr addr) { struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; @@ -1607,7 +1607,7 @@ static uint32_t omap_mpui_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_mpui_write(void *opaque, target_phys_addr_t addr, +static void omap_mpui_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; @@ -1650,7 +1650,7 @@ static void omap_mpui_reset(struct omap_mpu_state_s *s) s->mpui_ctrl = 0x0003ff1b; } -static void omap_mpui_init(target_phys_addr_t base, +static void omap_mpui_init(a_target_phys_addr base, struct omap_mpu_state_s *mpu) { int iomemtype = cpu_register_io_memory(omap_mpui_readfn, @@ -1672,7 +1672,7 @@ struct omap_tipb_bridge_s { uint16_t enh_control; }; -static uint32_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_tipb_bridge_read(void *opaque, a_target_phys_addr addr) { struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; @@ -1697,7 +1697,7 @@ static uint32_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr, +static void omap_tipb_bridge_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; @@ -1752,7 +1752,7 @@ static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s) s->enh_control = 0x000f; } -struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base, +struct omap_tipb_bridge_s *omap_tipb_bridge_init(a_target_phys_addr base, qemu_irq abort_irq, omap_clk clk) { int iomemtype; @@ -1770,7 +1770,7 @@ struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base, } /* Dummy Traffic Controller's Memory Interface */ -static uint32_t omap_tcmi_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_tcmi_read(void *opaque, a_target_phys_addr addr) { struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; uint32_t ret; @@ -1803,7 +1803,7 @@ static uint32_t omap_tcmi_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_tcmi_write(void *opaque, target_phys_addr_t addr, +static void omap_tcmi_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; @@ -1865,7 +1865,7 @@ static void omap_tcmi_reset(struct omap_mpu_state_s *mpu) mpu->tcmi_regs[0x40 >> 2] = 0x00000000; } -static void omap_tcmi_init(target_phys_addr_t base, +static void omap_tcmi_init(a_target_phys_addr base, struct omap_mpu_state_s *mpu) { int iomemtype = cpu_register_io_memory(omap_tcmi_readfn, @@ -1876,7 +1876,7 @@ static void omap_tcmi_init(target_phys_addr_t base, } /* Digital phase-locked loops control */ -static uint32_t omap_dpll_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_dpll_read(void *opaque, a_target_phys_addr addr) { struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; @@ -1887,7 +1887,7 @@ static uint32_t omap_dpll_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_dpll_write(void *opaque, target_phys_addr_t addr, +static void omap_dpll_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; @@ -1938,7 +1938,7 @@ static void omap_dpll_reset(struct dpll_ctl_s *s) omap_clk_setrate(s->dpll, 1, 1); } -static void omap_dpll_init(struct dpll_ctl_s *s, target_phys_addr_t base, +static void omap_dpll_init(struct dpll_ctl_s *s, a_target_phys_addr base, omap_clk clk) { int iomemtype = cpu_register_io_memory(omap_dpll_readfn, @@ -1952,7 +1952,7 @@ static void omap_dpll_init(struct dpll_ctl_s *s, target_phys_addr_t base, /* UARTs */ struct omap_uart_s { - target_phys_addr_t base; + a_target_phys_addr base; SerialState *serial; /* TODO */ struct omap_target_agent_s *ta; omap_clk fclk; @@ -1976,7 +1976,7 @@ void omap_uart_reset(struct omap_uart_s *s) s->clksel = 0; } -struct omap_uart_s *omap_uart_init(target_phys_addr_t base, +struct omap_uart_s *omap_uart_init(a_target_phys_addr base, qemu_irq irq, omap_clk fclk, omap_clk iclk, qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr) { @@ -1992,7 +1992,7 @@ struct omap_uart_s *omap_uart_init(target_phys_addr_t base, return s; } -static uint32_t omap_uart_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_uart_read(void *opaque, a_target_phys_addr addr) { struct omap_uart_s *s = (struct omap_uart_s *) opaque; @@ -2026,7 +2026,7 @@ static uint32_t omap_uart_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_uart_write(void *opaque, target_phys_addr_t addr, +static void omap_uart_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_uart_s *s = (struct omap_uart_s *) opaque; @@ -2085,7 +2085,7 @@ struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta, qemu_irq irq, omap_clk fclk, omap_clk iclk, qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr) { - target_phys_addr_t base = omap_l4_attach(ta, 0, 0); + a_target_phys_addr base = omap_l4_attach(ta, 0, 0); struct omap_uart_s *s = omap_uart_init(base, irq, fclk, iclk, txdma, rxdma, chr); int iomemtype = cpu_register_io_memory(omap_uart_readfn, @@ -2107,7 +2107,7 @@ void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr) } /* MPU Clock/Reset/Power Mode Control */ -static uint32_t omap_clkm_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_clkm_read(void *opaque, a_target_phys_addr addr) { struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; @@ -2303,7 +2303,7 @@ static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s, } } -static void omap_clkm_write(void *opaque, target_phys_addr_t addr, +static void omap_clkm_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; @@ -2393,7 +2393,7 @@ static CPUWriteMemoryFunc * const omap_clkm_writefn[] = { omap_badwidth_write16, }; -static uint32_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_clkdsp_read(void *opaque, a_target_phys_addr addr) { struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; @@ -2432,7 +2432,7 @@ static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s, SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */ } -static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr, +static void omap_clkdsp_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; @@ -2499,8 +2499,8 @@ static void omap_clkm_reset(struct omap_mpu_state_s *s) s->clkm.dsp_rstct2 = 0x0000; } -static void omap_clkm_init(target_phys_addr_t mpu_base, - target_phys_addr_t dsp_base, struct omap_mpu_state_s *s) +static void omap_clkm_init(a_target_phys_addr mpu_base, + a_target_phys_addr dsp_base, struct omap_mpu_state_s *s) { int iomemtype[2] = { cpu_register_io_memory(omap_clkm_readfn, omap_clkm_writefn, s), @@ -2578,7 +2578,7 @@ static void omap_mpuio_kbd_update(struct omap_mpuio_s *s) s->row_latch = ~rows; } -static uint32_t omap_mpuio_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_mpuio_read(void *opaque, a_target_phys_addr addr) { struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; int offset = addr & OMAP_MPUI_REG_MASK; @@ -2633,7 +2633,7 @@ static uint32_t omap_mpuio_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_mpuio_write(void *opaque, target_phys_addr_t addr, +static void omap_mpuio_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; @@ -2743,7 +2743,7 @@ static void omap_mpuio_onoff(void *opaque, int line, int on) omap_mpuio_kbd_update(s); } -struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base, +struct omap_mpuio_s *omap_mpuio_init(a_target_phys_addr base, qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup, omap_clk clk) { @@ -2823,7 +2823,7 @@ static void omap_gpio_set(void *opaque, int line, int level) } } -static uint32_t omap_gpio_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_gpio_read(void *opaque, a_target_phys_addr addr) { struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; int offset = addr & OMAP_MPUI_REG_MASK; @@ -2856,7 +2856,7 @@ static uint32_t omap_gpio_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_gpio_write(void *opaque, target_phys_addr_t addr, +static void omap_gpio_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; @@ -2942,7 +2942,7 @@ static void omap_gpio_reset(struct omap_gpio_s *s) s->pins = ~0; } -struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base, +struct omap_gpio_s *omap_gpio_init(a_target_phys_addr base, qemu_irq irq, omap_clk clk) { int iomemtype; @@ -3011,7 +3011,7 @@ static void omap_uwire_transfer_start(struct omap_uwire_s *s) } } -static uint32_t omap_uwire_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_uwire_read(void *opaque, a_target_phys_addr addr) { struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; int offset = addr & OMAP_MPUI_REG_MASK; @@ -3040,7 +3040,7 @@ static uint32_t omap_uwire_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_uwire_write(void *opaque, target_phys_addr_t addr, +static void omap_uwire_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; @@ -3111,7 +3111,7 @@ static void omap_uwire_reset(struct omap_uwire_s *s) s->setup[4] = 0; } -struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base, +struct omap_uwire_s *omap_uwire_init(a_target_phys_addr base, qemu_irq *irq, qemu_irq dma, omap_clk clk) { int iomemtype; @@ -3152,7 +3152,7 @@ static void omap_pwl_update(struct omap_mpu_state_s *s) } } -static uint32_t omap_pwl_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_pwl_read(void *opaque, a_target_phys_addr addr) { struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; int offset = addr & OMAP_MPUI_REG_MASK; @@ -3167,7 +3167,7 @@ static uint32_t omap_pwl_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_pwl_write(void *opaque, target_phys_addr_t addr, +static void omap_pwl_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; @@ -3217,7 +3217,7 @@ static void omap_pwl_clk_update(void *opaque, int line, int on) omap_pwl_update(s); } -static void omap_pwl_init(target_phys_addr_t base, struct omap_mpu_state_s *s, +static void omap_pwl_init(a_target_phys_addr base, struct omap_mpu_state_s *s, omap_clk clk) { int iomemtype; @@ -3232,7 +3232,7 @@ static void omap_pwl_init(target_phys_addr_t base, struct omap_mpu_state_s *s, } /* Pulse-Width Tone module */ -static uint32_t omap_pwt_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_pwt_read(void *opaque, a_target_phys_addr addr) { struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; int offset = addr & OMAP_MPUI_REG_MASK; @@ -3249,7 +3249,7 @@ static uint32_t omap_pwt_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_pwt_write(void *opaque, target_phys_addr_t addr, +static void omap_pwt_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; @@ -3311,7 +3311,7 @@ static void omap_pwt_reset(struct omap_mpu_state_s *s) s->pwt.gcr = 0; } -static void omap_pwt_init(target_phys_addr_t base, struct omap_mpu_state_s *s, +static void omap_pwt_init(a_target_phys_addr base, struct omap_mpu_state_s *s, omap_clk clk) { int iomemtype; @@ -3368,7 +3368,7 @@ static inline int omap_rtc_bin(uint8_t num) return (num & 15) + 10 * (num >> 4); } -static uint32_t omap_rtc_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_rtc_read(void *opaque, a_target_phys_addr addr) { struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; int offset = addr & OMAP_MPUI_REG_MASK; @@ -3445,7 +3445,7 @@ static uint32_t omap_rtc_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_rtc_write(void *opaque, target_phys_addr_t addr, +static void omap_rtc_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; @@ -3729,7 +3729,7 @@ static void omap_rtc_reset(struct omap_rtc_s *s) omap_rtc_tick(s); } -struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base, +struct omap_rtc_s *omap_rtc_init(a_target_phys_addr base, qemu_irq *irq, omap_clk clk) { int iomemtype; @@ -3956,7 +3956,7 @@ static void omap_mcbsp_req_update(struct omap_mcbsp_s *s) omap_mcbsp_rx_stop(s); } -static uint32_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_mcbsp_read(void *opaque, a_target_phys_addr addr) { struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; int offset = addr & OMAP_MPUI_REG_MASK; @@ -4049,7 +4049,7 @@ static uint32_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_mcbsp_writeh(void *opaque, target_phys_addr_t addr, +static void omap_mcbsp_writeh(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; @@ -4187,7 +4187,7 @@ static void omap_mcbsp_writeh(void *opaque, target_phys_addr_t addr, OMAP_BAD_REG(addr); } -static void omap_mcbsp_writew(void *opaque, target_phys_addr_t addr, +static void omap_mcbsp_writew(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; @@ -4249,7 +4249,7 @@ static void omap_mcbsp_reset(struct omap_mcbsp_s *s) qemu_del_timer(s->sink_timer); } -struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base, +struct omap_mcbsp_s *omap_mcbsp_init(a_target_phys_addr base, qemu_irq *irq, qemu_irq *dma, omap_clk clk) { int iomemtype; @@ -4364,7 +4364,7 @@ static void omap_lpg_reset(struct omap_lpg_s *s) omap_lpg_update(s); } -static uint32_t omap_lpg_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_lpg_read(void *opaque, a_target_phys_addr addr) { struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; int offset = addr & OMAP_MPUI_REG_MASK; @@ -4381,7 +4381,7 @@ static uint32_t omap_lpg_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_lpg_write(void *opaque, target_phys_addr_t addr, +static void omap_lpg_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; @@ -4426,7 +4426,7 @@ static void omap_lpg_clk_update(void *opaque, int line, int on) omap_lpg_update(s); } -struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk) +struct omap_lpg_s *omap_lpg_init(a_target_phys_addr base, omap_clk clk) { int iomemtype; struct omap_lpg_s *s = (struct omap_lpg_s *) @@ -4446,7 +4446,7 @@ struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk) } /* MPUI Peripheral Bridge configuration */ -static uint32_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_mpui_io_read(void *opaque, a_target_phys_addr addr) { if (addr == OMAP_MPUI_BASE) /* CMR */ return 0xfe4d; @@ -4517,8 +4517,8 @@ static void omap1_mpu_reset(void *opaque) } static const struct omap_map_s { - target_phys_addr_t phys_dsp; - target_phys_addr_t phys_mpu; + a_target_phys_addr phys_dsp; + a_target_phys_addr phys_mpu; uint32_t size; const char *name; } omap15xx_dsp_mm[] = { @@ -4586,37 +4586,37 @@ static const struct dma_irq_map omap1_dma_irq_map[] = { /* DMA ports for OMAP1 */ static int omap_validate_emiff_addr(struct omap_mpu_state_s *s, - target_phys_addr_t addr) + a_target_phys_addr addr) { return addr >= OMAP_EMIFF_BASE && addr < OMAP_EMIFF_BASE + s->sdram_size; } static int omap_validate_emifs_addr(struct omap_mpu_state_s *s, - target_phys_addr_t addr) + a_target_phys_addr addr) { return addr >= OMAP_EMIFS_BASE && addr < OMAP_EMIFF_BASE; } static int omap_validate_imif_addr(struct omap_mpu_state_s *s, - target_phys_addr_t addr) + a_target_phys_addr addr) { return addr >= OMAP_IMIF_BASE && addr < OMAP_IMIF_BASE + s->sram_size; } static int omap_validate_tipb_addr(struct omap_mpu_state_s *s, - target_phys_addr_t addr) + a_target_phys_addr addr) { return addr >= 0xfffb0000 && addr < 0xffff0000; } static int omap_validate_local_addr(struct omap_mpu_state_s *s, - target_phys_addr_t addr) + a_target_phys_addr addr) { return addr >= OMAP_LOCALBUS_BASE && addr < OMAP_LOCALBUS_BASE + 0x1000000; } static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s, - target_phys_addr_t addr) + a_target_phys_addr addr) { return addr >= 0xe1010000 && addr < 0xe1020004; } @@ -4627,7 +4627,7 @@ struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size, int i; struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) qemu_mallocz(sizeof(struct omap_mpu_state_s)); - ram_addr_t imif_base, emiff_base; + a_ram_addr imif_base, emiff_base; qemu_irq *cpu_irq; qemu_irq dma_irqs[6]; DriveInfo *dinfo; diff --git a/hw/omap2.c b/hw/omap2.c index a3fa89d3ee..700823c1ab 100644 --- a/hw/omap2.c +++ b/hw/omap2.c @@ -263,7 +263,7 @@ static void omap_gp_timer_reset(struct omap_gp_timer_s *s) omap_gp_timer_update(s); } -static uint32_t omap_gp_timer_readw(void *opaque, target_phys_addr_t addr) +static uint32_t omap_gp_timer_readw(void *opaque, a_target_phys_addr addr) { struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; @@ -329,7 +329,7 @@ static uint32_t omap_gp_timer_readw(void *opaque, target_phys_addr_t addr) return 0; } -static uint32_t omap_gp_timer_readh(void *opaque, target_phys_addr_t addr) +static uint32_t omap_gp_timer_readh(void *opaque, a_target_phys_addr addr) { struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; uint32_t ret; @@ -349,7 +349,7 @@ static CPUReadMemoryFunc * const omap_gp_timer_readfn[] = { omap_gp_timer_readw, }; -static void omap_gp_timer_write(void *opaque, target_phys_addr_t addr, +static void omap_gp_timer_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; @@ -449,7 +449,7 @@ static void omap_gp_timer_write(void *opaque, target_phys_addr_t addr, } } -static void omap_gp_timer_writeh(void *opaque, target_phys_addr_t addr, +static void omap_gp_timer_writeh(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; @@ -499,7 +499,7 @@ static void omap_synctimer_reset(struct omap_synctimer_s *s) s->val = omap_synctimer_read(s); } -static uint32_t omap_synctimer_readw(void *opaque, target_phys_addr_t addr) +static uint32_t omap_synctimer_readw(void *opaque, a_target_phys_addr addr) { struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque; @@ -515,7 +515,7 @@ static uint32_t omap_synctimer_readw(void *opaque, target_phys_addr_t addr) return 0; } -static uint32_t omap_synctimer_readh(void *opaque, target_phys_addr_t addr) +static uint32_t omap_synctimer_readh(void *opaque, a_target_phys_addr addr) { struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque; uint32_t ret; @@ -535,7 +535,7 @@ static CPUReadMemoryFunc * const omap_synctimer_readfn[] = { omap_synctimer_readw, }; -static void omap_synctimer_write(void *opaque, target_phys_addr_t addr, +static void omap_synctimer_write(void *opaque, a_target_phys_addr addr, uint32_t value) { OMAP_BAD_REG(addr); @@ -658,7 +658,7 @@ static void omap_gpio_module_reset(struct omap2_gpio_s *s) s->delay = 0; } -static uint32_t omap_gpio_module_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_gpio_module_read(void *opaque, a_target_phys_addr addr) { struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque; @@ -730,7 +730,7 @@ static uint32_t omap_gpio_module_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_gpio_module_write(void *opaque, target_phys_addr_t addr, +static void omap_gpio_module_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque; @@ -872,12 +872,12 @@ static void omap_gpio_module_write(void *opaque, target_phys_addr_t addr, } } -static uint32_t omap_gpio_module_readp(void *opaque, target_phys_addr_t addr) +static uint32_t omap_gpio_module_readp(void *opaque, a_target_phys_addr addr) { return omap_gpio_module_readp(opaque, addr) >> ((addr & 3) << 3); } -static void omap_gpio_module_writep(void *opaque, target_phys_addr_t addr, +static void omap_gpio_module_writep(void *opaque, a_target_phys_addr addr, uint32_t value) { uint32_t cur = 0; @@ -975,7 +975,7 @@ static void omap_gpif_reset(struct omap_gpif_s *s) s->gpo = 0; } -static uint32_t omap_gpif_top_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_gpif_top_read(void *opaque, a_target_phys_addr addr) { struct omap_gpif_s *s = (struct omap_gpif_s *) opaque; @@ -1003,7 +1003,7 @@ static uint32_t omap_gpif_top_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_gpif_top_write(void *opaque, target_phys_addr_t addr, +static void omap_gpif_top_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_gpif_s *s = (struct omap_gpif_s *) opaque; @@ -1187,7 +1187,7 @@ static void omap_mcspi_reset(struct omap_mcspi_s *s) omap_mcspi_interrupt_update(s); } -static uint32_t omap_mcspi_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_mcspi_read(void *opaque, a_target_phys_addr addr) { struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque; int ch = 0; @@ -1256,7 +1256,7 @@ static uint32_t omap_mcspi_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_mcspi_write(void *opaque, target_phys_addr_t addr, +static void omap_mcspi_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque; @@ -1696,7 +1696,7 @@ static void omap_eac_reset(struct omap_eac_s *s) omap_eac_interrupt_update(s); } -static uint32_t omap_eac_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_eac_read(void *opaque, a_target_phys_addr addr) { struct omap_eac_s *s = (struct omap_eac_s *) opaque; uint32_t ret; @@ -1807,7 +1807,7 @@ static uint32_t omap_eac_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_eac_write(void *opaque, target_phys_addr_t addr, +static void omap_eac_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_eac_s *s = (struct omap_eac_s *) opaque; @@ -2014,7 +2014,7 @@ static void omap_sti_reset(struct omap_sti_s *s) omap_sti_interrupt_update(s); } -static uint32_t omap_sti_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_sti_read(void *opaque, a_target_phys_addr addr) { struct omap_sti_s *s = (struct omap_sti_s *) opaque; @@ -2050,7 +2050,7 @@ static uint32_t omap_sti_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_sti_write(void *opaque, target_phys_addr_t addr, +static void omap_sti_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_sti_s *s = (struct omap_sti_s *) opaque; @@ -2108,13 +2108,13 @@ static CPUWriteMemoryFunc * const omap_sti_writefn[] = { omap_sti_write, }; -static uint32_t omap_sti_fifo_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_sti_fifo_read(void *opaque, a_target_phys_addr addr) { OMAP_BAD_REG(addr); return 0; } -static void omap_sti_fifo_write(void *opaque, target_phys_addr_t addr, +static void omap_sti_fifo_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_sti_s *s = (struct omap_sti_s *) opaque; @@ -2147,7 +2147,7 @@ static CPUWriteMemoryFunc * const omap_sti_fifo_writefn[] = { }; static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta, - target_phys_addr_t channel_base, qemu_irq irq, omap_clk clk, + a_target_phys_addr channel_base, qemu_irq irq, omap_clk clk, CharDriverState *chr) { int iomemtype; @@ -2175,14 +2175,14 @@ struct omap_target_agent_s { struct omap_l4_s *bus; int regions; struct omap_l4_region_s *start; - target_phys_addr_t base; + a_target_phys_addr base; uint32_t component; uint32_t control; uint32_t status; }; struct omap_l4_s { - target_phys_addr_t base; + a_target_phys_addr base; int ta_num; struct omap_target_agent_s ta[0]; }; @@ -2213,28 +2213,28 @@ int l4_register_io_memory(CPUReadMemoryFunc * const *mem_read, return omap_l4_io_entries ++; } -static uint32_t omap_l4_io_readb(void *opaque, target_phys_addr_t addr) +static uint32_t omap_l4_io_readb(void *opaque, a_target_phys_addr addr) { unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; return omap_l4_io_readb_fn[i](omap_l4_io_opaque[i], addr); } -static uint32_t omap_l4_io_readh(void *opaque, target_phys_addr_t addr) +static uint32_t omap_l4_io_readh(void *opaque, a_target_phys_addr addr) { unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; return omap_l4_io_readh_fn[i](omap_l4_io_opaque[i], addr); } -static uint32_t omap_l4_io_readw(void *opaque, target_phys_addr_t addr) +static uint32_t omap_l4_io_readw(void *opaque, a_target_phys_addr addr) { unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; return omap_l4_io_readw_fn[i](omap_l4_io_opaque[i], addr); } -static void omap_l4_io_writeb(void *opaque, target_phys_addr_t addr, +static void omap_l4_io_writeb(void *opaque, a_target_phys_addr addr, uint32_t value) { unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; @@ -2242,7 +2242,7 @@ static void omap_l4_io_writeb(void *opaque, target_phys_addr_t addr, return omap_l4_io_writeb_fn[i](omap_l4_io_opaque[i], addr, value); } -static void omap_l4_io_writeh(void *opaque, target_phys_addr_t addr, +static void omap_l4_io_writeh(void *opaque, a_target_phys_addr addr, uint32_t value) { unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; @@ -2250,7 +2250,7 @@ static void omap_l4_io_writeh(void *opaque, target_phys_addr_t addr, return omap_l4_io_writeh_fn[i](omap_l4_io_opaque[i], addr, value); } -static void omap_l4_io_writew(void *opaque, target_phys_addr_t addr, +static void omap_l4_io_writew(void *opaque, a_target_phys_addr addr, uint32_t value) { unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; @@ -2271,7 +2271,7 @@ static CPUWriteMemoryFunc * const omap_l4_io_writefn[] = { }; #endif -struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num) +struct omap_l4_s *omap_l4_init(a_target_phys_addr base, int ta_num) { struct omap_l4_s *bus = qemu_mallocz( sizeof(*bus) + ta_num * sizeof(*bus->ta)); @@ -2299,7 +2299,7 @@ struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num) return bus; } -static uint32_t omap_l4ta_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_l4ta_read(void *opaque, a_target_phys_addr addr) { struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque; @@ -2318,7 +2318,7 @@ static uint32_t omap_l4ta_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_l4ta_write(void *opaque, target_phys_addr_t addr, +static void omap_l4ta_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque; @@ -2356,7 +2356,7 @@ static CPUWriteMemoryFunc * const omap_l4ta_writefn[] = { #define L4TAO(n) ((n) + 39) static struct omap_l4_region_s { - target_phys_addr_t offset; + a_target_phys_addr offset; size_t size; int access; } omap_l4_region[125] = { @@ -2584,10 +2584,10 @@ struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs) return ta; } -target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region, +a_target_phys_addr omap_l4_attach(struct omap_target_agent_s *ta, int region, int iotype) { - target_phys_addr_t base; + a_target_phys_addr base; ssize_t size; #ifdef L4_MUX_HACK int i; @@ -2622,7 +2622,7 @@ target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region, } /* TEST-Chip-level TAP */ -static uint32_t omap_tap_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_tap_read(void *opaque, a_target_phys_addr addr) { struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; @@ -2686,7 +2686,7 @@ static uint32_t omap_tap_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_tap_write(void *opaque, target_phys_addr_t addr, +static void omap_tap_write(void *opaque, a_target_phys_addr addr, uint32_t value) { OMAP_BAD_REG(addr); @@ -2753,7 +2753,7 @@ static void omap_prcm_int_update(struct omap_prcm_s *s, int dom) /* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */ } -static uint32_t omap_prcm_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_prcm_read(void *opaque, a_target_phys_addr addr) { struct omap_prcm_s *s = (struct omap_prcm_s *) opaque; uint32_t ret; @@ -3060,7 +3060,7 @@ static void omap_prcm_dpll_update(struct omap_prcm_s *s) } } -static void omap_prcm_write(void *opaque, target_phys_addr_t addr, +static void omap_prcm_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_prcm_s *s = (struct omap_prcm_s *) opaque; @@ -3540,7 +3540,7 @@ struct omap_sysctl_s { uint32_t msuspendmux[5]; }; -static uint32_t omap_sysctl_read8(void *opaque, target_phys_addr_t addr) +static uint32_t omap_sysctl_read8(void *opaque, a_target_phys_addr addr) { struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; @@ -3565,7 +3565,7 @@ static uint32_t omap_sysctl_read8(void *opaque, target_phys_addr_t addr) return 0; } -static uint32_t omap_sysctl_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_sysctl_read(void *opaque, a_target_phys_addr addr) { struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; @@ -3665,7 +3665,7 @@ static uint32_t omap_sysctl_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_sysctl_write8(void *opaque, target_phys_addr_t addr, +static void omap_sysctl_write8(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; @@ -3689,7 +3689,7 @@ static void omap_sysctl_write8(void *opaque, target_phys_addr_t addr, } } -static void omap_sysctl_write(void *opaque, target_phys_addr_t addr, +static void omap_sysctl_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; @@ -3907,7 +3907,7 @@ static void omap_sdrc_reset(struct omap_sdrc_s *s) s->config = 0x10; } -static uint32_t omap_sdrc_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_sdrc_read(void *opaque, a_target_phys_addr addr) { struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque; @@ -3957,7 +3957,7 @@ static uint32_t omap_sdrc_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_sdrc_write(void *opaque, target_phys_addr_t addr, +static void omap_sdrc_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque; @@ -4026,7 +4026,7 @@ static CPUWriteMemoryFunc * const omap_sdrc_writefn[] = { omap_sdrc_write, }; -struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base) +struct omap_sdrc_s *omap_sdrc_init(a_target_phys_addr base) { int iomemtype; struct omap_sdrc_s *s = (struct omap_sdrc_s *) @@ -4056,10 +4056,10 @@ struct omap_gpmc_s { int prefcount; struct omap_gpmc_cs_file_s { uint32_t config[7]; - target_phys_addr_t base; + a_target_phys_addr base; size_t size; int iomemtype; - void (*base_update)(void *opaque, target_phys_addr_t new); + void (*base_update)(void *opaque, a_target_phys_addr new); void (*unmap)(void *opaque); void *opaque; } cs_file[8]; @@ -4151,7 +4151,7 @@ static void omap_gpmc_reset(struct omap_gpmc_s *s) ecc_reset(&s->ecc[i]); } -static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_gpmc_read(void *opaque, a_target_phys_addr addr) { struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque; int cs; @@ -4248,7 +4248,7 @@ static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_gpmc_write(void *opaque, target_phys_addr_t addr, +static void omap_gpmc_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque; @@ -4400,7 +4400,7 @@ static CPUWriteMemoryFunc * const omap_gpmc_writefn[] = { omap_gpmc_write, }; -struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq) +struct omap_gpmc_s *omap_gpmc_init(a_target_phys_addr base, qemu_irq irq) { int iomemtype; struct omap_gpmc_s *s = (struct omap_gpmc_s *) @@ -4416,7 +4416,7 @@ struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq) } void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype, - void (*base_upd)(void *opaque, target_phys_addr_t new), + void (*base_upd)(void *opaque, a_target_phys_addr new), void (*unmap)(void *opaque), void *opaque) { struct omap_gpmc_cs_file_s *f; @@ -4475,7 +4475,7 @@ static void omap2_mpu_reset(void *opaque) } static int omap2_validate_addr(struct omap_mpu_state_s *s, - target_phys_addr_t addr) + a_target_phys_addr addr) { return 1; } @@ -4492,7 +4492,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size, { struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) qemu_mallocz(sizeof(struct omap_mpu_state_s)); - ram_addr_t sram_base, q2_base; + a_ram_addr sram_base, q2_base; qemu_irq *cpu_irq; qemu_irq dma_irqs[4]; omap_clk gpio_clks[4]; diff --git a/hw/omap_dma.c b/hw/omap_dma.c index 205d01039c..99e4306f37 100644 --- a/hw/omap_dma.c +++ b/hw/omap_dma.c @@ -31,8 +31,8 @@ struct omap_dma_channel_s { int endian_lock[2]; int translate[2]; enum omap_dma_port port[2]; - target_phys_addr_t addr[2]; - omap_dma_addressing_t mode[2]; + a_target_phys_addr addr[2]; + e_omap_dma_addressing mode[2]; uint32_t elements; uint16_t frames; int32_t frame_index[2]; @@ -78,7 +78,7 @@ struct omap_dma_channel_s { struct omap_dma_channel_s *sibling; struct omap_dma_reg_set_s { - target_phys_addr_t src, dest; + a_target_phys_addr src, dest; int frame; int element; int pck_element; @@ -885,8 +885,8 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s, break; case 0x02: /* SYS_DMA_CCR_CH0 */ - ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14); - ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12); + ch->mode[1] = (e_omap_dma_addressing) ((value & 0xc000) >> 14); + ch->mode[0] = (e_omap_dma_addressing) ((value & 0x3000) >> 12); ch->end_prog = (value & 0x0800) >> 11; if (s->model >= omap_dma_3_2) ch->omap_3_1_compatible_disable = (value >> 10) & 0x1; @@ -911,7 +911,7 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s, break; case 0x06: /* SYS_DMA_CSR_CH0 */ - OMAP_RO_REG((target_phys_addr_t) reg); + OMAP_RO_REG((a_target_phys_addr) reg); break; case 0x08: /* SYS_DMA_CSSA_L_CH0 */ @@ -951,7 +951,7 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s, break; case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */ - OMAP_RO_REG((target_phys_addr_t) reg); + OMAP_RO_REG((a_target_phys_addr) reg); break; case 0x1c: /* DMA_CDEI */ @@ -1443,7 +1443,7 @@ static int omap_dma_sys_read(struct omap_dma_s *s, int offset, return 0; } -static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_dma_read(void *opaque, a_target_phys_addr addr) { struct omap_dma_s *s = (struct omap_dma_s *) opaque; int reg, ch; @@ -1486,7 +1486,7 @@ static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_dma_write(void *opaque, target_phys_addr_t addr, +static void omap_dma_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_dma_s *s = (struct omap_dma_s *) opaque; @@ -1612,7 +1612,7 @@ static void omap_dma_setcaps(struct omap_dma_s *s) } } -struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs, +struct soc_dma_s *omap_dma_init(a_target_phys_addr base, qemu_irq *irqs, qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk, enum omap_dma_model model) { @@ -1686,7 +1686,7 @@ static void omap_dma_interrupts_4_update(struct omap_dma_s *s) qemu_irq_raise(s->irq[3]); } -static uint32_t omap_dma4_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_dma4_read(void *opaque, a_target_phys_addr addr) { struct omap_dma_s *s = (struct omap_dma_s *) opaque; int irqn = 0, chnum; @@ -1831,7 +1831,7 @@ static uint32_t omap_dma4_read(void *opaque, target_phys_addr_t addr) } } -static void omap_dma4_write(void *opaque, target_phys_addr_t addr, +static void omap_dma4_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_dma_s *s = (struct omap_dma_s *) opaque; @@ -1908,8 +1908,8 @@ static void omap_dma4_write(void *opaque, target_phys_addr_t addr, ch->bs = (value >> 18) & 1; ch->transparent_copy = (value >> 17) & 1; ch->constant_fill = (value >> 16) & 1; - ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14); - ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12); + ch->mode[1] = (e_omap_dma_addressing) ((value & 0xc000) >> 14); + ch->mode[0] = (e_omap_dma_addressing) ((value & 0x3000) >> 12); ch->suspend = (value & 0x0100) >> 8; ch->priority = (value & 0x0040) >> 6; ch->fs = (value & 0x0020) >> 5; @@ -1973,12 +1973,12 @@ static void omap_dma4_write(void *opaque, target_phys_addr_t addr, break; case 0x1c: /* DMA4_CSSA */ - ch->addr[0] = (target_phys_addr_t) (uint32_t) value; + ch->addr[0] = (a_target_phys_addr) (uint32_t) value; ch->set_update = 1; break; case 0x20: /* DMA4_CDSA */ - ch->addr[1] = (target_phys_addr_t) (uint32_t) value; + ch->addr[1] = (a_target_phys_addr) (uint32_t) value; ch->set_update = 1; break; @@ -2031,7 +2031,7 @@ static CPUWriteMemoryFunc * const omap_dma4_writefn[] = { omap_dma4_write, }; -struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs, +struct soc_dma_s *omap_dma4_init(a_target_phys_addr base, qemu_irq *irqs, struct omap_mpu_state_s *mpu, int fifo, int chans, omap_clk iclk, omap_clk fclk) { diff --git a/hw/omap_dss.c b/hw/omap_dss.c index 044f2d2428..12d288052d 100644 --- a/hw/omap_dss.c +++ b/hw/omap_dss.c @@ -59,7 +59,7 @@ struct omap_dss_s { int nx; int ny; - target_phys_addr_t addr[3]; + a_target_phys_addr addr[3]; uint32_t attr; uint32_t tresh; @@ -167,7 +167,7 @@ void omap_dss_reset(struct omap_dss_s *s) omap_dispc_interrupt_update(s); } -static uint32_t omap_diss_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_diss_read(void *opaque, a_target_phys_addr addr) { struct omap_dss_s *s = (struct omap_dss_s *) opaque; @@ -200,7 +200,7 @@ static uint32_t omap_diss_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_diss_write(void *opaque, target_phys_addr_t addr, +static void omap_diss_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_dss_s *s = (struct omap_dss_s *) opaque; @@ -242,7 +242,7 @@ static CPUWriteMemoryFunc * const omap_diss1_writefn[] = { omap_diss_write, }; -static uint32_t omap_disc_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_disc_read(void *opaque, a_target_phys_addr addr) { struct omap_dss_s *s = (struct omap_dss_s *) opaque; @@ -362,7 +362,7 @@ static uint32_t omap_disc_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_disc_write(void *opaque, target_phys_addr_t addr, +static void omap_disc_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_dss_s *s = (struct omap_dss_s *) opaque; @@ -488,11 +488,11 @@ static void omap_disc_write(void *opaque, target_phys_addr_t addr, s->dispc.invalidate = 1; break; case 0x080: /* DISPC_GFX_BA0 */ - s->dispc.l[0].addr[0] = (target_phys_addr_t) value; + s->dispc.l[0].addr[0] = (a_target_phys_addr) value; s->dispc.invalidate = 1; break; case 0x084: /* DISPC_GFX_BA1 */ - s->dispc.l[0].addr[1] = (target_phys_addr_t) value; + s->dispc.l[0].addr[1] = (a_target_phys_addr) value; s->dispc.invalidate = 1; break; case 0x088: /* DISPC_GFX_POSITION */ @@ -529,7 +529,7 @@ static void omap_disc_write(void *opaque, target_phys_addr_t addr, s->dispc.l[0].wininc = value; break; case 0x0b8: /* DISPC_GFX_TABLE_BA */ - s->dispc.l[0].addr[2] = (target_phys_addr_t) value; + s->dispc.l[0].addr[2] = (a_target_phys_addr) value; s->dispc.invalidate = 1; break; @@ -594,11 +594,11 @@ static void omap_rfbi_transfer_stop(struct omap_dss_s *s) static void omap_rfbi_transfer_start(struct omap_dss_s *s) { void *data; - target_phys_addr_t len; - target_phys_addr_t data_addr; + a_target_phys_addr len; + a_target_phys_addr data_addr; int pitch; static void *bounce_buffer; - static target_phys_addr_t bounce_len; + static a_target_phys_addr bounce_len; if (!s->rfbi.enable || s->rfbi.busy) return; @@ -655,7 +655,7 @@ static void omap_rfbi_transfer_start(struct omap_dss_s *s) omap_dispc_interrupt_update(s); } -static uint32_t omap_rfbi_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_rfbi_read(void *opaque, a_target_phys_addr addr) { struct omap_dss_s *s = (struct omap_dss_s *) opaque; @@ -717,7 +717,7 @@ static uint32_t omap_rfbi_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_rfbi_write(void *opaque, target_phys_addr_t addr, +static void omap_rfbi_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_dss_s *s = (struct omap_dss_s *) opaque; @@ -853,7 +853,7 @@ static CPUWriteMemoryFunc * const omap_rfbi1_writefn[] = { omap_rfbi_write, }; -static uint32_t omap_venc_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_venc_read(void *opaque, a_target_phys_addr addr) { switch (addr) { case 0x00: /* REV_ID */ @@ -908,7 +908,7 @@ static uint32_t omap_venc_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_venc_write(void *opaque, target_phys_addr_t addr, +static void omap_venc_write(void *opaque, a_target_phys_addr addr, uint32_t value) { switch (addr) { @@ -972,7 +972,7 @@ static CPUWriteMemoryFunc * const omap_venc1_writefn[] = { omap_venc_write, }; -static uint32_t omap_im3_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_im3_read(void *opaque, a_target_phys_addr addr) { switch (addr) { case 0x0a8: /* SBIMERRLOGA */ @@ -993,7 +993,7 @@ static uint32_t omap_im3_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_im3_write(void *opaque, target_phys_addr_t addr, +static void omap_im3_write(void *opaque, a_target_phys_addr addr, uint32_t value) { switch (addr) { @@ -1023,7 +1023,7 @@ static CPUWriteMemoryFunc * const omap_im3_writefn[] = { }; struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta, - target_phys_addr_t l3_base, + a_target_phys_addr l3_base, qemu_irq irq, qemu_irq drq, omap_clk fck1, omap_clk fck2, omap_clk ck54m, omap_clk ick1, omap_clk ick2) diff --git a/hw/omap_i2c.c b/hw/omap_i2c.c index d7c18882da..570db9f030 100644 --- a/hw/omap_i2c.c +++ b/hw/omap_i2c.c @@ -140,7 +140,7 @@ void omap_i2c_reset(struct omap_i2c_s *s) s->test = 0; } -static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_i2c_read(void *opaque, a_target_phys_addr addr) { struct omap_i2c_s *s = (struct omap_i2c_s *) opaque; int offset = addr & OMAP_MPUI_REG_MASK; @@ -238,7 +238,7 @@ static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_i2c_write(void *opaque, target_phys_addr_t addr, +static void omap_i2c_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_i2c_s *s = (struct omap_i2c_s *) opaque; @@ -380,7 +380,7 @@ static void omap_i2c_write(void *opaque, target_phys_addr_t addr, } } -static void omap_i2c_writeb(void *opaque, target_phys_addr_t addr, +static void omap_i2c_writeb(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_i2c_s *s = (struct omap_i2c_s *) opaque; @@ -420,7 +420,7 @@ static CPUWriteMemoryFunc * const omap_i2c_writefn[] = { omap_badwidth_write16, }; -struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base, +struct omap_i2c_s *omap_i2c_init(a_target_phys_addr base, qemu_irq irq, qemu_irq *dma, omap_clk clk) { int iomemtype; diff --git a/hw/omap_lcdc.c b/hw/omap_lcdc.c index 6affef67b9..d762f91216 100644 --- a/hw/omap_lcdc.c +++ b/hw/omap_lcdc.c @@ -24,8 +24,8 @@ struct omap_lcd_panel_s { qemu_irq irq; DisplayState *state; - ram_addr_t imif_base; - ram_addr_t emiff_base; + a_ram_addr imif_base; + a_ram_addr emiff_base; int plm; int tft; @@ -117,7 +117,7 @@ static void omap_update_display(void *opaque) draw_line_func draw_line; int size, height, first, last; int width, linesize, step, bpp, frame_offset; - target_phys_addr_t frame_base; + a_target_phys_addr frame_base; if (!omap_lcd || omap_lcd->plm == 1 || !omap_lcd->enable || !ds_get_bits_per_pixel(omap_lcd->state)) @@ -325,7 +325,7 @@ static void omap_lcd_update(struct omap_lcd_panel_s *s) { } } -static uint32_t omap_lcdc_read(void *opaque, target_phys_addr_t addr) +static uint32_t omap_lcdc_read(void *opaque, a_target_phys_addr addr) { struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque; @@ -357,7 +357,7 @@ static uint32_t omap_lcdc_read(void *opaque, target_phys_addr_t addr) return 0; } -static void omap_lcdc_write(void *opaque, target_phys_addr_t addr, +static void omap_lcdc_write(void *opaque, a_target_phys_addr addr, uint32_t value) { struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque; @@ -435,9 +435,9 @@ void omap_lcdc_reset(struct omap_lcd_panel_s *s) s->ctrl = 0; } -struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq, +struct omap_lcd_panel_s *omap_lcdc_init(a_target_phys_addr base, qemu_irq irq, struct omap_dma_lcd_channel_s *dma, - ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk) + a_ram_addr imif_base, a_ram_addr emiff_base, omap_clk clk) { int iomemtype; struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) diff --git a/hw/omap_mmc.c b/hw/omap_mmc.c index 15cbf06c87..7edfba5cb1 100644 --- a/hw/omap_mmc.c +++ b/hw/omap_mmc.c @@ -104,10 +104,10 @@ typedef enum { sd_r3, /* OCR register */ sd_r6 = 6, /* Published RCA response */ sd_r1b = -1, -} sd_rsp_type_t; +} e_sd_rsp_type; static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir, - sd_cmd_type_t type, int busy, sd_rsp_type_t resptype, int init) + e_sd_cmd_type type, int busy, e_sd_rsp_type resptype, int init) { uint32_t rspstatus, mask; int rsplen, timeout; @@ -305,7 +305,7 @@ void omap_mmc_reset(struct omap_mmc_s *host) host->clkdiv = 0; } -static uint32_t omap_mmc_read(void *opaque, target_phys_addr_t offset) +static uint32_t omap_mmc_read(void *opaque, a_target_phys_addr offset) { uint16_t i; struct omap_mmc_s *s = (struct omap_mmc_s *) opaque; @@ -394,7 +394,7 @@ static uint32_t omap_mmc_read(void *opaque, target_phys_addr_t offset) return 0; } -static void omap_mmc_write(void *opaque, target_phys_addr_t offset, +static void omap_mmc_write(void *opaque, a_target_phys_addr offset, uint32_t value) { int i; @@ -410,9 +410,9 @@ static void omap_mmc_write(void *opaque, target_phys_addr_t offset, for (i = 0; i < 8; i ++) s->rsp[i] = 0x0000; omap_mmc_command(s, value & 63, (value >> 15) & 1, - (sd_cmd_type_t) ((value >> 12) & 3), + (e_sd_cmd_type) ((value >> 12) & 3), (value >> 11) & 1, - (sd_rsp_type_t) ((value >> 8) & 7), + (e_sd_rsp_type) ((value >> 8) & 7), (value >> 7) & 1); omap_mmc_update(s); break; @@ -569,7 +569,7 @@ static void omap_mmc_cover_cb(void *opaque, int line, int level) } } -struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base, +struct omap_mmc_s *omap_mmc_init(a_target_phys_addr base, BlockDriverState *bd, qemu_irq irq, qemu_irq dma[], omap_clk clk) { diff --git a/hw/omap_sx1.c b/hw/omap_sx1.c index 255dcbd74d..99744c548e 100644 --- a/hw/omap_sx1.c +++ b/hw/omap_sx1.c @@ -58,28 +58,28 @@ * - 1 RTC */ -static uint32_t static_readb(void *opaque, target_phys_addr_t offset) +static uint32_t static_readb(void *opaque, a_target_phys_addr offset) { uint32_t *val = (uint32_t *) opaque; return *val >> ((offset & 3) << 3); } -static uint32_t static_readh(void *opaque, target_phys_addr_t offset) +static uint32_t static_readh(void *opaque, a_target_phys_addr offset) { uint32_t *val = (uint32_t *) opaque; return *val >> ((offset & 1) << 3); } -static uint32_t static_readw(void *opaque, target_phys_addr_t offset) +static uint32_t static_readw(void *opaque, a_target_phys_addr offset) { uint32_t *val = (uint32_t *) opaque; return *val >> ((offset & 0) << 3); } -static void static_write(void *opaque, target_phys_addr_t offset, +static void static_write(void *opaque, a_target_phys_addr offset, uint32_t value) { #ifdef SPY @@ -114,7 +114,7 @@ static struct arm_boot_info sx1_binfo = { .board_id = 0x265, }; -static void sx1_init(ram_addr_t ram_size, +static void sx1_init(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model, @@ -126,7 +126,7 @@ static void sx1_init(ram_addr_t ram_size, static uint32_t cs1val = 0x00215070; static uint32_t cs2val = 0x00001139; static uint32_t cs3val = 0x00001139; - ram_addr_t phys_flash; + a_ram_addr phys_flash; DriveInfo *dinfo; int fl_idx; uint32_t flash_size = flash0_size; @@ -204,7 +204,7 @@ static void sx1_init(ram_addr_t ram_size, //~ qemu_console_resize(ds, 640, 480); } -static void sx1_init_v1(ram_addr_t ram_size, +static void sx1_init_v1(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -213,7 +213,7 @@ static void sx1_init_v1(ram_addr_t ram_size, kernel_cmdline, initrd_filename, cpu_model, 1); } -static void sx1_init_v2(ram_addr_t ram_size, +static void sx1_init_v2(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) diff --git a/hw/onenand.c b/hw/onenand.c index c1e7e4d608..46fabedccf 100644 --- a/hw/onenand.c +++ b/hw/onenand.c @@ -33,7 +33,7 @@ typedef struct { uint32_t id; int shift; - target_phys_addr_t base; + a_target_phys_addr base; qemu_irq intr; qemu_irq rdy; BlockDriverState *bdrv; @@ -41,7 +41,7 @@ typedef struct { uint8_t *image; uint8_t *otp; uint8_t *current; - ram_addr_t ram; + a_ram_addr ram; uint8_t *boot[2]; uint8_t *data[2][2]; int iomemtype; @@ -96,7 +96,7 @@ enum { ONEN_LOCK_UNLOCKED = 1 << 2, }; -void onenand_base_update(void *opaque, target_phys_addr_t new) +void onenand_base_update(void *opaque, a_target_phys_addr new) { OneNANDState *s = (OneNANDState *) opaque; @@ -443,7 +443,7 @@ static void onenand_command(OneNANDState *s, int cmd) onenand_intr_update(s); } -static uint32_t onenand_read(void *opaque, target_phys_addr_t addr) +static uint32_t onenand_read(void *opaque, a_target_phys_addr addr) { OneNANDState *s = (OneNANDState *) opaque; int offset = addr >> s->shift; @@ -507,7 +507,7 @@ static uint32_t onenand_read(void *opaque, target_phys_addr_t addr) return 0; } -static void onenand_write(void *opaque, target_phys_addr_t addr, +static void onenand_write(void *opaque, a_target_phys_addr addr, uint32_t value) { OneNANDState *s = (OneNANDState *) opaque; diff --git a/hw/openpic.c b/hw/openpic.c index 74dde6d1cb..eea3e309dd 100644 --- a/hw/openpic.c +++ b/hw/openpic.c @@ -166,19 +166,19 @@ enum { IRQ_SPECIAL = 0x08, }; -typedef struct IRQ_queue_t { +typedef struct IRQ_queue { uint32_t queue[BF_WIDTH(MAX_IRQ)]; int next; int priority; -} IRQ_queue_t; +} a_IRQ_queue; -typedef struct IRQ_src_t { +typedef struct IRQ_src { uint32_t ipvp; /* IRQ vector/priority register */ uint32_t ide; /* IRQ destination register */ int type; int last_cpu; int pending; /* TRUE if IRQ is pending */ -} IRQ_src_t; +} a_IRQ_src; enum IPVP_bits { IPVP_MASK = 31, @@ -192,16 +192,16 @@ enum IPVP_bits { #define IPVP_VECTOR_MASK ((1 << VECTOR_BITS) - 1) #define IPVP_VECTOR(_ipvpr_) ((_ipvpr_) & IPVP_VECTOR_MASK) -typedef struct IRQ_dst_t { +typedef struct IRQ_dst { uint32_t tfrr; uint32_t pctp; /* CPU current task priority */ uint32_t pcsr; /* CPU sensitivity register */ - IRQ_queue_t raised; - IRQ_queue_t servicing; + a_IRQ_queue raised; + a_IRQ_queue servicing; qemu_irq *irqs; -} IRQ_dst_t; +} a_IRQ_dst; -typedef struct openpic_t { +typedef struct openpic { PCIDevice pci_dev; int mem_index; /* Global registers */ @@ -213,9 +213,9 @@ typedef struct openpic_t { uint32_t spve; /* Spurious vector register */ uint32_t tifr; /* Timer frequency reporting register */ /* Source registers */ - IRQ_src_t src[MAX_IRQ]; + a_IRQ_src src[MAX_IRQ]; /* Local registers per output pin */ - IRQ_dst_t dst[MAX_CPU]; + a_IRQ_dst dst[MAX_CPU]; int nb_cpus; /* Timer registers */ struct { @@ -242,10 +242,10 @@ typedef struct openpic_t { int irq_tim0; int need_swap; void (*reset) (void *); - void (*irq_raise) (struct openpic_t *, int, IRQ_src_t *); -} openpic_t; + void (*irq_raise) (struct openpic *, int, a_IRQ_src *); +} a_openpic; -static inline uint32_t openpic_swap32(openpic_t *opp, uint32_t val) +static inline uint32_t openpic_swap32(a_openpic *opp, uint32_t val) { if (opp->need_swap) return bswap32(val); @@ -253,22 +253,22 @@ static inline uint32_t openpic_swap32(openpic_t *opp, uint32_t val) return val; } -static inline void IRQ_setbit (IRQ_queue_t *q, int n_IRQ) +static inline void IRQ_setbit (a_IRQ_queue *q, int n_IRQ) { set_bit(q->queue, n_IRQ); } -static inline void IRQ_resetbit (IRQ_queue_t *q, int n_IRQ) +static inline void IRQ_resetbit (a_IRQ_queue *q, int n_IRQ) { reset_bit(q->queue, n_IRQ); } -static inline int IRQ_testbit (IRQ_queue_t *q, int n_IRQ) +static inline int IRQ_testbit (a_IRQ_queue *q, int n_IRQ) { return test_bit(q->queue, n_IRQ); } -static void IRQ_check (openpic_t *opp, IRQ_queue_t *q) +static void IRQ_check (a_openpic *opp, a_IRQ_queue *q) { int next, i; int priority; @@ -289,7 +289,7 @@ static void IRQ_check (openpic_t *opp, IRQ_queue_t *q) q->priority = priority; } -static int IRQ_get_next (openpic_t *opp, IRQ_queue_t *q) +static int IRQ_get_next (a_openpic *opp, a_IRQ_queue *q) { if (q->next == -1) { /* XXX: optimize */ @@ -299,10 +299,10 @@ static int IRQ_get_next (openpic_t *opp, IRQ_queue_t *q) return q->next; } -static void IRQ_local_pipe (openpic_t *opp, int n_CPU, int n_IRQ) +static void IRQ_local_pipe (a_openpic *opp, int n_CPU, int n_IRQ) { - IRQ_dst_t *dst; - IRQ_src_t *src; + a_IRQ_dst *dst; + a_IRQ_src *src; int priority; dst = &opp->dst[n_CPU]; @@ -341,9 +341,9 @@ static void IRQ_local_pipe (openpic_t *opp, int n_CPU, int n_IRQ) } /* update pic state because registers for n_IRQ have changed value */ -static void openpic_update_irq(openpic_t *opp, int n_IRQ) +static void openpic_update_irq(a_openpic *opp, int n_IRQ) { - IRQ_src_t *src; + a_IRQ_src *src; int i; src = &opp->src[n_IRQ]; @@ -399,8 +399,8 @@ static void openpic_update_irq(openpic_t *opp, int n_IRQ) static void openpic_set_irq(void *opaque, int n_IRQ, int level) { - openpic_t *opp = opaque; - IRQ_src_t *src; + a_openpic *opp = opaque; + a_IRQ_src *src; src = &opp->src[n_IRQ]; DPRINTF("openpic: set irq %d = %d ipvp=%08x\n", @@ -420,7 +420,7 @@ static void openpic_set_irq(void *opaque, int n_IRQ, int level) static void openpic_reset (void *opaque) { - openpic_t *opp = (openpic_t *)opaque; + a_openpic *opp = (a_openpic *)opaque; int i; opp->glbc = 0x80000000; @@ -441,8 +441,8 @@ static void openpic_reset (void *opaque) for (i = 0; i < MAX_CPU; i++) { opp->dst[i].pctp = 0x0000000F; opp->dst[i].pcsr = 0x00000000; - memset(&opp->dst[i].raised, 0, sizeof(IRQ_queue_t)); - memset(&opp->dst[i].servicing, 0, sizeof(IRQ_queue_t)); + memset(&opp->dst[i].raised, 0, sizeof(a_IRQ_queue)); + memset(&opp->dst[i].servicing, 0, sizeof(a_IRQ_queue)); } /* Initialise timers */ for (i = 0; i < MAX_TMR; i++) { @@ -466,7 +466,7 @@ static void openpic_reset (void *opaque) opp->glbc = 0x00000000; } -static inline uint32_t read_IRQreg (openpic_t *opp, int n_IRQ, uint32_t reg) +static inline uint32_t read_IRQreg (a_openpic *opp, int n_IRQ, uint32_t reg) { uint32_t retval; @@ -482,7 +482,7 @@ static inline uint32_t read_IRQreg (openpic_t *opp, int n_IRQ, uint32_t reg) return retval; } -static inline void write_IRQreg (openpic_t *opp, int n_IRQ, +static inline void write_IRQreg (a_openpic *opp, int n_IRQ, uint32_t reg, uint32_t val) { uint32_t tmp; @@ -510,7 +510,7 @@ static inline void write_IRQreg (openpic_t *opp, int n_IRQ, #if 0 // Code provision for Intel model #if MAX_DBL > 0 -static uint32_t read_doorbell_register (openpic_t *opp, +static uint32_t read_doorbell_register (a_openpic *opp, int n_dbl, uint32_t offset) { uint32_t retval; @@ -548,7 +548,7 @@ static void write_doorbell_register (penpic_t *opp, int n_dbl, #endif #if MAX_MBX > 0 -static uint32_t read_mailbox_register (openpic_t *opp, +static uint32_t read_mailbox_register (a_openpic *opp, int n_mbx, uint32_t offset) { uint32_t retval; @@ -568,7 +568,7 @@ static uint32_t read_mailbox_register (openpic_t *opp, return retval; } -static void write_mailbox_register (openpic_t *opp, int n_mbx, +static void write_mailbox_register (a_openpic *opp, int n_mbx, uint32_t address, uint32_t value) { switch (offset) { @@ -586,10 +586,10 @@ static void write_mailbox_register (openpic_t *opp, int n_mbx, #endif #endif /* 0 : Code provision for Intel model */ -static void openpic_gbl_write (void *opaque, target_phys_addr_t addr, uint32_t val) +static void openpic_gbl_write (void *opaque, a_target_phys_addr addr, uint32_t val) { - openpic_t *opp = opaque; - IRQ_dst_t *dst; + a_openpic *opp = opaque; + a_IRQ_dst *dst; int idx; DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val); @@ -646,9 +646,9 @@ static void openpic_gbl_write (void *opaque, target_phys_addr_t addr, uint32_t v } } -static uint32_t openpic_gbl_read (void *opaque, target_phys_addr_t addr) +static uint32_t openpic_gbl_read (void *opaque, a_target_phys_addr addr) { - openpic_t *opp = opaque; + a_openpic *opp = opaque; uint32_t retval; DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr); @@ -700,7 +700,7 @@ static uint32_t openpic_gbl_read (void *opaque, target_phys_addr_t addr) static void openpic_timer_write (void *opaque, uint32_t addr, uint32_t val) { - openpic_t *opp = opaque; + a_openpic *opp = opaque; int idx; DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val); @@ -734,7 +734,7 @@ static void openpic_timer_write (void *opaque, uint32_t addr, uint32_t val) static uint32_t openpic_timer_read (void *opaque, uint32_t addr) { - openpic_t *opp = opaque; + a_openpic *opp = opaque; uint32_t retval; int idx; @@ -770,7 +770,7 @@ static uint32_t openpic_timer_read (void *opaque, uint32_t addr) static void openpic_src_write (void *opaque, uint32_t addr, uint32_t val) { - openpic_t *opp = opaque; + a_openpic *opp = opaque; int idx; DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val); @@ -792,7 +792,7 @@ static void openpic_src_write (void *opaque, uint32_t addr, uint32_t val) static uint32_t openpic_src_read (void *opaque, uint32_t addr) { - openpic_t *opp = opaque; + a_openpic *opp = opaque; uint32_t retval; int idx; @@ -817,11 +817,11 @@ static uint32_t openpic_src_read (void *opaque, uint32_t addr) return retval; } -static void openpic_cpu_write (void *opaque, target_phys_addr_t addr, uint32_t val) +static void openpic_cpu_write (void *opaque, a_target_phys_addr addr, uint32_t val) { - openpic_t *opp = opaque; - IRQ_src_t *src; - IRQ_dst_t *dst; + a_openpic *opp = opaque; + a_IRQ_src *src; + a_IRQ_dst *dst; int idx, s_IRQ, n_IRQ; DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val); @@ -878,11 +878,11 @@ static void openpic_cpu_write (void *opaque, target_phys_addr_t addr, uint32_t v } } -static uint32_t openpic_cpu_read (void *opaque, target_phys_addr_t addr) +static uint32_t openpic_cpu_read (void *opaque, a_target_phys_addr addr) { - openpic_t *opp = opaque; - IRQ_src_t *src; - IRQ_dst_t *dst; + a_openpic *opp = opaque; + a_IRQ_src *src; + a_IRQ_dst *dst; uint32_t retval; int idx, n_IRQ; @@ -955,12 +955,12 @@ static uint32_t openpic_cpu_read (void *opaque, target_phys_addr_t addr) } static void openpic_buggy_write (void *opaque, - target_phys_addr_t addr, uint32_t val) + a_target_phys_addr addr, uint32_t val) { printf("Invalid OPENPIC write access !\n"); } -static uint32_t openpic_buggy_read (void *opaque, target_phys_addr_t addr) +static uint32_t openpic_buggy_read (void *opaque, a_target_phys_addr addr) { printf("Invalid OPENPIC read access !\n"); @@ -968,9 +968,9 @@ static uint32_t openpic_buggy_read (void *opaque, target_phys_addr_t addr) } static void openpic_writel (void *opaque, - target_phys_addr_t addr, uint32_t val) + a_target_phys_addr addr, uint32_t val) { - openpic_t *opp = opaque; + a_openpic *opp = opaque; addr &= 0x3FFFF; DPRINTF("%s: offset %08x val: %08x\n", __func__, (int)addr, val); @@ -989,9 +989,9 @@ static void openpic_writel (void *opaque, } } -static uint32_t openpic_readl (void *opaque,target_phys_addr_t addr) +static uint32_t openpic_readl (void *opaque,a_target_phys_addr addr) { - openpic_t *opp = opaque; + a_openpic *opp = opaque; uint32_t retval; addr &= 0x3FFFF; @@ -1028,10 +1028,10 @@ static CPUReadMemoryFunc * const openpic_read[] = { static void openpic_map(PCIDevice *pci_dev, int region_num, uint32_t addr, uint32_t size, int type) { - openpic_t *opp; + a_openpic *opp; DPRINTF("Map OpenPIC\n"); - opp = (openpic_t *)pci_dev; + opp = (a_openpic *)pci_dev; /* Global registers */ DPRINTF("Register OPENPIC gbl %08x => %08x\n", addr + 0x1000, addr + 0x1000 + 0x100); @@ -1053,7 +1053,7 @@ static void openpic_map(PCIDevice *pci_dev, int region_num, #endif } -static void openpic_save_IRQ_queue(QEMUFile* f, IRQ_queue_t *q) +static void openpic_save_IRQ_queue(QEMUFile* f, a_IRQ_queue *q) { unsigned int i; @@ -1066,7 +1066,7 @@ static void openpic_save_IRQ_queue(QEMUFile* f, IRQ_queue_t *q) static void openpic_save(QEMUFile* f, void *opaque) { - openpic_t *opp = (openpic_t *)opaque; + a_openpic *opp = (a_openpic *)opaque; unsigned int i; qemu_put_be32s(f, &opp->frep); @@ -1117,7 +1117,7 @@ static void openpic_save(QEMUFile* f, void *opaque) pci_device_save(&opp->pci_dev, f); } -static void openpic_load_IRQ_queue(QEMUFile* f, IRQ_queue_t *q) +static void openpic_load_IRQ_queue(QEMUFile* f, a_IRQ_queue *q) { unsigned int i; @@ -1130,7 +1130,7 @@ static void openpic_load_IRQ_queue(QEMUFile* f, IRQ_queue_t *q) static int openpic_load(QEMUFile* f, void *opaque, int version_id) { - openpic_t *opp = (openpic_t *)opaque; + a_openpic *opp = (a_openpic *)opaque; unsigned int i; if (version_id != 1) @@ -1184,7 +1184,7 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id) return pci_device_load(&opp->pci_dev, f); } -static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src) +static void openpic_irq_raise(a_openpic *opp, int n_CPU, a_IRQ_src *src) { qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]); } @@ -1192,7 +1192,7 @@ static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src) qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus, qemu_irq **irqs, qemu_irq irq_out) { - openpic_t *opp; + a_openpic *opp; uint8_t *pci_conf; int i, m; @@ -1200,7 +1200,7 @@ qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus, if (nb_cpus != 1) return NULL; if (bus) { - opp = (openpic_t *)pci_register_device(bus, "OpenPIC", sizeof(openpic_t), + opp = (a_openpic *)pci_register_device(bus, "OpenPIC", sizeof(a_openpic), -1, NULL, NULL); if (opp == NULL) return NULL; @@ -1215,7 +1215,7 @@ qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus, pci_register_bar((PCIDevice *)opp, 0, 0x40000, PCI_ADDRESS_SPACE_MEM, &openpic_map); } else { - opp = qemu_mallocz(sizeof(openpic_t)); + opp = qemu_mallocz(sizeof(a_openpic)); } opp->mem_index = cpu_register_io_memory(openpic_read, openpic_write, opp); @@ -1261,7 +1261,7 @@ qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus, return qemu_allocate_irqs(openpic_set_irq, opp, opp->max_irq); } -static void mpic_irq_raise(openpic_t *mpp, int n_CPU, IRQ_src_t *src) +static void mpic_irq_raise(a_openpic *mpp, int n_CPU, a_IRQ_src *src) { int n_ci = IDR_CI0 - n_CPU; @@ -1275,7 +1275,7 @@ static void mpic_irq_raise(openpic_t *mpp, int n_CPU, IRQ_src_t *src) static void mpic_reset (void *opaque) { - openpic_t *mpp = (openpic_t *)opaque; + a_openpic *mpp = (a_openpic *)opaque; int i; mpp->glbc = 0x80000000; @@ -1293,9 +1293,9 @@ static void mpic_reset (void *opaque) for (i = 0; i < MAX_CPU; i++) { mpp->dst[i].pctp = 0x0000000F; mpp->dst[i].tfrr = 0x00000000; - memset(&mpp->dst[i].raised, 0, sizeof(IRQ_queue_t)); + memset(&mpp->dst[i].raised, 0, sizeof(a_IRQ_queue)); mpp->dst[i].raised.next = -1; - memset(&mpp->dst[i].servicing, 0, sizeof(IRQ_queue_t)); + memset(&mpp->dst[i].servicing, 0, sizeof(a_IRQ_queue)); mpp->dst[i].servicing.next = -1; } /* Initialise timers */ @@ -1307,9 +1307,9 @@ static void mpic_reset (void *opaque) mpp->glbc = 0x00000000; } -static void mpic_timer_write (void *opaque, target_phys_addr_t addr, uint32_t val) +static void mpic_timer_write (void *opaque, a_target_phys_addr addr, uint32_t val) { - openpic_t *mpp = opaque; + a_openpic *mpp = opaque; int idx, cpu; DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val); @@ -1340,9 +1340,9 @@ static void mpic_timer_write (void *opaque, target_phys_addr_t addr, uint32_t va } } -static uint32_t mpic_timer_read (void *opaque, target_phys_addr_t addr) +static uint32_t mpic_timer_read (void *opaque, a_target_phys_addr addr) { - openpic_t *mpp = opaque; + a_openpic *mpp = opaque; uint32_t retval; int idx, cpu; @@ -1375,10 +1375,10 @@ static uint32_t mpic_timer_read (void *opaque, target_phys_addr_t addr) return retval; } -static void mpic_src_ext_write (void *opaque, target_phys_addr_t addr, +static void mpic_src_ext_write (void *opaque, a_target_phys_addr addr, uint32_t val) { - openpic_t *mpp = opaque; + a_openpic *mpp = opaque; int idx = MPIC_EXT_IRQ; DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val); @@ -1398,9 +1398,9 @@ static void mpic_src_ext_write (void *opaque, target_phys_addr_t addr, } } -static uint32_t mpic_src_ext_read (void *opaque, target_phys_addr_t addr) +static uint32_t mpic_src_ext_read (void *opaque, a_target_phys_addr addr) { - openpic_t *mpp = opaque; + a_openpic *mpp = opaque; uint32_t retval; int idx = MPIC_EXT_IRQ; @@ -1425,10 +1425,10 @@ static uint32_t mpic_src_ext_read (void *opaque, target_phys_addr_t addr) return retval; } -static void mpic_src_int_write (void *opaque, target_phys_addr_t addr, +static void mpic_src_int_write (void *opaque, a_target_phys_addr addr, uint32_t val) { - openpic_t *mpp = opaque; + a_openpic *mpp = opaque; int idx = MPIC_INT_IRQ; DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val); @@ -1448,9 +1448,9 @@ static void mpic_src_int_write (void *opaque, target_phys_addr_t addr, } } -static uint32_t mpic_src_int_read (void *opaque, target_phys_addr_t addr) +static uint32_t mpic_src_int_read (void *opaque, a_target_phys_addr addr) { - openpic_t *mpp = opaque; + a_openpic *mpp = opaque; uint32_t retval; int idx = MPIC_INT_IRQ; @@ -1475,10 +1475,10 @@ static uint32_t mpic_src_int_read (void *opaque, target_phys_addr_t addr) return retval; } -static void mpic_src_msg_write (void *opaque, target_phys_addr_t addr, +static void mpic_src_msg_write (void *opaque, a_target_phys_addr addr, uint32_t val) { - openpic_t *mpp = opaque; + a_openpic *mpp = opaque; int idx = MPIC_MSG_IRQ; DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val); @@ -1498,9 +1498,9 @@ static void mpic_src_msg_write (void *opaque, target_phys_addr_t addr, } } -static uint32_t mpic_src_msg_read (void *opaque, target_phys_addr_t addr) +static uint32_t mpic_src_msg_read (void *opaque, a_target_phys_addr addr) { - openpic_t *mpp = opaque; + a_openpic *mpp = opaque; uint32_t retval; int idx = MPIC_MSG_IRQ; @@ -1525,10 +1525,10 @@ static uint32_t mpic_src_msg_read (void *opaque, target_phys_addr_t addr) return retval; } -static void mpic_src_msi_write (void *opaque, target_phys_addr_t addr, +static void mpic_src_msi_write (void *opaque, a_target_phys_addr addr, uint32_t val) { - openpic_t *mpp = opaque; + a_openpic *mpp = opaque; int idx = MPIC_MSI_IRQ; DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val); @@ -1547,9 +1547,9 @@ static void mpic_src_msi_write (void *opaque, target_phys_addr_t addr, } } } -static uint32_t mpic_src_msi_read (void *opaque, target_phys_addr_t addr) +static uint32_t mpic_src_msi_read (void *opaque, a_target_phys_addr addr) { - openpic_t *mpp = opaque; + a_openpic *mpp = opaque; uint32_t retval; int idx = MPIC_MSI_IRQ; @@ -1657,16 +1657,16 @@ static CPUReadMemoryFunc * const mpic_msi_read[] = { &mpic_src_msi_read, }; -qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus, +qemu_irq *mpic_init (a_target_phys_addr base, int nb_cpus, qemu_irq **irqs, qemu_irq irq_out) { - openpic_t *mpp; + a_openpic *mpp; int i; struct { CPUReadMemoryFunc * const *read; CPUWriteMemoryFunc * const *write; - target_phys_addr_t start_addr; - ram_addr_t size; + a_target_phys_addr start_addr; + a_ram_addr size; } const list[] = { {mpic_glb_read, mpic_glb_write, MPIC_GLB_REG_START, MPIC_GLB_REG_SIZE}, {mpic_tmr_read, mpic_tmr_write, MPIC_TMR_REG_START, MPIC_TMR_REG_SIZE}, @@ -1681,7 +1681,7 @@ qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus, if (nb_cpus != 1) return NULL; - mpp = qemu_mallocz(sizeof(openpic_t)); + mpp = qemu_mallocz(sizeof(a_openpic)); for (i = 0; i < sizeof(list)/sizeof(list[0]); i++) { int mem_index; diff --git a/hw/openpic.h b/hw/openpic.h index 0957c1ff00..1ab010a9e2 100644 --- a/hw/openpic.h +++ b/hw/openpic.h @@ -13,6 +13,6 @@ enum { qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus, qemu_irq **irqs, qemu_irq irq_out); -qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus, +qemu_irq *mpic_init (a_target_phys_addr base, int nb_cpus, qemu_irq **irqs, qemu_irq irq_out); #endif /* __OPENPIC_H__ */ @@ -26,25 +26,25 @@ #include "devices.h" #include "loader.h" -static uint32_t static_readb(void *opaque, target_phys_addr_t offset) +static uint32_t static_readb(void *opaque, a_target_phys_addr offset) { uint32_t *val = (uint32_t *) opaque; return *val >> ((offset & 3) << 3); } -static uint32_t static_readh(void *opaque, target_phys_addr_t offset) +static uint32_t static_readh(void *opaque, a_target_phys_addr offset) { uint32_t *val = (uint32_t *) opaque; return *val >> ((offset & 1) << 3); } -static uint32_t static_readw(void *opaque, target_phys_addr_t offset) +static uint32_t static_readw(void *opaque, a_target_phys_addr offset) { uint32_t *val = (uint32_t *) opaque; return *val >> ((offset & 0) << 3); } -static void static_write(void *opaque, target_phys_addr_t offset, +static void static_write(void *opaque, a_target_phys_addr offset, uint32_t value) { #ifdef SPY @@ -193,7 +193,7 @@ static struct arm_boot_info palmte_binfo = { .board_id = 0x331, }; -static void palmte_init(ram_addr_t ram_size, +static void palmte_init(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -206,7 +206,7 @@ static void palmte_init(ram_addr_t ram_size, static uint32_t cs1val = 0x0000e1a0; static uint32_t cs2val = 0x0000e1a0; static uint32_t cs3val = 0xe1a0e1a0; - ram_addr_t phys_flash; + a_ram_addr phys_flash; int rom_size, rom_loaded = 0; DisplayState *ds = get_displaystate(); diff --git a/hw/parallel.c b/hw/parallel.c index faaaa0d9e4..12fe25bbbd 100644 --- a/hw/parallel.c +++ b/hw/parallel.c @@ -473,7 +473,7 @@ ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr) } /* Memory mapped interface */ -static uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr) +static uint32_t parallel_mm_readb (void *opaque, a_target_phys_addr addr) { ParallelState *s = opaque; @@ -481,14 +481,14 @@ static uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr) } static void parallel_mm_writeb (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { ParallelState *s = opaque; parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF); } -static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr) +static uint32_t parallel_mm_readw (void *opaque, a_target_phys_addr addr) { ParallelState *s = opaque; @@ -496,14 +496,14 @@ static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr) } static void parallel_mm_writew (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { ParallelState *s = opaque; parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF); } -static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr) +static uint32_t parallel_mm_readl (void *opaque, a_target_phys_addr addr) { ParallelState *s = opaque; @@ -511,7 +511,7 @@ static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr) } static void parallel_mm_writel (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { ParallelState *s = opaque; @@ -531,7 +531,7 @@ static CPUWriteMemoryFunc * const parallel_mm_write_sw[] = { }; /* If fd is zero, it means that the parallel device uses the console */ -ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr) +ParallelState *parallel_mm_init(a_target_phys_addr base, int it_shift, qemu_irq irq, CharDriverState *chr) { ParallelState *s; int io_sw; @@ -61,14 +61,14 @@ #define MAX_IDE_BUS 2 -static fdctrl_t *floppy_controller; +static a_fdctrl *floppy_controller; static RTCState *rtc_state; static PITState *pit; static PCII440FXState *i440fx_state; typedef struct rom_reset_data { uint8_t *data; - target_phys_addr_t addr; + a_target_phys_addr addr; unsigned size; } RomResetData; @@ -79,7 +79,7 @@ static void option_rom_reset(void *_rrd) cpu_physical_memory_write_rom(rrd->addr, rrd->data, rrd->size); } -static void option_rom_setup_reset(target_phys_addr_t addr, unsigned size) +static void option_rom_setup_reset(a_target_phys_addr addr, unsigned size) { RomResetData *rrd = qemu_malloc(sizeof *rrd); @@ -266,7 +266,7 @@ static int pc_boot_set(void *opaque, const char *boot_device) } /* hd_table must contain 4 block drivers */ -static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, +static void cmos_init(a_ram_addr ram_size, a_ram_addr above_4g_mem_size, const char *boot_device, DriveInfo **hd_table) { RTCState *s = rtc_state; @@ -515,7 +515,7 @@ static void *bochs_bios_init(void) /* Generate an initial boot sector which sets state and jump to a specified vector */ -static void generate_bootsect(target_phys_addr_t option_rom, +static void generate_bootsect(a_target_phys_addr option_rom, uint32_t gpr[8], uint16_t segs[6], uint16_t ip) { uint8_t rom[512], *p, *reloc; @@ -819,11 +819,11 @@ static int load_multiboot(void *fw_cfg, } static void load_linux(void *fw_cfg, - target_phys_addr_t option_rom, + a_target_phys_addr option_rom, const char *kernel_filename, const char *initrd_filename, const char *kernel_cmdline, - target_phys_addr_t max_ram_size) + a_target_phys_addr max_ram_size) { uint16_t protocol; uint32_t gpr[8]; @@ -832,7 +832,7 @@ static void load_linux(void *fw_cfg, int setup_size, kernel_size, initrd_size = 0, cmdline_size; uint32_t initrd_max; uint8_t header[8192]; - target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0; + a_target_phys_addr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; FILE *f, *fi; char *vmode; @@ -1058,8 +1058,8 @@ static void pc_init_ne2k_isa(NICInfo *nd) nb_ne2k++; } -static int load_option_rom(const char *oprom, target_phys_addr_t start, - target_phys_addr_t end) +static int load_option_rom(const char *oprom, a_target_phys_addr start, + a_target_phys_addr end) { int size; char *filename; @@ -1112,7 +1112,7 @@ static CPUState *pc_new_cpu(const char *cpu_model) } /* PC hardware initialisation */ -static void pc_init1(ram_addr_t ram_size, +static void pc_init1(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, @@ -1122,8 +1122,8 @@ static void pc_init1(ram_addr_t ram_size, { char *filename; int ret, linux_boot, i; - ram_addr_t ram_addr, bios_offset, option_rom_offset; - ram_addr_t below_4g_mem_size, above_4g_mem_size = 0; + a_ram_addr ram_addr, bios_offset, option_rom_offset; + a_ram_addr below_4g_mem_size, above_4g_mem_size = 0; int bios_size, isa_bios_size, oprom_area_size; PCIBus *pci_bus; ISADevice *isa_dev; @@ -1432,7 +1432,7 @@ static void pc_init1(ram_addr_t ram_size, } } -static void pc_init_pci(ram_addr_t ram_size, +static void pc_init_pci(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, @@ -1444,7 +1444,7 @@ static void pc_init_pci(ram_addr_t ram_size, initrd_filename, cpu_model, 1); } -static void pc_init_isa(ram_addr_t ram_size, +static void pc_init_isa(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, @@ -9,7 +9,7 @@ SerialState *serial_init(int base, qemu_irq irq, int baudbase, CharDriverState *chr); -SerialState *serial_mm_init (target_phys_addr_t base, int it_shift, +SerialState *serial_mm_init (a_target_phys_addr base, int it_shift, qemu_irq irq, int baudbase, CharDriverState *chr, int ioregister); @@ -17,7 +17,7 @@ SerialState *serial_mm_init (target_phys_addr_t base, int it_shift, typedef struct ParallelState ParallelState; ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr); -ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr); +ParallelState *parallel_mm_init(a_target_phys_addr base, int it_shift, qemu_irq irq, CharDriverState *chr); /* i8259.c */ @@ -74,15 +74,15 @@ void *vmmouse_init(void *m); void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base); void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, - target_phys_addr_t base, ram_addr_t size, - target_phys_addr_t mask); + a_target_phys_addr base, a_ram_addr size, + a_target_phys_addr mask); /* mc146818rtc.c */ typedef struct RTCState RTCState; RTCState *rtc_init(int base_year); -RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, +RTCState *rtc_mm_init(a_target_phys_addr base, int it_shift, qemu_irq irq, int base_year); void rtc_set_memory(RTCState *s, int addr, int val); void rtc_set_date(RTCState *s, const struct tm *tm); @@ -138,8 +138,8 @@ extern enum vga_retrace_method vga_retrace_method; int isa_vga_init(void); int pci_vga_init(PCIBus *bus, unsigned long vga_bios_offset, int vga_bios_size); -int isa_vga_mm_init(target_phys_addr_t vram_base, - target_phys_addr_t ctrl_base, int it_shift); +int isa_vga_mm_init(a_target_phys_addr vram_base, + a_target_phys_addr ctrl_base, int it_shift); /* cirrus_vga.c */ void pci_cirrus_vga_init(PCIBus *bus); @@ -66,7 +66,7 @@ static struct BusInfo pci_bus_info = { static void pci_update_mappings(PCIDevice *d); static void pci_set_irq(void *opaque, int irq_num, int level); -target_phys_addr_t pci_mem_base; +a_target_phys_addr pci_mem_base; static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; static PCIBus *first_bus; @@ -354,7 +354,7 @@ PCIDevice *pci_register_device(PCIBus *bus, const char *name, config_read, config_write); return pci_dev; } -static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr) +static a_target_phys_addr pci_to_cpu_addr(a_target_phys_addr addr) { return addr + pci_mem_base; } @@ -10,7 +10,7 @@ /* PCI bus */ -extern target_phys_addr_t pci_mem_base; +extern a_target_phys_addr pci_mem_base; #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) @@ -217,7 +217,7 @@ struct PCIDevice { * a 4K aligned region all by itself. Align it to * target pages so that drivers can do passthrough * on the rest of the region. */ - target_phys_addr_t msix_page_size; + a_target_phys_addr msix_page_size; }; PCIDevice *pci_register_device(PCIBus *bus, const char *name, @@ -354,8 +354,8 @@ void usb_ohci_init_pci(struct PCIBus *bus, int devfn); PCIBus *pci_prep_init(qemu_irq *pic); /* apb_pci.c */ -PCIBus *pci_apb_init(target_phys_addr_t special_base, - target_phys_addr_t mem_base, +PCIBus *pci_apb_init(a_target_phys_addr special_base, + a_target_phys_addr mem_base, qemu_irq *pic, PCIBus **bus2, PCIBus **bus3); /* sh_pci.c */ diff --git a/hw/pci_host.h b/hw/pci_host.h index 48862b5083..608e8c63d0 100644 --- a/hw/pci_host.h +++ b/hw/pci_host.h @@ -43,41 +43,41 @@ typedef struct { PCIBus *bus; } PCIHostState; -static void pci_host_data_writeb(void* opaque, pci_addr_t addr, uint32_t val) +static void pci_host_data_writeb(void* opaque, a_pci_addr addr, uint32_t val) { PCIHostState *s = opaque; PCI_DPRINTF("writeb addr " TARGET_FMT_plx " val %x\n", - (target_phys_addr_t)addr, val); + (a_target_phys_addr)addr, val); if (s->config_reg & (1u << 31)) pci_data_write(s->bus, s->config_reg | (addr & 3), val, 1); } -static void pci_host_data_writew(void* opaque, pci_addr_t addr, uint32_t val) +static void pci_host_data_writew(void* opaque, a_pci_addr addr, uint32_t val) { PCIHostState *s = opaque; #ifdef TARGET_WORDS_BIGENDIAN val = bswap16(val); #endif PCI_DPRINTF("writew addr " TARGET_FMT_plx " val %x\n", - (target_phys_addr_t)addr, val); + (a_target_phys_addr)addr, val); if (s->config_reg & (1u << 31)) pci_data_write(s->bus, s->config_reg | (addr & 3), val, 2); } -static void pci_host_data_writel(void* opaque, pci_addr_t addr, uint32_t val) +static void pci_host_data_writel(void* opaque, a_pci_addr addr, uint32_t val) { PCIHostState *s = opaque; #ifdef TARGET_WORDS_BIGENDIAN val = bswap32(val); #endif PCI_DPRINTF("writel addr " TARGET_FMT_plx " val %x\n", - (target_phys_addr_t)addr, val); + (a_target_phys_addr)addr, val); if (s->config_reg & (1u << 31)) pci_data_write(s->bus, s->config_reg, val, 4); } -static uint32_t pci_host_data_readb(void* opaque, pci_addr_t addr) +static uint32_t pci_host_data_readb(void* opaque, a_pci_addr addr) { PCIHostState *s = opaque; uint32_t val; @@ -86,11 +86,11 @@ static uint32_t pci_host_data_readb(void* opaque, pci_addr_t addr) return 0xff; val = pci_data_read(s->bus, s->config_reg | (addr & 3), 1); PCI_DPRINTF("readb addr " TARGET_FMT_plx " val %x\n", - (target_phys_addr_t)addr, val); + (a_target_phys_addr)addr, val); return val; } -static uint32_t pci_host_data_readw(void* opaque, pci_addr_t addr) +static uint32_t pci_host_data_readw(void* opaque, a_pci_addr addr) { PCIHostState *s = opaque; uint32_t val; @@ -98,14 +98,14 @@ static uint32_t pci_host_data_readw(void* opaque, pci_addr_t addr) return 0xffff; val = pci_data_read(s->bus, s->config_reg | (addr & 3), 2); PCI_DPRINTF("readw addr " TARGET_FMT_plx " val %x\n", - (target_phys_addr_t)addr, val); + (a_target_phys_addr)addr, val); #ifdef TARGET_WORDS_BIGENDIAN val = bswap16(val); #endif return val; } -static uint32_t pci_host_data_readl(void* opaque, pci_addr_t addr) +static uint32_t pci_host_data_readl(void* opaque, a_pci_addr addr) { PCIHostState *s = opaque; uint32_t val; @@ -113,7 +113,7 @@ static uint32_t pci_host_data_readl(void* opaque, pci_addr_t addr) return 0xffffffff; val = pci_data_read(s->bus, s->config_reg | (addr & 3), 4); PCI_DPRINTF("readl addr " TARGET_FMT_plx " val %x\n", - (target_phys_addr_t)addr, val); + (a_target_phys_addr)addr, val); #ifdef TARGET_WORDS_BIGENDIAN val = bswap32(val); #endif diff --git a/hw/pckbd.c b/hw/pckbd.c index c049047aea..57f6668bbc 100644 --- a/hw/pckbd.c +++ b/hw/pckbd.c @@ -123,7 +123,7 @@ typedef struct KBDState { qemu_irq irq_kbd; qemu_irq irq_mouse; - target_phys_addr_t mask; + a_target_phys_addr mask; } KBDState; static KBDState kbd_state; @@ -354,7 +354,7 @@ static const VMStateDescription vmstate_kbd = { }; /* Memory mapped interface */ -static uint32_t kbd_mm_readb (void *opaque, target_phys_addr_t addr) +static uint32_t kbd_mm_readb (void *opaque, a_target_phys_addr addr) { KBDState *s = opaque; @@ -364,7 +364,7 @@ static uint32_t kbd_mm_readb (void *opaque, target_phys_addr_t addr) return kbd_read_data(s, 0) & 0xff; } -static void kbd_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) +static void kbd_mm_writeb (void *opaque, a_target_phys_addr addr, uint32_t value) { KBDState *s = opaque; @@ -387,8 +387,8 @@ static CPUWriteMemoryFunc * const kbd_mm_write[] = { }; void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, - target_phys_addr_t base, ram_addr_t size, - target_phys_addr_t mask) + a_target_phys_addr base, a_ram_addr size, + a_target_phys_addr mask) { KBDState *s = &kbd_state; int s_io_memory; diff --git a/hw/pcnet.c b/hw/pcnet.c index ae98a201dc..c9d823da26 100644 --- a/hw/pcnet.c +++ b/hw/pcnet.c @@ -73,9 +73,9 @@ struct PCNetState_st { uint8_t buffer[4096]; int tx_busy; qemu_irq irq; - void (*phys_mem_read)(void *dma_opaque, target_phys_addr_t addr, + void (*phys_mem_read)(void *dma_opaque, a_target_phys_addr addr, uint8_t *buf, int len, int do_bswap); - void (*phys_mem_write)(void *dma_opaque, target_phys_addr_t addr, + void (*phys_mem_write)(void *dma_opaque, a_target_phys_addr addr, uint8_t *buf, int len, int do_bswap); void *dma_opaque; int looptest; @@ -349,7 +349,7 @@ struct pcnet_RMD { GET_FIELD((R)->msg_length, RMDM, ZEROS)) static inline void pcnet_tmd_load(PCNetState *s, struct pcnet_TMD *tmd, - target_phys_addr_t addr) + a_target_phys_addr addr) { if (!BCR_SSIZE32(s)) { struct { @@ -379,7 +379,7 @@ static inline void pcnet_tmd_load(PCNetState *s, struct pcnet_TMD *tmd, } static inline void pcnet_tmd_store(PCNetState *s, const struct pcnet_TMD *tmd, - target_phys_addr_t addr) + a_target_phys_addr addr) { if (!BCR_SSIZE32(s)) { struct { @@ -415,7 +415,7 @@ static inline void pcnet_tmd_store(PCNetState *s, const struct pcnet_TMD *tmd, } static inline void pcnet_rmd_load(PCNetState *s, struct pcnet_RMD *rmd, - target_phys_addr_t addr) + a_target_phys_addr addr) { if (!BCR_SSIZE32(s)) { struct { @@ -445,7 +445,7 @@ static inline void pcnet_rmd_load(PCNetState *s, struct pcnet_RMD *rmd, } static inline void pcnet_rmd_store(PCNetState *s, struct pcnet_RMD *rmd, - target_phys_addr_t addr) + a_target_phys_addr addr) { if (!BCR_SSIZE32(s)) { struct { @@ -716,7 +716,7 @@ static inline int ladr_match(PCNetState *s, const uint8_t *buf, int size) return 0; } -static inline target_phys_addr_t pcnet_rdra_addr(PCNetState *s, int idx) +static inline a_target_phys_addr pcnet_rdra_addr(PCNetState *s, int idx) { while (idx < 1) idx += CSR_RCVRL(s); return s->rdra + ((CSR_RCVRL(s) - idx) * (BCR_SWSTYLE(s) ? 16 : 8)); @@ -955,19 +955,19 @@ static void pcnet_rdte_poll(PCNetState *s) if (s->rdra) { int bad = 0; #if 1 - target_phys_addr_t crda = pcnet_rdra_addr(s, CSR_RCVRC(s)); - target_phys_addr_t nrda = pcnet_rdra_addr(s, -1 + CSR_RCVRC(s)); - target_phys_addr_t nnrd = pcnet_rdra_addr(s, -2 + CSR_RCVRC(s)); + a_target_phys_addr crda = pcnet_rdra_addr(s, CSR_RCVRC(s)); + a_target_phys_addr nrda = pcnet_rdra_addr(s, -1 + CSR_RCVRC(s)); + a_target_phys_addr nnrd = pcnet_rdra_addr(s, -2 + CSR_RCVRC(s)); #else - target_phys_addr_t crda = s->rdra + + a_target_phys_addr crda = s->rdra + (CSR_RCVRL(s) - CSR_RCVRC(s)) * (BCR_SWSTYLE(s) ? 16 : 8 ); int nrdc = CSR_RCVRC(s)<=1 ? CSR_RCVRL(s) : CSR_RCVRC(s)-1; - target_phys_addr_t nrda = s->rdra + + a_target_phys_addr nrda = s->rdra + (CSR_RCVRL(s) - nrdc) * (BCR_SWSTYLE(s) ? 16 : 8 ); int nnrc = nrdc<=1 ? CSR_RCVRL(s) : nrdc-1; - target_phys_addr_t nnrd = s->rdra + + a_target_phys_addr nnrd = s->rdra + (CSR_RCVRL(s) - nnrc) * (BCR_SWSTYLE(s) ? 16 : 8 ); #endif @@ -1027,7 +1027,7 @@ static int pcnet_tdte_poll(PCNetState *s) { s->csr[34] = s->csr[35] = 0; if (s->tdra) { - target_phys_addr_t cxda = s->tdra + + a_target_phys_addr cxda = s->tdra + (CSR_XMTRL(s) - CSR_XMTRC(s)) * (BCR_SWSTYLE(s) ? 16 : 8); int bad = 0; @@ -1109,7 +1109,7 @@ static ssize_t pcnet_receive(VLANClientState *vc, const uint8_t *buf, size_t siz if (!(CSR_CRST(s) & 0x8000) && s->rdra) { struct pcnet_RMD rmd; int rcvrc = CSR_RCVRC(s)-1,i; - target_phys_addr_t nrda; + a_target_phys_addr nrda; for (i = CSR_RCVRL(s)-1; i > 0; i--, rcvrc--) { if (rcvrc <= 1) rcvrc = CSR_RCVRL(s); @@ -1137,7 +1137,7 @@ static ssize_t pcnet_receive(VLANClientState *vc, const uint8_t *buf, size_t siz CSR_MISSC(s)++; } else { uint8_t *src = s->buffer; - target_phys_addr_t crda = CSR_CRDA(s); + a_target_phys_addr crda = CSR_CRDA(s); struct pcnet_RMD rmd; int pktcount = 0; @@ -1177,7 +1177,7 @@ static ssize_t pcnet_receive(VLANClientState *vc, const uint8_t *buf, size_t siz #define PCNET_RECV_STORE() do { \ int count = MIN(4096 - GET_FIELD(rmd.buf_length, RMDL, BCNT),remaining); \ - target_phys_addr_t rbadr = PHYSADDR(s, rmd.rbadr); \ + a_target_phys_addr rbadr = PHYSADDR(s, rmd.rbadr); \ s->phys_mem_write(s->dma_opaque, rbadr, src, count, CSR_BSWP(s)); \ src += count; remaining -= count; \ SET_FIELD(&rmd.status, RMDS, OWN, 0); \ @@ -1188,7 +1188,7 @@ static ssize_t pcnet_receive(VLANClientState *vc, const uint8_t *buf, size_t siz remaining = size; PCNET_RECV_STORE(); if ((remaining > 0) && CSR_NRDA(s)) { - target_phys_addr_t nrda = CSR_NRDA(s); + a_target_phys_addr nrda = CSR_NRDA(s); #ifdef PCNET_DEBUG_RMD PRINT_RMD(&rmd); #endif @@ -1258,7 +1258,7 @@ static ssize_t pcnet_receive(VLANClientState *vc, const uint8_t *buf, size_t siz static void pcnet_transmit(PCNetState *s) { - target_phys_addr_t xmit_cxda = 0; + a_target_phys_addr xmit_cxda = 0; int count = CSR_XMTRL(s)-1; int add_crc = 0; @@ -1778,7 +1778,7 @@ static void pcnet_ioport_map(PCIDevice *pci_dev, int region_num, register_ioport_read(addr + 0x10, 0x10, 4, pcnet_ioport_readl, d); } -static void pcnet_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) +static void pcnet_mmio_writeb(void *opaque, a_target_phys_addr addr, uint32_t val) { PCNetState *d = opaque; #ifdef PCNET_DEBUG_IO @@ -1789,7 +1789,7 @@ static void pcnet_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t va pcnet_aprom_writeb(d, addr & 0x0f, val); } -static uint32_t pcnet_mmio_readb(void *opaque, target_phys_addr_t addr) +static uint32_t pcnet_mmio_readb(void *opaque, a_target_phys_addr addr) { PCNetState *d = opaque; uint32_t val = -1; @@ -1802,7 +1802,7 @@ static uint32_t pcnet_mmio_readb(void *opaque, target_phys_addr_t addr) return val; } -static void pcnet_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) +static void pcnet_mmio_writew(void *opaque, a_target_phys_addr addr, uint32_t val) { PCNetState *d = opaque; #ifdef PCNET_DEBUG_IO @@ -1818,7 +1818,7 @@ static void pcnet_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t va } } -static uint32_t pcnet_mmio_readw(void *opaque, target_phys_addr_t addr) +static uint32_t pcnet_mmio_readw(void *opaque, a_target_phys_addr addr) { PCNetState *d = opaque; uint32_t val = -1; @@ -1837,7 +1837,7 @@ static uint32_t pcnet_mmio_readw(void *opaque, target_phys_addr_t addr) return val; } -static void pcnet_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) +static void pcnet_mmio_writel(void *opaque, a_target_phys_addr addr, uint32_t val) { PCNetState *d = opaque; #ifdef PCNET_DEBUG_IO @@ -1855,7 +1855,7 @@ static void pcnet_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t va } } -static uint32_t pcnet_mmio_readl(void *opaque, target_phys_addr_t addr) +static uint32_t pcnet_mmio_readl(void *opaque, a_target_phys_addr addr) { PCNetState *d = opaque; uint32_t val; @@ -2000,13 +2000,13 @@ static void pcnet_mmio_map(PCIDevice *pci_dev, int region_num, cpu_register_physical_memory(addr, PCNET_PNPMMIO_SIZE, d->state.mmio_index); } -static void pci_physical_memory_write(void *dma_opaque, target_phys_addr_t addr, +static void pci_physical_memory_write(void *dma_opaque, a_target_phys_addr addr, uint8_t *buf, int len, int do_bswap) { cpu_physical_memory_write(addr, buf, len); } -static void pci_physical_memory_read(void *dma_opaque, target_phys_addr_t addr, +static void pci_physical_memory_read(void *dma_opaque, a_target_phys_addr addr, uint8_t *buf, int len, int do_bswap) { cpu_physical_memory_read(addr, buf, len); @@ -2089,7 +2089,7 @@ static void parent_lance_reset(void *opaque, int irq, int level) pcnet_h_reset(&d->state); } -static void lance_mem_writew(void *opaque, target_phys_addr_t addr, +static void lance_mem_writew(void *opaque, a_target_phys_addr addr, uint32_t val) { SysBusPCNetState *d = opaque; @@ -2100,7 +2100,7 @@ static void lance_mem_writew(void *opaque, target_phys_addr_t addr, pcnet_ioport_writew(&d->state, addr, val & 0xffff); } -static uint32_t lance_mem_readw(void *opaque, target_phys_addr_t addr) +static uint32_t lance_mem_readw(void *opaque, a_target_phys_addr addr) { SysBusPCNetState *d = opaque; uint32_t val; diff --git a/hw/petalogix_s3adsp1800_mmu.c b/hw/petalogix_s3adsp1800_mmu.c index f343dbf7b8..0ff0ade0b3 100644 --- a/hw/petalogix_s3adsp1800_mmu.c +++ b/hw/petalogix_s3adsp1800_mmu.c @@ -48,10 +48,10 @@ static void main_cpu_reset(void *opaque) } #define BINARY_DEVICE_TREE_FILE "petalogix-s3adsp1800.dtb" -static int petalogix_load_device_tree(target_phys_addr_t addr, +static int petalogix_load_device_tree(a_target_phys_addr addr, uint32_t ramsize, - target_phys_addr_t initrd_base, - target_phys_addr_t initrd_size, + a_target_phys_addr initrd_base, + a_target_phys_addr initrd_size, const char *kernel_cmdline) { char *path; @@ -97,7 +97,7 @@ static int petalogix_load_device_tree(target_phys_addr_t addr, } static void -petalogix_s3adsp1800_init(ram_addr_t ram_size, +petalogix_s3adsp1800_init(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, @@ -108,10 +108,10 @@ petalogix_s3adsp1800_init(ram_addr_t ram_size, int kernel_size; DriveInfo *dinfo; int i; - target_phys_addr_t ddr_base = 0x90000000; - ram_addr_t phys_lmb_bram; - ram_addr_t phys_ram; - ram_addr_t phys_flash; + a_target_phys_addr ddr_base = 0x90000000; + a_ram_addr phys_lmb_bram; + a_ram_addr phys_ram; + a_ram_addr phys_flash; qemu_irq irq[32], *cpu_irq; /* init CPUs */ diff --git a/hw/pflash_cfi01.c b/hw/pflash_cfi01.c index dfdced97b0..b45f0c20e4 100644 --- a/hw/pflash_cfi01.c +++ b/hw/pflash_cfi01.c @@ -57,11 +57,11 @@ do { \ #define DPRINTF(fmt, ...) do { } while (0) #endif -struct pflash_t { +struct pflash { BlockDriverState *bs; - target_phys_addr_t base; - target_phys_addr_t sector_len; - target_phys_addr_t total_len; + a_target_phys_addr base; + a_target_phys_addr sector_len; + a_target_phys_addr total_len; int width; int wcycle; /* if 0, the flash is read normally */ int bypass; @@ -71,16 +71,16 @@ struct pflash_t { uint16_t ident[4]; uint8_t cfi_len; uint8_t cfi_table[0x52]; - target_phys_addr_t counter; + a_target_phys_addr counter; QEMUTimer *timer; - ram_addr_t off; + a_ram_addr off; int fl_mem; void *storage; }; static void pflash_timer (void *opaque) { - pflash_t *pfl = opaque; + a_pflash *pfl = opaque; DPRINTF("%s: command %02x done\n", __func__, pfl->cmd); /* Reset flash */ @@ -95,10 +95,10 @@ static void pflash_timer (void *opaque) pfl->cmd = 0; } -static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset, +static uint32_t pflash_read (a_pflash *pfl, a_target_phys_addr offset, int width) { - target_phys_addr_t boff; + a_target_phys_addr boff; uint32_t ret; uint8_t *p; @@ -181,7 +181,7 @@ static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset, } /* update flash content on disk */ -static void pflash_update(pflash_t *pfl, int offset, +static void pflash_update(a_pflash *pfl, int offset, int size) { int offset_end; @@ -195,7 +195,7 @@ static void pflash_update(pflash_t *pfl, int offset, } } -static inline void pflash_data_write(pflash_t *pfl, target_phys_addr_t offset, +static inline void pflash_data_write(a_pflash *pfl, a_target_phys_addr offset, uint32_t value, int width) { uint8_t *p = pfl->storage; @@ -236,10 +236,10 @@ static inline void pflash_data_write(pflash_t *pfl, target_phys_addr_t offset, } -static void pflash_write(pflash_t *pfl, target_phys_addr_t offset, +static void pflash_write(a_pflash *pfl, a_target_phys_addr offset, uint32_t value, int width) { - target_phys_addr_t boff; + a_target_phys_addr boff; uint8_t *p; uint8_t cmd; @@ -413,43 +413,43 @@ static void pflash_write(pflash_t *pfl, target_phys_addr_t offset, } -static uint32_t pflash_readb (void *opaque, target_phys_addr_t addr) +static uint32_t pflash_readb (void *opaque, a_target_phys_addr addr) { return pflash_read(opaque, addr, 1); } -static uint32_t pflash_readw (void *opaque, target_phys_addr_t addr) +static uint32_t pflash_readw (void *opaque, a_target_phys_addr addr) { - pflash_t *pfl = opaque; + a_pflash *pfl = opaque; return pflash_read(pfl, addr, 2); } -static uint32_t pflash_readl (void *opaque, target_phys_addr_t addr) +static uint32_t pflash_readl (void *opaque, a_target_phys_addr addr) { - pflash_t *pfl = opaque; + a_pflash *pfl = opaque; return pflash_read(pfl, addr, 4); } -static void pflash_writeb (void *opaque, target_phys_addr_t addr, +static void pflash_writeb (void *opaque, a_target_phys_addr addr, uint32_t value) { pflash_write(opaque, addr, value, 1); } -static void pflash_writew (void *opaque, target_phys_addr_t addr, +static void pflash_writew (void *opaque, a_target_phys_addr addr, uint32_t value) { - pflash_t *pfl = opaque; + a_pflash *pfl = opaque; pflash_write(pfl, addr, value, 2); } -static void pflash_writel (void *opaque, target_phys_addr_t addr, +static void pflash_writel (void *opaque, a_target_phys_addr addr, uint32_t value) { - pflash_t *pfl = opaque; + a_pflash *pfl = opaque; pflash_write(pfl, addr, value, 4); } @@ -500,14 +500,14 @@ static int ctz32 (uint32_t n) return ret; } -pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off, +a_pflash *pflash_cfi01_register(a_target_phys_addr base, a_ram_addr off, BlockDriverState *bs, uint32_t sector_len, int nb_blocs, int width, uint16_t id0, uint16_t id1, uint16_t id2, uint16_t id3) { - pflash_t *pfl; - target_phys_addr_t total_len; + a_pflash *pfl; + a_target_phys_addr total_len; int ret; total_len = sector_len * nb_blocs; @@ -519,7 +519,7 @@ pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off, return NULL; #endif - pfl = qemu_mallocz(sizeof(pflash_t)); + pfl = qemu_mallocz(sizeof(a_pflash)); /* FIXME: Allocate ram ourselves. */ pfl->storage = qemu_get_ram_ptr(off); diff --git a/hw/pflash_cfi02.c b/hw/pflash_cfi02.c index 135c850797..2836a897c5 100644 --- a/hw/pflash_cfi02.c +++ b/hw/pflash_cfi02.c @@ -50,9 +50,9 @@ do { \ #define DPRINTF(fmt, ...) do { } while (0) #endif -struct pflash_t { +struct pflash { BlockDriverState *bs; - target_phys_addr_t base; + a_target_phys_addr base; uint32_t sector_len; uint32_t chip_len; int mappings; @@ -67,13 +67,13 @@ struct pflash_t { uint8_t cfi_len; uint8_t cfi_table[0x52]; QEMUTimer *timer; - ram_addr_t off; + a_ram_addr off; int fl_mem; int rom_mode; void *storage; }; -static void pflash_register_memory(pflash_t *pfl, int rom_mode) +static void pflash_register_memory(a_pflash *pfl, int rom_mode) { unsigned long phys_offset = pfl->fl_mem; int i; @@ -89,7 +89,7 @@ static void pflash_register_memory(pflash_t *pfl, int rom_mode) static void pflash_timer (void *opaque) { - pflash_t *pfl = opaque; + a_pflash *pfl = opaque; DPRINTF("%s: command %02x done\n", __func__, pfl->cmd); /* Reset flash */ @@ -103,7 +103,7 @@ static void pflash_timer (void *opaque) pfl->cmd = 0; } -static uint32_t pflash_read (pflash_t *pfl, uint32_t offset, int width) +static uint32_t pflash_read (a_pflash *pfl, uint32_t offset, int width) { uint32_t boff; uint32_t ret; @@ -208,7 +208,7 @@ static uint32_t pflash_read (pflash_t *pfl, uint32_t offset, int width) } /* update flash content on disk */ -static void pflash_update(pflash_t *pfl, int offset, +static void pflash_update(a_pflash *pfl, int offset, int size) { int offset_end; @@ -222,7 +222,7 @@ static void pflash_update(pflash_t *pfl, int offset, } } -static void pflash_write (pflash_t *pfl, uint32_t offset, uint32_t value, +static void pflash_write (a_pflash *pfl, uint32_t offset, uint32_t value, int width) { uint32_t boff; @@ -451,43 +451,43 @@ static void pflash_write (pflash_t *pfl, uint32_t offset, uint32_t value, } -static uint32_t pflash_readb (void *opaque, target_phys_addr_t addr) +static uint32_t pflash_readb (void *opaque, a_target_phys_addr addr) { return pflash_read(opaque, addr, 1); } -static uint32_t pflash_readw (void *opaque, target_phys_addr_t addr) +static uint32_t pflash_readw (void *opaque, a_target_phys_addr addr) { - pflash_t *pfl = opaque; + a_pflash *pfl = opaque; return pflash_read(pfl, addr, 2); } -static uint32_t pflash_readl (void *opaque, target_phys_addr_t addr) +static uint32_t pflash_readl (void *opaque, a_target_phys_addr addr) { - pflash_t *pfl = opaque; + a_pflash *pfl = opaque; return pflash_read(pfl, addr, 4); } -static void pflash_writeb (void *opaque, target_phys_addr_t addr, +static void pflash_writeb (void *opaque, a_target_phys_addr addr, uint32_t value) { pflash_write(opaque, addr, value, 1); } -static void pflash_writew (void *opaque, target_phys_addr_t addr, +static void pflash_writew (void *opaque, a_target_phys_addr addr, uint32_t value) { - pflash_t *pfl = opaque; + a_pflash *pfl = opaque; pflash_write(pfl, addr, value, 2); } -static void pflash_writel (void *opaque, target_phys_addr_t addr, +static void pflash_writel (void *opaque, a_target_phys_addr addr, uint32_t value) { - pflash_t *pfl = opaque; + a_pflash *pfl = opaque; pflash_write(pfl, addr, value, 4); } @@ -538,14 +538,14 @@ static int ctz32 (uint32_t n) return ret; } -pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off, +a_pflash *pflash_cfi02_register(a_target_phys_addr base, a_ram_addr off, BlockDriverState *bs, uint32_t sector_len, int nb_blocs, int nb_mappings, int width, uint16_t id0, uint16_t id1, uint16_t id2, uint16_t id3, uint16_t unlock_addr0, uint16_t unlock_addr1) { - pflash_t *pfl; + a_pflash *pfl; int32_t chip_len; int ret; @@ -556,7 +556,7 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off, total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024)) return NULL; #endif - pfl = qemu_mallocz(sizeof(pflash_t)); + pfl = qemu_mallocz(sizeof(a_pflash)); /* FIXME: Allocate ram ourselves. */ pfl->storage = qemu_get_ram_ptr(off); pfl->fl_mem = cpu_register_io_memory(pflash_read_ops, pflash_write_ops, diff --git a/hw/piix_pci.c b/hw/piix_pci.c index edd6df07e3..ef313ce324 100644 --- a/hw/piix_pci.c +++ b/hw/piix_pci.c @@ -28,7 +28,7 @@ #include "isa.h" #include "sysbus.h" -typedef uint32_t pci_addr_t; +typedef uint32_t a_pci_addr; #include "pci_host.h" typedef PCIHostState I440FXState; @@ -45,7 +45,7 @@ typedef struct PIIX3IrqState { struct PCII440FXState { PCIDevice dev; - target_phys_addr_t isa_page_descs[384 / 4]; + a_target_phys_addr isa_page_descs[384 / 4]; uint8_t smm_enabled; PIIX3IrqState *irq_state; }; diff --git a/hw/pl011.c b/hw/pl011.c index 81de91e4c4..14c00eb00a 100644 --- a/hw/pl011.c +++ b/hw/pl011.c @@ -53,7 +53,7 @@ static void pl011_update(pl011_state *s) qemu_set_irq(s->irq, flags != 0); } -static uint32_t pl011_read(void *opaque, target_phys_addr_t offset) +static uint32_t pl011_read(void *opaque, a_target_phys_addr offset) { pl011_state *s = (pl011_state *)opaque; uint32_t c; @@ -122,7 +122,7 @@ static void pl011_set_read_trigger(pl011_state *s) s->read_trigger = 1; } -static void pl011_write(void *opaque, target_phys_addr_t offset, +static void pl011_write(void *opaque, a_target_phys_addr offset, uint32_t value) { pl011_state *s = (pl011_state *)opaque; diff --git a/hw/pl022.c b/hw/pl022.c index c2e2ddafef..0cb3f3bce4 100644 --- a/hw/pl022.c +++ b/hw/pl022.c @@ -130,7 +130,7 @@ static void pl022_xfer(pl022_state *s) pl022_update(s); } -static uint32_t pl022_read(void *opaque, target_phys_addr_t offset) +static uint32_t pl022_read(void *opaque, a_target_phys_addr offset) { pl022_state *s = (pl022_state *)opaque; int val; @@ -172,7 +172,7 @@ static uint32_t pl022_read(void *opaque, target_phys_addr_t offset) } } -static void pl022_write(void *opaque, target_phys_addr_t offset, +static void pl022_write(void *opaque, a_target_phys_addr offset, uint32_t value) { pl022_state *s = (pl022_state *)opaque; diff --git a/hw/pl031.c b/hw/pl031.c index 45b7032c50..8077187356 100644 --- a/hw/pl031.c +++ b/hw/pl031.c @@ -90,7 +90,7 @@ static void pl031_set_alarm(pl031_state *s) } } -static uint32_t pl031_read(void *opaque, target_phys_addr_t offset) +static uint32_t pl031_read(void *opaque, a_target_phys_addr offset) { pl031_state *s = (pl031_state *)opaque; @@ -125,7 +125,7 @@ static uint32_t pl031_read(void *opaque, target_phys_addr_t offset) return 0; } -static void pl031_write(void * opaque, target_phys_addr_t offset, +static void pl031_write(void * opaque, a_target_phys_addr offset, uint32_t value) { pl031_state *s = (pl031_state *)opaque; diff --git a/hw/pl050.c b/hw/pl050.c index a47786cb0a..c89456fa78 100644 --- a/hw/pl050.c +++ b/hw/pl050.c @@ -43,7 +43,7 @@ static void pl050_update(void *opaque, int level) qemu_set_irq(s->irq, raise); } -static uint32_t pl050_read(void *opaque, target_phys_addr_t offset) +static uint32_t pl050_read(void *opaque, a_target_phys_addr offset) { pl050_state *s = (pl050_state *)opaque; if (offset >= 0xfe0 && offset < 0x1000) @@ -84,7 +84,7 @@ static uint32_t pl050_read(void *opaque, target_phys_addr_t offset) } } -static void pl050_write(void *opaque, target_phys_addr_t offset, +static void pl050_write(void *opaque, a_target_phys_addr offset, uint32_t value) { pl050_state *s = (pl050_state *)opaque; diff --git a/hw/pl061.c b/hw/pl061.c index 7b1b636e9b..3cea71d9c3 100644 --- a/hw/pl061.c +++ b/hw/pl061.c @@ -78,7 +78,7 @@ static void pl061_update(pl061_state *s) /* FIXME: Implement input interrupts. */ } -static uint32_t pl061_read(void *opaque, target_phys_addr_t offset) +static uint32_t pl061_read(void *opaque, a_target_phys_addr offset) { pl061_state *s = (pl061_state *)opaque; @@ -131,7 +131,7 @@ static uint32_t pl061_read(void *opaque, target_phys_addr_t offset) } } -static void pl061_write(void *opaque, target_phys_addr_t offset, +static void pl061_write(void *opaque, a_target_phys_addr offset, uint32_t value) { pl061_state *s = (pl061_state *)opaque; diff --git a/hw/pl080.c b/hw/pl080.c index 2df65fab94..4abc319a64 100644 --- a/hw/pl080.c +++ b/hw/pl080.c @@ -180,7 +180,7 @@ again: } } -static uint32_t pl080_read(void *opaque, target_phys_addr_t offset) +static uint32_t pl080_read(void *opaque, a_target_phys_addr offset) { pl080_state *s = (pl080_state *)opaque; uint32_t i; @@ -247,7 +247,7 @@ static uint32_t pl080_read(void *opaque, target_phys_addr_t offset) } } -static void pl080_write(void *opaque, target_phys_addr_t offset, +static void pl080_write(void *opaque, a_target_phys_addr offset, uint32_t value) { pl080_state *s = (pl080_state *)opaque; diff --git a/hw/pl110.c b/hw/pl110.c index 173458a7cd..41ae88db20 100644 --- a/hw/pl110.c +++ b/hw/pl110.c @@ -226,7 +226,7 @@ static void pl110_update(pl110_state *s) /* TODO: Implement interrupts. */ } -static uint32_t pl110_read(void *opaque, target_phys_addr_t offset) +static uint32_t pl110_read(void *opaque, a_target_phys_addr offset) { pl110_state *s = (pl110_state *)opaque; @@ -275,7 +275,7 @@ static uint32_t pl110_read(void *opaque, target_phys_addr_t offset) } } -static void pl110_write(void *opaque, target_phys_addr_t offset, +static void pl110_write(void *opaque, a_target_phys_addr offset, uint32_t val) { pl110_state *s = (pl110_state *)opaque; diff --git a/hw/pl181.c b/hw/pl181.c index 7282053053..d92bad6eba 100644 --- a/hw/pl181.c +++ b/hw/pl181.c @@ -256,7 +256,7 @@ static void pl181_fifo_run(pl181_state *s) } } -static uint32_t pl181_read(void *opaque, target_phys_addr_t offset) +static uint32_t pl181_read(void *opaque, a_target_phys_addr offset) { pl181_state *s = (pl181_state *)opaque; uint32_t tmp; @@ -338,7 +338,7 @@ static uint32_t pl181_read(void *opaque, target_phys_addr_t offset) } } -static void pl181_write(void *opaque, target_phys_addr_t offset, +static void pl181_write(void *opaque, a_target_phys_addr offset, uint32_t value) { pl181_state *s = (pl181_state *)opaque; diff --git a/hw/pl190.c b/hw/pl190.c index a4bc9c15e1..1e8ab9ee25 100644 --- a/hw/pl190.c +++ b/hw/pl190.c @@ -85,7 +85,7 @@ static void pl190_update_vectors(pl190_state *s) pl190_update(s); } -static uint32_t pl190_read(void *opaque, target_phys_addr_t offset) +static uint32_t pl190_read(void *opaque, a_target_phys_addr offset) { pl190_state *s = (pl190_state *)opaque; int i; @@ -141,7 +141,7 @@ static uint32_t pl190_read(void *opaque, target_phys_addr_t offset) } } -static void pl190_write(void *opaque, target_phys_addr_t offset, uint32_t val) +static void pl190_write(void *opaque, a_target_phys_addr offset, uint32_t val) { pl190_state *s = (pl190_state *)opaque; @@ -377,7 +377,7 @@ void ppce500_irq_init (CPUState *env) } /*****************************************************************************/ /* PowerPC time base and decrementer emulation */ -struct ppc_tb_t { +struct ppc_tb { /* Time base management */ int64_t tb_offset; /* Compensation */ int64_t atb_offset; /* Compensation */ @@ -394,7 +394,7 @@ struct ppc_tb_t { void *opaque; }; -static inline uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, +static inline uint64_t cpu_ppc_get_tb(a_ppc_tb *tb_env, uint64_t vmclk, int64_t tb_offset) { /* TB time in tb periods */ @@ -403,7 +403,7 @@ static inline uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, uint32_t cpu_ppc_load_tbl (CPUState *env) { - ppc_tb_t *tb_env = env->tb_env; + a_ppc_tb *tb_env = env->tb_env; uint64_t tb; tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); @@ -414,7 +414,7 @@ uint32_t cpu_ppc_load_tbl (CPUState *env) static inline uint32_t _cpu_ppc_load_tbu(CPUState *env) { - ppc_tb_t *tb_env = env->tb_env; + a_ppc_tb *tb_env = env->tb_env; uint64_t tb; tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); @@ -428,7 +428,7 @@ uint32_t cpu_ppc_load_tbu (CPUState *env) return _cpu_ppc_load_tbu(env); } -static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk, +static inline void cpu_ppc_store_tb(a_ppc_tb *tb_env, uint64_t vmclk, int64_t *tb_offsetp, uint64_t value) { *tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec()); @@ -438,7 +438,7 @@ static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk, void cpu_ppc_store_tbl (CPUState *env, uint32_t value) { - ppc_tb_t *tb_env = env->tb_env; + a_ppc_tb *tb_env = env->tb_env; uint64_t tb; tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); @@ -449,7 +449,7 @@ void cpu_ppc_store_tbl (CPUState *env, uint32_t value) static inline void _cpu_ppc_store_tbu(CPUState *env, uint32_t value) { - ppc_tb_t *tb_env = env->tb_env; + a_ppc_tb *tb_env = env->tb_env; uint64_t tb; tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); @@ -465,7 +465,7 @@ void cpu_ppc_store_tbu (CPUState *env, uint32_t value) uint32_t cpu_ppc_load_atbl (CPUState *env) { - ppc_tb_t *tb_env = env->tb_env; + a_ppc_tb *tb_env = env->tb_env; uint64_t tb; tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); @@ -476,7 +476,7 @@ uint32_t cpu_ppc_load_atbl (CPUState *env) uint32_t cpu_ppc_load_atbu (CPUState *env) { - ppc_tb_t *tb_env = env->tb_env; + a_ppc_tb *tb_env = env->tb_env; uint64_t tb; tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); @@ -487,7 +487,7 @@ uint32_t cpu_ppc_load_atbu (CPUState *env) void cpu_ppc_store_atbl (CPUState *env, uint32_t value) { - ppc_tb_t *tb_env = env->tb_env; + a_ppc_tb *tb_env = env->tb_env; uint64_t tb; tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); @@ -498,7 +498,7 @@ void cpu_ppc_store_atbl (CPUState *env, uint32_t value) void cpu_ppc_store_atbu (CPUState *env, uint32_t value) { - ppc_tb_t *tb_env = env->tb_env; + a_ppc_tb *tb_env = env->tb_env; uint64_t tb; tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); @@ -509,7 +509,7 @@ void cpu_ppc_store_atbu (CPUState *env, uint32_t value) static void cpu_ppc_tb_stop (CPUState *env) { - ppc_tb_t *tb_env = env->tb_env; + a_ppc_tb *tb_env = env->tb_env; uint64_t tb, atb, vmclk; /* If the time base is already frozen, do nothing */ @@ -531,7 +531,7 @@ static void cpu_ppc_tb_stop (CPUState *env) static void cpu_ppc_tb_start (CPUState *env) { - ppc_tb_t *tb_env = env->tb_env; + a_ppc_tb *tb_env = env->tb_env; uint64_t tb, atb, vmclk; /* If the time base is not frozen, do nothing */ @@ -552,7 +552,7 @@ static void cpu_ppc_tb_start (CPUState *env) static inline uint32_t _cpu_ppc_load_decr(CPUState *env, uint64_t next) { - ppc_tb_t *tb_env = env->tb_env; + a_ppc_tb *tb_env = env->tb_env; uint32_t decr; int64_t diff; @@ -568,21 +568,21 @@ static inline uint32_t _cpu_ppc_load_decr(CPUState *env, uint64_t next) uint32_t cpu_ppc_load_decr (CPUState *env) { - ppc_tb_t *tb_env = env->tb_env; + a_ppc_tb *tb_env = env->tb_env; return _cpu_ppc_load_decr(env, tb_env->decr_next); } uint32_t cpu_ppc_load_hdecr (CPUState *env) { - ppc_tb_t *tb_env = env->tb_env; + a_ppc_tb *tb_env = env->tb_env; return _cpu_ppc_load_decr(env, tb_env->hdecr_next); } uint64_t cpu_ppc_load_purr (CPUState *env) { - ppc_tb_t *tb_env = env->tb_env; + a_ppc_tb *tb_env = env->tb_env; uint64_t diff; diff = qemu_get_clock(vm_clock) - tb_env->purr_start; @@ -613,7 +613,7 @@ static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp, uint32_t decr, uint32_t value, int is_excp) { - ppc_tb_t *tb_env = env->tb_env; + a_ppc_tb *tb_env = env->tb_env; uint64_t now, next; LOG_TB("%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__, @@ -637,7 +637,7 @@ static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp, static inline void _cpu_ppc_store_decr(CPUState *env, uint32_t decr, uint32_t value, int is_excp) { - ppc_tb_t *tb_env = env->tb_env; + a_ppc_tb *tb_env = env->tb_env; __cpu_ppc_store_decr(env, &tb_env->decr_next, tb_env->decr_timer, &cpu_ppc_decr_excp, decr, value, is_excp); @@ -656,7 +656,7 @@ static void cpu_ppc_decr_cb (void *opaque) static inline void _cpu_ppc_store_hdecr(CPUState *env, uint32_t hdecr, uint32_t value, int is_excp) { - ppc_tb_t *tb_env = env->tb_env; + a_ppc_tb *tb_env = env->tb_env; if (tb_env->hdecr_timer != NULL) { __cpu_ppc_store_decr(env, &tb_env->hdecr_next, tb_env->hdecr_timer, @@ -676,7 +676,7 @@ static void cpu_ppc_hdecr_cb (void *opaque) void cpu_ppc_store_purr (CPUState *env, uint64_t value) { - ppc_tb_t *tb_env = env->tb_env; + a_ppc_tb *tb_env = env->tb_env; tb_env->purr_load = value; tb_env->purr_start = qemu_get_clock(vm_clock); @@ -685,7 +685,7 @@ void cpu_ppc_store_purr (CPUState *env, uint64_t value) static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq) { CPUState *env = opaque; - ppc_tb_t *tb_env = env->tb_env; + a_ppc_tb *tb_env = env->tb_env; tb_env->tb_freq = freq; tb_env->decr_freq = freq; @@ -701,9 +701,9 @@ static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq) /* Set up (once) timebase frequency (in Hz) */ clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq) { - ppc_tb_t *tb_env; + a_ppc_tb *tb_env; - tb_env = qemu_mallocz(sizeof(ppc_tb_t)); + tb_env = qemu_mallocz(sizeof(a_ppc_tb)); env->tb_env = tb_env; /* Create new timer */ tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env); @@ -751,8 +751,8 @@ uint32_t cpu_ppc601_load_rtcl (CPUState *env) /* Embedded PowerPC timers */ /* PIT, FIT & WDT */ -typedef struct ppcemb_timer_t ppcemb_timer_t; -struct ppcemb_timer_t { +typedef struct ppcemb_timer a_ppcemb_timer; +struct ppcemb_timer { uint64_t pit_reload; /* PIT auto-reload value */ uint64_t fit_next; /* Tick for next FIT interrupt */ struct QEMUTimer *fit_timer; @@ -764,8 +764,8 @@ struct ppcemb_timer_t { static void cpu_4xx_fit_cb (void *opaque) { CPUState *env; - ppc_tb_t *tb_env; - ppcemb_timer_t *ppcemb_timer; + a_ppc_tb *tb_env; + a_ppcemb_timer *ppcemb_timer; uint64_t now, next; env = opaque; @@ -802,9 +802,9 @@ static void cpu_4xx_fit_cb (void *opaque) } /* Programmable interval timer */ -static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp) +static void start_stop_pit (CPUState *env, a_ppc_tb *tb_env, int is_excp) { - ppcemb_timer_t *ppcemb_timer; + a_ppcemb_timer *ppcemb_timer; uint64_t now, next; ppcemb_timer = tb_env->opaque; @@ -832,8 +832,8 @@ static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp) static void cpu_4xx_pit_cb (void *opaque) { CPUState *env; - ppc_tb_t *tb_env; - ppcemb_timer_t *ppcemb_timer; + a_ppc_tb *tb_env; + a_ppcemb_timer *ppcemb_timer; env = opaque; tb_env = env->tb_env; @@ -854,8 +854,8 @@ static void cpu_4xx_pit_cb (void *opaque) static void cpu_4xx_wdt_cb (void *opaque) { CPUState *env; - ppc_tb_t *tb_env; - ppcemb_timer_t *ppcemb_timer; + a_ppc_tb *tb_env; + a_ppcemb_timer *ppcemb_timer; uint64_t now, next; env = opaque; @@ -920,8 +920,8 @@ static void cpu_4xx_wdt_cb (void *opaque) void store_40x_pit (CPUState *env, target_ulong val) { - ppc_tb_t *tb_env; - ppcemb_timer_t *ppcemb_timer; + a_ppc_tb *tb_env; + a_ppcemb_timer *ppcemb_timer; tb_env = env->tb_env; ppcemb_timer = tb_env->opaque; @@ -945,7 +945,7 @@ void store_booke_tsr (CPUState *env, target_ulong val) void store_booke_tcr (CPUState *env, target_ulong val) { - ppc_tb_t *tb_env; + a_ppc_tb *tb_env; tb_env = env->tb_env; LOG_TB("%s: val " TARGET_FMT_lx "\n", __func__, val); @@ -957,7 +957,7 @@ void store_booke_tcr (CPUState *env, target_ulong val) static void ppc_emb_set_tb_clk (void *opaque, uint32_t freq) { CPUState *env = opaque; - ppc_tb_t *tb_env = env->tb_env; + a_ppc_tb *tb_env = env->tb_env; LOG_TB("%s set new frequency to %" PRIu32 "\n", __func__, freq); @@ -968,12 +968,12 @@ static void ppc_emb_set_tb_clk (void *opaque, uint32_t freq) clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq) { - ppc_tb_t *tb_env; - ppcemb_timer_t *ppcemb_timer; + a_ppc_tb *tb_env; + a_ppcemb_timer *ppcemb_timer; - tb_env = qemu_mallocz(sizeof(ppc_tb_t)); + tb_env = qemu_mallocz(sizeof(a_ppc_tb)); env->tb_env = tb_env; - ppcemb_timer = qemu_mallocz(sizeof(ppcemb_timer_t)); + ppcemb_timer = qemu_mallocz(sizeof(a_ppcemb_timer)); tb_env->tb_freq = freq; tb_env->decr_freq = freq; tb_env->opaque = ppcemb_timer; @@ -992,8 +992,8 @@ clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq) /*****************************************************************************/ /* Embedded PowerPC Device Control Registers */ -typedef struct ppc_dcrn_t ppc_dcrn_t; -struct ppc_dcrn_t { +typedef struct ppc_dcrn a_ppc_dcrn; +struct ppc_dcrn { dcr_read_cb dcr_read; dcr_write_cb dcr_write; void *opaque; @@ -1003,15 +1003,15 @@ struct ppc_dcrn_t { * using DCRIPR to get the 22 upper bits of the DCR address */ #define DCRN_NB 1024 -struct ppc_dcr_t { - ppc_dcrn_t dcrn[DCRN_NB]; +struct ppc_dcr { + a_ppc_dcrn dcrn[DCRN_NB]; int (*read_error)(int dcrn); int (*write_error)(int dcrn); }; -int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp) +int ppc_dcr_read (a_ppc_dcr *dcr_env, int dcrn, target_ulong *valp) { - ppc_dcrn_t *dcr; + a_ppc_dcrn *dcr; if (dcrn < 0 || dcrn >= DCRN_NB) goto error; @@ -1029,9 +1029,9 @@ int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp) return -1; } -int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val) +int ppc_dcr_write (a_ppc_dcr *dcr_env, int dcrn, target_ulong val) { - ppc_dcrn_t *dcr; + a_ppc_dcrn *dcr; if (dcrn < 0 || dcrn >= DCRN_NB) goto error; @@ -1052,8 +1052,8 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val) int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, dcr_read_cb dcr_read, dcr_write_cb dcr_write) { - ppc_dcr_t *dcr_env; - ppc_dcrn_t *dcr; + a_ppc_dcr *dcr_env; + a_ppc_dcrn *dcr; dcr_env = env->dcr_env; if (dcr_env == NULL) @@ -1075,9 +1075,9 @@ int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, int ppc_dcr_init (CPUState *env, int (*read_error)(int dcrn), int (*write_error)(int dcrn)) { - ppc_dcr_t *dcr_env; + a_ppc_dcr *dcr_env; - dcr_env = qemu_mallocz(sizeof(ppc_dcr_t)); + dcr_env = qemu_mallocz(sizeof(a_ppc_dcr)); dcr_env->read_error = read_error; dcr_env->write_error = write_error; env->dcr_env = dcr_env; @@ -1117,33 +1117,33 @@ void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val) /*****************************************************************************/ /* NVRAM helpers */ -static inline uint32_t nvram_read (nvram_t *nvram, uint32_t addr) +static inline uint32_t nvram_read (a_nvram *nvram, uint32_t addr) { return (*nvram->read_fn)(nvram->opaque, addr);; } -static inline void nvram_write (nvram_t *nvram, uint32_t addr, uint32_t val) +static inline void nvram_write (a_nvram *nvram, uint32_t addr, uint32_t val) { (*nvram->write_fn)(nvram->opaque, addr, val); } -void NVRAM_set_byte (nvram_t *nvram, uint32_t addr, uint8_t value) +void NVRAM_set_byte (a_nvram *nvram, uint32_t addr, uint8_t value) { nvram_write(nvram, addr, value); } -uint8_t NVRAM_get_byte (nvram_t *nvram, uint32_t addr) +uint8_t NVRAM_get_byte (a_nvram *nvram, uint32_t addr) { return nvram_read(nvram, addr); } -void NVRAM_set_word (nvram_t *nvram, uint32_t addr, uint16_t value) +void NVRAM_set_word (a_nvram *nvram, uint32_t addr, uint16_t value) { nvram_write(nvram, addr, value >> 8); nvram_write(nvram, addr + 1, value & 0xFF); } -uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr) +uint16_t NVRAM_get_word (a_nvram *nvram, uint32_t addr) { uint16_t tmp; @@ -1153,7 +1153,7 @@ uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr) return tmp; } -void NVRAM_set_lword (nvram_t *nvram, uint32_t addr, uint32_t value) +void NVRAM_set_lword (a_nvram *nvram, uint32_t addr, uint32_t value) { nvram_write(nvram, addr, value >> 24); nvram_write(nvram, addr + 1, (value >> 16) & 0xFF); @@ -1161,7 +1161,7 @@ void NVRAM_set_lword (nvram_t *nvram, uint32_t addr, uint32_t value) nvram_write(nvram, addr + 3, value & 0xFF); } -uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr) +uint32_t NVRAM_get_lword (a_nvram *nvram, uint32_t addr) { uint32_t tmp; @@ -1173,7 +1173,7 @@ uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr) return tmp; } -void NVRAM_set_string (nvram_t *nvram, uint32_t addr, +void NVRAM_set_string (a_nvram *nvram, uint32_t addr, const char *str, uint32_t max) { int i; @@ -1185,7 +1185,7 @@ void NVRAM_set_string (nvram_t *nvram, uint32_t addr, nvram_write(nvram, addr + max - 1, '\0'); } -int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max) +int NVRAM_get_string (a_nvram *nvram, uint8_t *dst, uint16_t addr, int max) { int i; @@ -1214,7 +1214,7 @@ static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value) return tmp; } -static uint16_t NVRAM_compute_crc (nvram_t *nvram, uint32_t start, uint32_t count) +static uint16_t NVRAM_compute_crc (a_nvram *nvram, uint32_t start, uint32_t count) { uint32_t i; uint16_t crc = 0xFFFF; @@ -1234,7 +1234,7 @@ static uint16_t NVRAM_compute_crc (nvram_t *nvram, uint32_t start, uint32_t coun #define CMDLINE_ADDR 0x017ff000 -int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size, +int PPC_NVRAM_set_params (a_nvram *nvram, uint16_t NVRAM_size, const char *arch, uint32_t RAM_size, int boot_device, uint32_t kernel_image, uint32_t kernel_size, @@ -1,11 +1,11 @@ /* PowerPC hardware exceptions management helpers */ typedef void (*clk_setup_cb)(void *opaque, uint32_t freq); -typedef struct clk_setup_t clk_setup_t; -struct clk_setup_t { +typedef struct clk_setup a_clk_setup; +struct clk_setup { clk_setup_cb cb; void *opaque; }; -static inline void clk_setup (clk_setup_t *clk, uint32_t freq) +static inline void clk_setup (a_clk_setup *clk, uint32_t freq) { if (clk->cb != NULL) (*clk->cb)(clk->opaque, freq); diff --git a/hw/ppc405.h b/hw/ppc405.h index e042a05b3b..ac1673a883 100644 --- a/hw/ppc405.h +++ b/hw/ppc405.h @@ -28,8 +28,8 @@ #include "ppc4xx.h" /* Bootinfo as set-up by u-boot */ -typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t; -struct ppc4xx_bd_info_t { +typedef struct ppc4xx_bd_info a_ppc4xx_bd_info; +struct ppc4xx_bd_info { uint32_t bi_memstart; uint32_t bi_memsize; uint32_t bi_flashstart; @@ -56,21 +56,21 @@ struct ppc4xx_bd_info_t { }; /* PowerPC 405 core */ -ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd, +a_ram_addr ppc405_set_bootinfo (CPUState *env, a_ppc4xx_bd_info *bd, uint32_t flags); -CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4], - target_phys_addr_t ram_sizes[4], +CPUState *ppc405cr_init (a_target_phys_addr ram_bases[4], + a_target_phys_addr ram_sizes[4], uint32_t sysclk, qemu_irq **picp, int do_init); -CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2], - target_phys_addr_t ram_sizes[2], +CPUState *ppc405ep_init (a_target_phys_addr ram_bases[2], + a_target_phys_addr ram_sizes[2], uint32_t sysclk, qemu_irq **picp, int do_init); /* IBM STBxxx microcontrollers */ -CPUState *ppc_stb025_init (target_phys_addr_t ram_bases[2], - target_phys_addr_t ram_sizes[2], +CPUState *ppc_stb025_init (a_target_phys_addr ram_bases[2], + a_target_phys_addr ram_sizes[2], uint32_t sysclk, qemu_irq **picp, - ram_addr_t *offsetp); + a_ram_addr *offsetp); #endif /* !defined(PPC_405_H) */ diff --git a/hw/ppc405_boards.c b/hw/ppc405_boards.c index 9aa99c1781..6a355ced55 100644 --- a/hw/ppc405_boards.c +++ b/hw/ppc405_boards.c @@ -52,15 +52,15 @@ * - NVRAM (0xF0000000) * - FPGA (0xF0300000) */ -typedef struct ref405ep_fpga_t ref405ep_fpga_t; -struct ref405ep_fpga_t { +typedef struct ref405ep_fpga a_ref405ep_fpga; +struct ref405ep_fpga { uint8_t reg0; uint8_t reg1; }; -static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr) +static uint32_t ref405ep_fpga_readb (void *opaque, a_target_phys_addr addr) { - ref405ep_fpga_t *fpga; + a_ref405ep_fpga *fpga; uint32_t ret; fpga = opaque; @@ -80,9 +80,9 @@ static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr) } static void ref405ep_fpga_writeb (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { - ref405ep_fpga_t *fpga; + a_ref405ep_fpga *fpga; fpga = opaque; switch (addr) { @@ -97,7 +97,7 @@ static void ref405ep_fpga_writeb (void *opaque, } } -static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr) +static uint32_t ref405ep_fpga_readw (void *opaque, a_target_phys_addr addr) { uint32_t ret; @@ -108,13 +108,13 @@ static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr) } static void ref405ep_fpga_writew (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF); ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF); } -static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr) +static uint32_t ref405ep_fpga_readl (void *opaque, a_target_phys_addr addr) { uint32_t ret; @@ -127,7 +127,7 @@ static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr) } static void ref405ep_fpga_writel (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF); ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF); @@ -149,7 +149,7 @@ static CPUWriteMemoryFunc * const ref405ep_fpga_write[] = { static void ref405ep_fpga_reset (void *opaque) { - ref405ep_fpga_t *fpga; + a_ref405ep_fpga *fpga; fpga = opaque; fpga->reg0 = 0x00; @@ -158,10 +158,10 @@ static void ref405ep_fpga_reset (void *opaque) static void ref405ep_fpga_init (uint32_t base) { - ref405ep_fpga_t *fpga; + a_ref405ep_fpga *fpga; int fpga_memory; - fpga = qemu_mallocz(sizeof(ref405ep_fpga_t)); + fpga = qemu_mallocz(sizeof(a_ref405ep_fpga)); fpga_memory = cpu_register_io_memory(ref405ep_fpga_read, ref405ep_fpga_write, fpga); cpu_register_physical_memory(base, 0x00000100, fpga_memory); @@ -169,7 +169,7 @@ static void ref405ep_fpga_init (uint32_t base) qemu_register_reset(&ref405ep_fpga_reset, fpga); } -static void ref405ep_init (ram_addr_t ram_size, +static void ref405ep_init (a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, @@ -177,11 +177,11 @@ static void ref405ep_init (ram_addr_t ram_size, const char *cpu_model) { char *filename; - ppc4xx_bd_info_t bd; + a_ppc4xx_bd_info bd; CPUPPCState *env; qemu_irq *pic; - ram_addr_t sram_offset, bios_offset, bdloc; - target_phys_addr_t ram_bases[2], ram_sizes[2]; + a_ram_addr sram_offset, bios_offset, bdloc; + a_target_phys_addr ram_bases[2], ram_sizes[2]; target_ulong sram_size, bios_size; //int phy_addr = 0; //static int phy_addr = 1; @@ -382,7 +382,7 @@ struct taihu_cpld_t { uint8_t reg1; }; -static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr) +static uint32_t taihu_cpld_readb (void *opaque, a_target_phys_addr addr) { taihu_cpld_t *cpld; uint32_t ret; @@ -404,7 +404,7 @@ static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr) } static void taihu_cpld_writeb (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { taihu_cpld_t *cpld; @@ -421,7 +421,7 @@ static void taihu_cpld_writeb (void *opaque, } } -static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr) +static uint32_t taihu_cpld_readw (void *opaque, a_target_phys_addr addr) { uint32_t ret; @@ -432,13 +432,13 @@ static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr) } static void taihu_cpld_writew (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF); taihu_cpld_writeb(opaque, addr + 1, value & 0xFF); } -static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr) +static uint32_t taihu_cpld_readl (void *opaque, a_target_phys_addr addr) { uint32_t ret; @@ -451,7 +451,7 @@ static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr) } static void taihu_cpld_writel (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF); taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF); @@ -493,7 +493,7 @@ static void taihu_cpld_init (uint32_t base) qemu_register_reset(&taihu_cpld_reset, cpld); } -static void taihu_405ep_init(ram_addr_t ram_size, +static void taihu_405ep_init(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, @@ -503,8 +503,8 @@ static void taihu_405ep_init(ram_addr_t ram_size, char *filename; CPUPPCState *env; qemu_irq *pic; - ram_addr_t bios_offset; - target_phys_addr_t ram_bases[2], ram_sizes[2]; + a_ram_addr bios_offset; + a_target_phys_addr ram_bases[2], ram_sizes[2]; target_ulong bios_size; target_ulong kernel_base, kernel_size, initrd_base, initrd_size; int linux_boot; diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c index 59def4ceb6..2bac4ee313 100644 --- a/hw/ppc405_uc.c +++ b/hw/ppc405_uc.c @@ -40,17 +40,17 @@ #define DEBUG_CLOCKS //#define DEBUG_CLOCKS_LL -ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd, +a_ram_addr ppc405_set_bootinfo (CPUState *env, a_ppc4xx_bd_info *bd, uint32_t flags) { - ram_addr_t bdloc; + a_ram_addr bdloc; int i, n; /* We put the bd structure at the top of memory */ if (bd->bi_memsize >= 0x01000000UL) - bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t); + bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info); else - bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t); + bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info); stl_phys(bdloc + 0x00, bd->bi_memstart); stl_phys(bdloc + 0x04, bd->bi_memsize); stl_phys(bdloc + 0x08, bd->bi_flashstart); @@ -100,8 +100,8 @@ enum { PLB0_ACR = 0x087, }; -typedef struct ppc4xx_plb_t ppc4xx_plb_t; -struct ppc4xx_plb_t { +typedef struct ppc4xx_plb a_ppc4xx_plb; +struct ppc4xx_plb { uint32_t acr; uint32_t bear; uint32_t besr; @@ -109,7 +109,7 @@ struct ppc4xx_plb_t { static target_ulong dcr_read_plb (void *opaque, int dcrn) { - ppc4xx_plb_t *plb; + a_ppc4xx_plb *plb; target_ulong ret; plb = opaque; @@ -134,7 +134,7 @@ static target_ulong dcr_read_plb (void *opaque, int dcrn) static void dcr_write_plb (void *opaque, int dcrn, target_ulong val) { - ppc4xx_plb_t *plb; + a_ppc4xx_plb *plb; plb = opaque; switch (dcrn) { @@ -156,7 +156,7 @@ static void dcr_write_plb (void *opaque, int dcrn, target_ulong val) static void ppc4xx_plb_reset (void *opaque) { - ppc4xx_plb_t *plb; + a_ppc4xx_plb *plb; plb = opaque; plb->acr = 0x00000000; @@ -166,9 +166,9 @@ static void ppc4xx_plb_reset (void *opaque) static void ppc4xx_plb_init(CPUState *env) { - ppc4xx_plb_t *plb; + a_ppc4xx_plb *plb; - plb = qemu_mallocz(sizeof(ppc4xx_plb_t)); + plb = qemu_mallocz(sizeof(a_ppc4xx_plb)); ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); @@ -184,15 +184,15 @@ enum { POB0_BEAR = 0x0A4, }; -typedef struct ppc4xx_pob_t ppc4xx_pob_t; -struct ppc4xx_pob_t { +typedef struct ppc4xx_pob a_ppc4xx_pob; +struct ppc4xx_pob { uint32_t bear; uint32_t besr[2]; }; static target_ulong dcr_read_pob (void *opaque, int dcrn) { - ppc4xx_pob_t *pob; + a_ppc4xx_pob *pob; target_ulong ret; pob = opaque; @@ -215,7 +215,7 @@ static target_ulong dcr_read_pob (void *opaque, int dcrn) static void dcr_write_pob (void *opaque, int dcrn, target_ulong val) { - ppc4xx_pob_t *pob; + a_ppc4xx_pob *pob; pob = opaque; switch (dcrn) { @@ -232,7 +232,7 @@ static void dcr_write_pob (void *opaque, int dcrn, target_ulong val) static void ppc4xx_pob_reset (void *opaque) { - ppc4xx_pob_t *pob; + a_ppc4xx_pob *pob; pob = opaque; /* No error */ @@ -243,9 +243,9 @@ static void ppc4xx_pob_reset (void *opaque) static void ppc4xx_pob_init(CPUState *env) { - ppc4xx_pob_t *pob; + a_ppc4xx_pob *pob; - pob = qemu_mallocz(sizeof(ppc4xx_pob_t)); + pob = qemu_mallocz(sizeof(a_ppc4xx_pob)); ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob); ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob); ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob); @@ -255,15 +255,15 @@ static void ppc4xx_pob_init(CPUState *env) /*****************************************************************************/ /* OPB arbitrer */ -typedef struct ppc4xx_opba_t ppc4xx_opba_t; -struct ppc4xx_opba_t { +typedef struct ppc4xx_opba a_ppc4xx_opba; +struct ppc4xx_opba { uint8_t cr; uint8_t pr; }; -static uint32_t opba_readb (void *opaque, target_phys_addr_t addr) +static uint32_t opba_readb (void *opaque, a_target_phys_addr addr) { - ppc4xx_opba_t *opba; + a_ppc4xx_opba *opba; uint32_t ret; #ifdef DEBUG_OPBA @@ -286,9 +286,9 @@ static uint32_t opba_readb (void *opaque, target_phys_addr_t addr) } static void opba_writeb (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { - ppc4xx_opba_t *opba; + a_ppc4xx_opba *opba; #ifdef DEBUG_OPBA printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, @@ -307,7 +307,7 @@ static void opba_writeb (void *opaque, } } -static uint32_t opba_readw (void *opaque, target_phys_addr_t addr) +static uint32_t opba_readw (void *opaque, a_target_phys_addr addr) { uint32_t ret; @@ -321,7 +321,7 @@ static uint32_t opba_readw (void *opaque, target_phys_addr_t addr) } static void opba_writew (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { #ifdef DEBUG_OPBA printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, @@ -331,7 +331,7 @@ static void opba_writew (void *opaque, opba_writeb(opaque, addr + 1, value); } -static uint32_t opba_readl (void *opaque, target_phys_addr_t addr) +static uint32_t opba_readl (void *opaque, a_target_phys_addr addr) { uint32_t ret; @@ -345,7 +345,7 @@ static uint32_t opba_readl (void *opaque, target_phys_addr_t addr) } static void opba_writel (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { #ifdef DEBUG_OPBA printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, @@ -369,19 +369,19 @@ static CPUWriteMemoryFunc * const opba_write[] = { static void ppc4xx_opba_reset (void *opaque) { - ppc4xx_opba_t *opba; + a_ppc4xx_opba *opba; opba = opaque; opba->cr = 0x00; /* No dynamic priorities - park disabled */ opba->pr = 0x11; } -static void ppc4xx_opba_init(target_phys_addr_t base) +static void ppc4xx_opba_init(a_target_phys_addr base) { - ppc4xx_opba_t *opba; + a_ppc4xx_opba *opba; int io; - opba = qemu_mallocz(sizeof(ppc4xx_opba_t)); + opba = qemu_mallocz(sizeof(a_ppc4xx_opba)); #ifdef DEBUG_OPBA printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); #endif @@ -397,8 +397,8 @@ static void ppc4xx_opba_init(target_phys_addr_t base) /*****************************************************************************/ /* Peripheral controller */ -typedef struct ppc4xx_ebc_t ppc4xx_ebc_t; -struct ppc4xx_ebc_t { +typedef struct ppc4xx_ebc a_ppc4xx_ebc; +struct ppc4xx_ebc { uint32_t addr; uint32_t bcr[8]; uint32_t bap[8]; @@ -415,7 +415,7 @@ enum { static target_ulong dcr_read_ebc (void *opaque, int dcrn) { - ppc4xx_ebc_t *ebc; + a_ppc4xx_ebc *ebc; target_ulong ret; ebc = opaque; @@ -499,7 +499,7 @@ static target_ulong dcr_read_ebc (void *opaque, int dcrn) static void dcr_write_ebc (void *opaque, int dcrn, target_ulong val) { - ppc4xx_ebc_t *ebc; + a_ppc4xx_ebc *ebc; ebc = opaque; switch (dcrn) { @@ -559,7 +559,7 @@ static void dcr_write_ebc (void *opaque, int dcrn, target_ulong val) static void ebc_reset (void *opaque) { - ppc4xx_ebc_t *ebc; + a_ppc4xx_ebc *ebc; int i; ebc = opaque; @@ -577,9 +577,9 @@ static void ebc_reset (void *opaque) static void ppc405_ebc_init(CPUState *env) { - ppc4xx_ebc_t *ebc; + a_ppc4xx_ebc *ebc; - ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t)); + ebc = qemu_mallocz(sizeof(a_ppc4xx_ebc)); ebc_reset(ebc); qemu_register_reset(&ebc_reset, ebc); ppc_dcr_register(env, EBC0_CFGADDR, @@ -617,8 +617,8 @@ enum { DMA0_POL = 0x126, }; -typedef struct ppc405_dma_t ppc405_dma_t; -struct ppc405_dma_t { +typedef struct ppc405_dma a_ppc405_dma; +struct ppc405_dma { qemu_irq irqs[4]; uint32_t cr[4]; uint32_t ct[4]; @@ -633,7 +633,7 @@ struct ppc405_dma_t { static target_ulong dcr_read_dma (void *opaque, int dcrn) { - ppc405_dma_t *dma; + a_ppc405_dma *dma; dma = opaque; @@ -642,14 +642,14 @@ static target_ulong dcr_read_dma (void *opaque, int dcrn) static void dcr_write_dma (void *opaque, int dcrn, target_ulong val) { - ppc405_dma_t *dma; + a_ppc405_dma *dma; dma = opaque; } static void ppc405_dma_reset (void *opaque) { - ppc405_dma_t *dma; + a_ppc405_dma *dma; int i; dma = opaque; @@ -668,9 +668,9 @@ static void ppc405_dma_reset (void *opaque) static void ppc405_dma_init(CPUState *env, qemu_irq irqs[4]) { - ppc405_dma_t *dma; + a_ppc405_dma *dma; - dma = qemu_mallocz(sizeof(ppc405_dma_t)); + dma = qemu_mallocz(sizeof(a_ppc405_dma)); memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq)); ppc405_dma_reset(dma); qemu_register_reset(&ppc405_dma_reset, dma); @@ -726,8 +726,8 @@ static void ppc405_dma_init(CPUState *env, qemu_irq irqs[4]) /*****************************************************************************/ /* GPIO */ -typedef struct ppc405_gpio_t ppc405_gpio_t; -struct ppc405_gpio_t { +typedef struct ppc405_gpio a_ppc405_gpio; +struct ppc405_gpio { uint32_t or; uint32_t tcr; uint32_t osrh; @@ -741,9 +741,9 @@ struct ppc405_gpio_t { uint32_t isr1l; }; -static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr) +static uint32_t ppc405_gpio_readb (void *opaque, a_target_phys_addr addr) { - ppc405_gpio_t *gpio; + a_ppc405_gpio *gpio; gpio = opaque; #ifdef DEBUG_GPIO @@ -754,9 +754,9 @@ static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr) } static void ppc405_gpio_writeb (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { - ppc405_gpio_t *gpio; + a_ppc405_gpio *gpio; gpio = opaque; #ifdef DEBUG_GPIO @@ -765,9 +765,9 @@ static void ppc405_gpio_writeb (void *opaque, #endif } -static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr) +static uint32_t ppc405_gpio_readw (void *opaque, a_target_phys_addr addr) { - ppc405_gpio_t *gpio; + a_ppc405_gpio *gpio; gpio = opaque; #ifdef DEBUG_GPIO @@ -778,9 +778,9 @@ static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr) } static void ppc405_gpio_writew (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { - ppc405_gpio_t *gpio; + a_ppc405_gpio *gpio; gpio = opaque; #ifdef DEBUG_GPIO @@ -789,9 +789,9 @@ static void ppc405_gpio_writew (void *opaque, #endif } -static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr) +static uint32_t ppc405_gpio_readl (void *opaque, a_target_phys_addr addr) { - ppc405_gpio_t *gpio; + a_ppc405_gpio *gpio; gpio = opaque; #ifdef DEBUG_GPIO @@ -802,9 +802,9 @@ static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr) } static void ppc405_gpio_writel (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { - ppc405_gpio_t *gpio; + a_ppc405_gpio *gpio; gpio = opaque; #ifdef DEBUG_GPIO @@ -827,17 +827,17 @@ static CPUWriteMemoryFunc * const ppc405_gpio_write[] = { static void ppc405_gpio_reset (void *opaque) { - ppc405_gpio_t *gpio; + a_ppc405_gpio *gpio; gpio = opaque; } -static void ppc405_gpio_init(target_phys_addr_t base) +static void ppc405_gpio_init(a_target_phys_addr base) { - ppc405_gpio_t *gpio; + a_ppc405_gpio *gpio; int io; - gpio = qemu_mallocz(sizeof(ppc405_gpio_t)); + gpio = qemu_mallocz(sizeof(a_ppc405_gpio)); #ifdef DEBUG_GPIO printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); #endif @@ -856,8 +856,8 @@ enum { OCM0_DSACNTL = 0x01B, }; -typedef struct ppc405_ocm_t ppc405_ocm_t; -struct ppc405_ocm_t { +typedef struct ppc405_ocm a_ppc405_ocm; +struct ppc405_ocm { target_ulong offset; uint32_t isarc; uint32_t isacntl; @@ -865,7 +865,7 @@ struct ppc405_ocm_t { uint32_t dsacntl; }; -static void ocm_update_mappings (ppc405_ocm_t *ocm, +static void ocm_update_mappings (a_ppc405_ocm *ocm, uint32_t isarc, uint32_t isacntl, uint32_t dsarc, uint32_t dsacntl) { @@ -922,7 +922,7 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm, static target_ulong dcr_read_ocm (void *opaque, int dcrn) { - ppc405_ocm_t *ocm; + a_ppc405_ocm *ocm; target_ulong ret; ocm = opaque; @@ -949,7 +949,7 @@ static target_ulong dcr_read_ocm (void *opaque, int dcrn) static void dcr_write_ocm (void *opaque, int dcrn, target_ulong val) { - ppc405_ocm_t *ocm; + a_ppc405_ocm *ocm; uint32_t isarc, dsarc, isacntl, dsacntl; ocm = opaque; @@ -980,7 +980,7 @@ static void dcr_write_ocm (void *opaque, int dcrn, target_ulong val) static void ocm_reset (void *opaque) { - ppc405_ocm_t *ocm; + a_ppc405_ocm *ocm; uint32_t isarc, dsarc, isacntl, dsacntl; ocm = opaque; @@ -997,9 +997,9 @@ static void ocm_reset (void *opaque) static void ppc405_ocm_init(CPUState *env) { - ppc405_ocm_t *ocm; + a_ppc405_ocm *ocm; - ocm = qemu_mallocz(sizeof(ppc405_ocm_t)); + ocm = qemu_mallocz(sizeof(a_ppc405_ocm)); ocm->offset = qemu_ram_alloc(4096); ocm_reset(ocm); qemu_register_reset(&ocm_reset, ocm); @@ -1015,8 +1015,8 @@ static void ppc405_ocm_init(CPUState *env) /*****************************************************************************/ /* I2C controller */ -typedef struct ppc4xx_i2c_t ppc4xx_i2c_t; -struct ppc4xx_i2c_t { +typedef struct ppc4xx_i2c a_ppc4xx_i2c; +struct ppc4xx_i2c { qemu_irq irq; uint8_t mdata; uint8_t lmadr; @@ -1035,9 +1035,9 @@ struct ppc4xx_i2c_t { uint8_t directcntl; }; -static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr) +static uint32_t ppc4xx_i2c_readb (void *opaque, a_target_phys_addr addr) { - ppc4xx_i2c_t *i2c; + a_ppc4xx_i2c *i2c; uint32_t ret; #ifdef DEBUG_I2C @@ -1103,9 +1103,9 @@ static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr) } static void ppc4xx_i2c_writeb (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { - ppc4xx_i2c_t *i2c; + a_ppc4xx_i2c *i2c; #ifdef DEBUG_I2C printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, @@ -1162,7 +1162,7 @@ static void ppc4xx_i2c_writeb (void *opaque, } } -static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr) +static uint32_t ppc4xx_i2c_readw (void *opaque, a_target_phys_addr addr) { uint32_t ret; @@ -1176,7 +1176,7 @@ static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr) } static void ppc4xx_i2c_writew (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { #ifdef DEBUG_I2C printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, @@ -1186,7 +1186,7 @@ static void ppc4xx_i2c_writew (void *opaque, ppc4xx_i2c_writeb(opaque, addr + 1, value); } -static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr) +static uint32_t ppc4xx_i2c_readl (void *opaque, a_target_phys_addr addr) { uint32_t ret; @@ -1202,7 +1202,7 @@ static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr) } static void ppc4xx_i2c_writel (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { #ifdef DEBUG_I2C printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, @@ -1228,7 +1228,7 @@ static CPUWriteMemoryFunc * const i2c_write[] = { static void ppc4xx_i2c_reset (void *opaque) { - ppc4xx_i2c_t *i2c; + a_ppc4xx_i2c *i2c; i2c = opaque; i2c->mdata = 0x00; @@ -1242,12 +1242,12 @@ static void ppc4xx_i2c_reset (void *opaque) i2c->directcntl = 0x0F; } -static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq) +static void ppc405_i2c_init(a_target_phys_addr base, qemu_irq irq) { - ppc4xx_i2c_t *i2c; + a_ppc4xx_i2c *i2c; int io; - i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t)); + i2c = qemu_mallocz(sizeof(a_ppc4xx_i2c)); i2c->irq = irq; #ifdef DEBUG_I2C printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); @@ -1260,8 +1260,8 @@ static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq) /*****************************************************************************/ /* General purpose timers */ -typedef struct ppc4xx_gpt_t ppc4xx_gpt_t; -struct ppc4xx_gpt_t { +typedef struct ppc4xx_gpt a_ppc4xx_gpt; +struct ppc4xx_gpt { int64_t tb_offset; uint32_t tb_freq; struct QEMUTimer *timer; @@ -1275,7 +1275,7 @@ struct ppc4xx_gpt_t { uint32_t mask[5]; }; -static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr) +static uint32_t ppc4xx_gpt_readb (void *opaque, a_target_phys_addr addr) { #ifdef DEBUG_GPT printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); @@ -1285,7 +1285,7 @@ static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr) } static void ppc4xx_gpt_writeb (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { #ifdef DEBUG_I2C printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, @@ -1294,7 +1294,7 @@ static void ppc4xx_gpt_writeb (void *opaque, /* XXX: generate a bus fault */ } -static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr) +static uint32_t ppc4xx_gpt_readw (void *opaque, a_target_phys_addr addr) { #ifdef DEBUG_GPT printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); @@ -1304,7 +1304,7 @@ static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr) } static void ppc4xx_gpt_writew (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { #ifdef DEBUG_I2C printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, @@ -1313,18 +1313,18 @@ static void ppc4xx_gpt_writew (void *opaque, /* XXX: generate a bus fault */ } -static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n) +static int ppc4xx_gpt_compare (a_ppc4xx_gpt *gpt, int n) { /* XXX: TODO */ return 0; } -static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level) +static void ppc4xx_gpt_set_output (a_ppc4xx_gpt *gpt, int n, int level) { /* XXX: TODO */ } -static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt) +static void ppc4xx_gpt_set_outputs (a_ppc4xx_gpt *gpt) { uint32_t mask; int i; @@ -1345,7 +1345,7 @@ static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt) } } -static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt) +static void ppc4xx_gpt_set_irqs (a_ppc4xx_gpt *gpt) { uint32_t mask; int i; @@ -1360,14 +1360,14 @@ static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt) } } -static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt) +static void ppc4xx_gpt_compute_timer (a_ppc4xx_gpt *gpt) { /* XXX: TODO */ } -static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr) +static uint32_t ppc4xx_gpt_readl (void *opaque, a_target_phys_addr addr) { - ppc4xx_gpt_t *gpt; + a_ppc4xx_gpt *gpt; uint32_t ret; int idx; @@ -1421,9 +1421,9 @@ static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr) } static void ppc4xx_gpt_writel (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { - ppc4xx_gpt_t *gpt; + a_ppc4xx_gpt *gpt; int idx; #ifdef DEBUG_I2C @@ -1496,7 +1496,7 @@ static CPUWriteMemoryFunc * const gpt_write[] = { static void ppc4xx_gpt_cb (void *opaque) { - ppc4xx_gpt_t *gpt; + a_ppc4xx_gpt *gpt; gpt = opaque; ppc4xx_gpt_set_irqs(gpt); @@ -1506,7 +1506,7 @@ static void ppc4xx_gpt_cb (void *opaque) static void ppc4xx_gpt_reset (void *opaque) { - ppc4xx_gpt_t *gpt; + a_ppc4xx_gpt *gpt; int i; gpt = opaque; @@ -1522,13 +1522,13 @@ static void ppc4xx_gpt_reset (void *opaque) } } -static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5]) +static void ppc4xx_gpt_init(a_target_phys_addr base, qemu_irq irqs[5]) { - ppc4xx_gpt_t *gpt; + a_ppc4xx_gpt *gpt; int i; int io; - gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t)); + gpt = qemu_mallocz(sizeof(a_ppc4xx_gpt)); for (i = 0; i < 5; i++) { gpt->irqs[i] = irqs[i]; } @@ -1566,8 +1566,8 @@ enum { MAL0_RCBS1 = 0x1E1, }; -typedef struct ppc40x_mal_t ppc40x_mal_t; -struct ppc40x_mal_t { +typedef struct ppc40x_mal a_ppc40x_mal; +struct ppc40x_mal { qemu_irq irqs[4]; uint32_t cfg; uint32_t esr; @@ -1589,7 +1589,7 @@ static void ppc40x_mal_reset (void *opaque); static target_ulong dcr_read_mal (void *opaque, int dcrn) { - ppc40x_mal_t *mal; + a_ppc40x_mal *mal; target_ulong ret; mal = opaque; @@ -1661,7 +1661,7 @@ static target_ulong dcr_read_mal (void *opaque, int dcrn) static void dcr_write_mal (void *opaque, int dcrn, target_ulong val) { - ppc40x_mal_t *mal; + a_ppc40x_mal *mal; int idx; mal = opaque; @@ -1741,7 +1741,7 @@ static void dcr_write_mal (void *opaque, int dcrn, target_ulong val) static void ppc40x_mal_reset (void *opaque) { - ppc40x_mal_t *mal; + a_ppc40x_mal *mal; mal = opaque; mal->cfg = 0x0007C000; @@ -1757,10 +1757,10 @@ static void ppc40x_mal_reset (void *opaque) static void ppc405_mal_init(CPUState *env, qemu_irq irqs[4]) { - ppc40x_mal_t *mal; + a_ppc40x_mal *mal; int i; - mal = qemu_mallocz(sizeof(ppc40x_mal_t)); + mal = qemu_mallocz(sizeof(a_ppc40x_mal)); for (i = 0; i < 4; i++) mal->irqs[i] = irqs[i]; ppc40x_mal_reset(mal); @@ -1895,9 +1895,9 @@ enum { PPC405CR_CLK_NB = 7, }; -typedef struct ppc405cr_cpc_t ppc405cr_cpc_t; -struct ppc405cr_cpc_t { - clk_setup_t clk_setup[PPC405CR_CLK_NB]; +typedef struct ppc405cr_cpc a_ppc405cr_cpc; +struct ppc405cr_cpc { + a_clk_setup clk_setup[PPC405CR_CLK_NB]; uint32_t sysclk; uint32_t psr; uint32_t cr0; @@ -1908,7 +1908,7 @@ struct ppc405cr_cpc_t { uint32_t fr; }; -static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc) +static void ppc405cr_clk_setup (a_ppc405cr_cpc *cpc) { uint64_t VCO_out, PLL_out; uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk; @@ -1963,7 +1963,7 @@ static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc) static target_ulong dcr_read_crcpc (void *opaque, int dcrn) { - ppc405cr_cpc_t *cpc; + a_ppc405cr_cpc *cpc; target_ulong ret; cpc = opaque; @@ -2003,7 +2003,7 @@ static target_ulong dcr_read_crcpc (void *opaque, int dcrn) static void dcr_write_crcpc (void *opaque, int dcrn, target_ulong val) { - ppc405cr_cpc_t *cpc; + a_ppc405cr_cpc *cpc; cpc = opaque; switch (dcrn) { @@ -2036,7 +2036,7 @@ static void dcr_write_crcpc (void *opaque, int dcrn, target_ulong val) static void ppc405cr_cpc_reset (void *opaque) { - ppc405cr_cpc_t *cpc; + a_ppc405cr_cpc *cpc; int D; cpc = opaque; @@ -2095,7 +2095,7 @@ static void ppc405cr_cpc_reset (void *opaque) ppc405cr_clk_setup(cpc); } -static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc) +static void ppc405cr_clk_init (a_ppc405cr_cpc *cpc) { int D; @@ -2121,14 +2121,14 @@ static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc) cpc->psr |= D << 17; } -static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7], +static void ppc405cr_cpc_init (CPUState *env, a_clk_setup clk_setup[7], uint32_t sysclk) { - ppc405cr_cpc_t *cpc; + a_ppc405cr_cpc *cpc; - cpc = qemu_mallocz(sizeof(ppc405cr_cpc_t)); + cpc = qemu_mallocz(sizeof(a_ppc405cr_cpc)); memcpy(cpc->clk_setup, clk_setup, - PPC405CR_CLK_NB * sizeof(clk_setup_t)); + PPC405CR_CLK_NB * sizeof(a_clk_setup)); cpc->sysclk = sysclk; cpc->jtagid = 0x42051049; ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc, @@ -2152,12 +2152,12 @@ static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7], ppc405cr_cpc_reset(cpc); } -CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4], - target_phys_addr_t ram_sizes[4], +CPUState *ppc405cr_init (a_target_phys_addr ram_bases[4], + a_target_phys_addr ram_sizes[4], uint32_t sysclk, qemu_irq **picp, int do_init) { - clk_setup_t clk_setup[PPC405CR_CLK_NB]; + a_clk_setup clk_setup[PPC405CR_CLK_NB]; qemu_irq dma_irqs[4]; CPUState *env; qemu_irq *pic, *irqs; @@ -2240,10 +2240,10 @@ enum { PPC405EP_CLK_NB = 8, }; -typedef struct ppc405ep_cpc_t ppc405ep_cpc_t; -struct ppc405ep_cpc_t { +typedef struct ppc405ep_cpc a_ppc405ep_cpc; +struct ppc405ep_cpc { uint32_t sysclk; - clk_setup_t clk_setup[PPC405EP_CLK_NB]; + a_clk_setup clk_setup[PPC405EP_CLK_NB]; uint32_t boot; uint32_t epctl; uint32_t pllmr[2]; @@ -2257,7 +2257,7 @@ struct ppc405ep_cpc_t { uint32_t sr; }; -static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc) +static void ppc405ep_compute_clocks (a_ppc405ep_cpc *cpc) { uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk; uint32_t UART0_clk, UART1_clk; @@ -2366,7 +2366,7 @@ static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc) static target_ulong dcr_read_epcpc (void *opaque, int dcrn) { - ppc405ep_cpc_t *cpc; + a_ppc405ep_cpc *cpc; target_ulong ret; cpc = opaque; @@ -2406,7 +2406,7 @@ static target_ulong dcr_read_epcpc (void *opaque, int dcrn) static void dcr_write_epcpc (void *opaque, int dcrn, target_ulong val) { - ppc405ep_cpc_t *cpc; + a_ppc405ep_cpc *cpc; cpc = opaque; switch (dcrn) { @@ -2443,7 +2443,7 @@ static void dcr_write_epcpc (void *opaque, int dcrn, target_ulong val) static void ppc405ep_cpc_reset (void *opaque) { - ppc405ep_cpc_t *cpc = opaque; + a_ppc405ep_cpc *cpc = opaque; cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */ cpc->epctl = 0x00000000; @@ -2459,14 +2459,14 @@ static void ppc405ep_cpc_reset (void *opaque) } /* XXX: sysclk should be between 25 and 100 MHz */ -static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8], +static void ppc405ep_cpc_init (CPUState *env, a_clk_setup clk_setup[8], uint32_t sysclk) { - ppc405ep_cpc_t *cpc; + a_ppc405ep_cpc *cpc; - cpc = qemu_mallocz(sizeof(ppc405ep_cpc_t)); + cpc = qemu_mallocz(sizeof(a_ppc405ep_cpc)); memcpy(cpc->clk_setup, clk_setup, - PPC405EP_CLK_NB * sizeof(clk_setup_t)); + PPC405EP_CLK_NB * sizeof(a_clk_setup)); cpc->jtagid = 0x20267049; cpc->sysclk = sysclk; ppc405ep_cpc_reset(cpc); @@ -2497,12 +2497,12 @@ static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8], #endif } -CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2], - target_phys_addr_t ram_sizes[2], +CPUState *ppc405ep_init (a_target_phys_addr ram_bases[2], + a_target_phys_addr ram_sizes[2], uint32_t sysclk, qemu_irq **picp, int do_init) { - clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; + a_clk_setup clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; CPUState *env; qemu_irq *pic, *irqs; diff --git a/hw/ppc440.c b/hw/ppc440.c index abe0a560da..4d728cf399 100644 --- a/hw/ppc440.c +++ b/hw/ppc440.c @@ -34,12 +34,12 @@ static const unsigned int ppc440ep_sdram_bank_sizes[] = { 256<<20, 128<<20, 64<<20, 32<<20, 16<<20, 8<<20, 0 }; -CPUState *ppc440ep_init(ram_addr_t *ram_size, PCIBus **pcip, +CPUState *ppc440ep_init(a_ram_addr *ram_size, PCIBus **pcip, const unsigned int pci_irq_nrs[4], int do_init, const char *cpu_model) { - target_phys_addr_t ram_bases[PPC440EP_SDRAM_NR_BANKS]; - target_phys_addr_t ram_sizes[PPC440EP_SDRAM_NR_BANKS]; + a_target_phys_addr ram_bases[PPC440EP_SDRAM_NR_BANKS]; + a_target_phys_addr ram_sizes[PPC440EP_SDRAM_NR_BANKS]; CPUState *env; qemu_irq *pic; qemu_irq *irqs; diff --git a/hw/ppc440.h b/hw/ppc440.h index a40f9176db..0501ee3083 100644 --- a/hw/ppc440.h +++ b/hw/ppc440.h @@ -14,7 +14,7 @@ #include "hw.h" -CPUState *ppc440ep_init(ram_addr_t *ram_size, PCIBus **pcip, +CPUState *ppc440ep_init(a_ram_addr *ram_size, PCIBus **pcip, const unsigned int pci_irq_nrs[4], int do_init, const char *cpu_model); diff --git a/hw/ppc440_bamboo.c b/hw/ppc440_bamboo.c index 8a6b7ced92..6d5bdd4924 100644 --- a/hw/ppc440_bamboo.c +++ b/hw/ppc440_bamboo.c @@ -27,10 +27,10 @@ #define BINARY_DEVICE_TREE_FILE "bamboo.dtb" -static void *bamboo_load_device_tree(target_phys_addr_t addr, +static void *bamboo_load_device_tree(a_target_phys_addr addr, uint32_t ramsize, - target_phys_addr_t initrd_base, - target_phys_addr_t initrd_size, + a_target_phys_addr initrd_base, + a_target_phys_addr initrd_size, const char *kernel_cmdline) { void *fdt = NULL; @@ -83,7 +83,7 @@ out: return fdt; } -static void bamboo_init(ram_addr_t ram_size, +static void bamboo_init(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, @@ -95,8 +95,8 @@ static void bamboo_init(ram_addr_t ram_size, CPUState *env; uint64_t elf_entry; uint64_t elf_lowaddr; - target_phys_addr_t entry = 0; - target_phys_addr_t loadaddr = 0; + a_target_phys_addr entry = 0; + a_target_phys_addr loadaddr = 0; target_long kernel_size = 0; target_ulong initrd_base = 0; target_long initrd_size = 0; diff --git a/hw/ppc4xx.h b/hw/ppc4xx.h index bc4ee019a5..34592cf7f7 100644 --- a/hw/ppc4xx.h +++ b/hw/ppc4xx.h @@ -29,7 +29,7 @@ /* PowerPC 4xx core initialization */ CPUState *ppc4xx_init (const char *cpu_model, - clk_setup_t *cpu_clk, clk_setup_t *tb_clk, + a_clk_setup *cpu_clk, a_clk_setup *tb_clk, uint32_t sysclk); /* PowerPC 4xx universal interrupt controller */ @@ -41,20 +41,20 @@ enum { qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs, uint32_t dcr_base, int has_ssr, int has_vr); -ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks, - target_phys_addr_t ram_bases[], - target_phys_addr_t ram_sizes[], +a_ram_addr ppc4xx_sdram_adjust(a_ram_addr ram_size, int nr_banks, + a_target_phys_addr ram_bases[], + a_target_phys_addr ram_sizes[], const unsigned int sdram_bank_sizes[]); void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks, - target_phys_addr_t *ram_bases, - target_phys_addr_t *ram_sizes, + a_target_phys_addr *ram_bases, + a_target_phys_addr *ram_sizes, int do_init); PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4], - target_phys_addr_t config_space, - target_phys_addr_t int_ack, - target_phys_addr_t special_cycle, - target_phys_addr_t registers); + a_target_phys_addr config_space, + a_target_phys_addr int_ack, + a_target_phys_addr special_cycle, + a_target_phys_addr registers); #endif /* !defined(PPC_4XX_H) */ diff --git a/hw/ppc4xx_devs.c b/hw/ppc4xx_devs.c index 0b1c93b802..2f84e3cddf 100644 --- a/hw/ppc4xx_devs.c +++ b/hw/ppc4xx_devs.c @@ -41,7 +41,7 @@ /*****************************************************************************/ /* Generic PowerPC 4xx processor instanciation */ CPUState *ppc4xx_init (const char *cpu_model, - clk_setup_t *cpu_clk, clk_setup_t *tb_clk, + a_clk_setup *cpu_clk, a_clk_setup *tb_clk, uint32_t sysclk) { CPUState *env; @@ -81,8 +81,8 @@ enum { }; #define UIC_MAX_IRQ 32 -typedef struct ppcuic_t ppcuic_t; -struct ppcuic_t { +typedef struct ppcuic a_ppcuic; +struct ppcuic { uint32_t dcr_base; int use_vectors; uint32_t level; /* Remembers the state of level-triggered interrupts. */ @@ -96,7 +96,7 @@ struct ppcuic_t { qemu_irq *irqs; }; -static void ppcuic_trigger_irq (ppcuic_t *uic) +static void ppcuic_trigger_irq (a_ppcuic *uic) { uint32_t ir, cr; int start, end, inc, i; @@ -149,7 +149,7 @@ static void ppcuic_trigger_irq (ppcuic_t *uic) static void ppcuic_set_irq (void *opaque, int irq_num, int level) { - ppcuic_t *uic; + a_ppcuic *uic; uint32_t mask, sr; uic = opaque; @@ -185,7 +185,7 @@ static void ppcuic_set_irq (void *opaque, int irq_num, int level) static target_ulong dcr_read_uic (void *opaque, int dcrn) { - ppcuic_t *uic; + a_ppcuic *uic; target_ulong ret; uic = opaque; @@ -231,7 +231,7 @@ static target_ulong dcr_read_uic (void *opaque, int dcrn) static void dcr_write_uic (void *opaque, int dcrn, target_ulong val) { - ppcuic_t *uic; + a_ppcuic *uic; uic = opaque; dcrn -= uic->dcr_base; @@ -274,7 +274,7 @@ static void dcr_write_uic (void *opaque, int dcrn, target_ulong val) static void ppcuic_reset (void *opaque) { - ppcuic_t *uic; + a_ppcuic *uic; uic = opaque; uic->uiccr = 0x00000000; @@ -291,10 +291,10 @@ static void ppcuic_reset (void *opaque) qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs, uint32_t dcr_base, int has_ssr, int has_vr) { - ppcuic_t *uic; + a_ppcuic *uic; int i; - uic = qemu_mallocz(sizeof(ppcuic_t)); + uic = qemu_mallocz(sizeof(a_ppcuic)); uic->dcr_base = dcr_base; uic->irqs = irqs; if (has_vr) @@ -311,12 +311,12 @@ qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs, /*****************************************************************************/ /* SDRAM controller */ -typedef struct ppc4xx_sdram_t ppc4xx_sdram_t; -struct ppc4xx_sdram_t { +typedef struct ppc4xx_sdram a_ppc4xx_sdram; +struct ppc4xx_sdram { uint32_t addr; int nbanks; - target_phys_addr_t ram_bases[4]; - target_phys_addr_t ram_sizes[4]; + a_target_phys_addr ram_bases[4]; + a_target_phys_addr ram_sizes[4]; uint32_t besr0; uint32_t besr1; uint32_t bear; @@ -337,11 +337,11 @@ enum { }; /* XXX: TOFIX: some patches have made this code become inconsistent: - * there are type inconsistencies, mixing target_phys_addr_t, target_ulong + * there are type inconsistencies, mixing a_target_phys_addr, target_ulong * and uint32_t */ -static uint32_t sdram_bcr (target_phys_addr_t ram_base, - target_phys_addr_t ram_size) +static uint32_t sdram_bcr (a_target_phys_addr ram_base, + a_target_phys_addr ram_size) { uint32_t bcr; @@ -378,7 +378,7 @@ static uint32_t sdram_bcr (target_phys_addr_t ram_base, return bcr; } -static inline target_phys_addr_t sdram_base(uint32_t bcr) +static inline a_target_phys_addr sdram_base(uint32_t bcr) { return bcr & 0xFF800000; } @@ -419,7 +419,7 @@ static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled) } } -static void sdram_map_bcr (ppc4xx_sdram_t *sdram) +static void sdram_map_bcr (a_ppc4xx_sdram *sdram) { int i; @@ -434,7 +434,7 @@ static void sdram_map_bcr (ppc4xx_sdram_t *sdram) } } -static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram) +static void sdram_unmap_bcr (a_ppc4xx_sdram *sdram) { int i; @@ -451,7 +451,7 @@ static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram) static target_ulong dcr_read_sdram (void *opaque, int dcrn) { - ppc4xx_sdram_t *sdram; + a_ppc4xx_sdram *sdram; target_ulong ret; sdram = opaque; @@ -519,7 +519,7 @@ static target_ulong dcr_read_sdram (void *opaque, int dcrn) static void dcr_write_sdram (void *opaque, int dcrn, target_ulong val) { - ppc4xx_sdram_t *sdram; + a_ppc4xx_sdram *sdram; sdram = opaque; switch (dcrn) { @@ -604,7 +604,7 @@ static void dcr_write_sdram (void *opaque, int dcrn, target_ulong val) static void sdram_reset (void *opaque) { - ppc4xx_sdram_t *sdram; + a_ppc4xx_sdram *sdram; sdram = opaque; sdram->addr = 0x00000000; @@ -624,21 +624,21 @@ static void sdram_reset (void *opaque) } void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks, - target_phys_addr_t *ram_bases, - target_phys_addr_t *ram_sizes, + a_target_phys_addr *ram_bases, + a_target_phys_addr *ram_sizes, int do_init) { - ppc4xx_sdram_t *sdram; + a_ppc4xx_sdram *sdram; - sdram = qemu_mallocz(sizeof(ppc4xx_sdram_t)); + sdram = qemu_mallocz(sizeof(a_ppc4xx_sdram)); sdram->irq = irq; sdram->nbanks = nbanks; - memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t)); + memset(sdram->ram_bases, 0, 4 * sizeof(a_target_phys_addr)); memcpy(sdram->ram_bases, ram_bases, - nbanks * sizeof(target_phys_addr_t)); - memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t)); + nbanks * sizeof(a_target_phys_addr)); + memset(sdram->ram_sizes, 0, 4 * sizeof(a_target_phys_addr)); memcpy(sdram->ram_sizes, ram_sizes, - nbanks * sizeof(target_phys_addr_t)); + nbanks * sizeof(a_target_phys_addr)); sdram_reset(sdram); qemu_register_reset(&sdram_reset, sdram); ppc_dcr_register(env, SDRAM0_CFGADDR, @@ -656,12 +656,12 @@ void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks, * The 4xx SDRAM controller supports a small number of banks, and each bank * must be one of a small set of sizes. The number of banks and the supported * sizes varies by SoC. */ -ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks, - target_phys_addr_t ram_bases[], - target_phys_addr_t ram_sizes[], +a_ram_addr ppc4xx_sdram_adjust(a_ram_addr ram_size, int nr_banks, + a_target_phys_addr ram_bases[], + a_target_phys_addr ram_sizes[], const unsigned int sdram_bank_sizes[]) { - ram_addr_t size_left = ram_size; + a_ram_addr size_left = ram_size; int i; int j; diff --git a/hw/ppc4xx_pci.c b/hw/ppc4xx_pci.c index 655fe86571..f9386603f1 100644 --- a/hw/ppc4xx_pci.c +++ b/hw/ppc4xx_pci.c @@ -23,7 +23,7 @@ #include "ppc.h" #include "ppc4xx.h" -typedef target_phys_addr_t pci_addr_t; +typedef a_target_phys_addr a_pci_addr; #include "pci.h" #include "pci_host.h" #include "bswap.h" @@ -86,7 +86,7 @@ typedef struct PPC4xxPCIState PPC4xxPCIState; #define PCI_REG_SIZE 0x40 -static uint32_t pci4xx_cfgaddr_readl(void *opaque, target_phys_addr_t addr) +static uint32_t pci4xx_cfgaddr_readl(void *opaque, a_target_phys_addr addr) { PPC4xxPCIState *ppc4xx_pci = opaque; @@ -99,7 +99,7 @@ static CPUReadMemoryFunc * const pci4xx_cfgaddr_read[] = { &pci4xx_cfgaddr_readl, }; -static void pci4xx_cfgaddr_writel(void *opaque, target_phys_addr_t addr, +static void pci4xx_cfgaddr_writel(void *opaque, a_target_phys_addr addr, uint32_t value) { PPC4xxPCIState *ppc4xx_pci = opaque; @@ -129,7 +129,7 @@ static CPUWriteMemoryFunc * const pci4xx_cfgdata_write[] = { &pci_host_data_writel, }; -static void ppc4xx_pci_reg_write4(void *opaque, target_phys_addr_t offset, +static void ppc4xx_pci_reg_write4(void *opaque, a_target_phys_addr offset, uint32_t value) { struct PPC4xxPCIState *pci = opaque; @@ -201,7 +201,7 @@ static void ppc4xx_pci_reg_write4(void *opaque, target_phys_addr_t offset, } } -static uint32_t ppc4xx_pci_reg_read4(void *opaque, target_phys_addr_t offset) +static uint32_t ppc4xx_pci_reg_read4(void *opaque, a_target_phys_addr offset) { struct PPC4xxPCIState *pci = opaque; uint32_t value; @@ -359,10 +359,10 @@ static int ppc4xx_pci_load(QEMUFile *f, void *opaque, int version_id) /* XXX Interrupt acknowledge cycles not supported. */ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4], - target_phys_addr_t config_space, - target_phys_addr_t int_ack, - target_phys_addr_t special_cycle, - target_phys_addr_t registers) + a_target_phys_addr config_space, + a_target_phys_addr int_ack, + a_target_phys_addr special_cycle, + a_target_phys_addr registers) { PPC4xxPCIState *controller; int index; diff --git a/hw/ppc_mac.h b/hw/ppc_mac.h index a04dffea84..5b3b7fe4ce 100644 --- a/hw/ppc_mac.h +++ b/hw/ppc_mac.h @@ -62,9 +62,9 @@ PCIBus *pci_pmac_init(qemu_irq *pic); /* Mac NVRAM */ typedef struct MacIONVRAMState MacIONVRAMState; -MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size, +MacIONVRAMState *macio_nvram_init (int *mem_index, a_target_phys_addr size, unsigned int it_shift); -void macio_nvram_map (void *opaque, target_phys_addr_t mem_base); +void macio_nvram_map (void *opaque, a_target_phys_addr mem_base); void pmac_format_nvram_partition (MacIONVRAMState *nvr, int len); uint32_t macio_nvram_read (void *opaque, uint32_t addr); void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val); diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c index 6bd5234d8f..5e18dd28f2 100644 --- a/hw/ppc_newworld.c +++ b/hw/ppc_newworld.c @@ -54,12 +54,12 @@ #endif /* UniN device */ -static void unin_writel (void *opaque, target_phys_addr_t addr, uint32_t value) +static void unin_writel (void *opaque, a_target_phys_addr addr, uint32_t value) { UNIN_DPRINTF("writel addr " TARGET_FMT_plx " val %x\n", addr, value); } -static uint32_t unin_readl (void *opaque, target_phys_addr_t addr) +static uint32_t unin_readl (void *opaque, a_target_phys_addr addr) { uint32_t value; @@ -88,7 +88,7 @@ static int fw_cfg_boot_set(void *opaque, const char *boot_device) } /* PowerPC Mac99 hardware initialisation */ -static void ppc_core99_init (ram_addr_t ram_size, +static void ppc_core99_init (a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, @@ -100,7 +100,7 @@ static void ppc_core99_init (ram_addr_t ram_size, qemu_irq *pic, **openpic_irqs; int unin_memory; int linux_boot, i; - ram_addr_t ram_offset, bios_offset, vga_bios_offset; + a_ram_addr ram_offset, bios_offset, vga_bios_offset; uint32_t kernel_base, kernel_size, initrd_base, initrd_size; PCIBus *pci_bus; MacIONVRAMState *nvr; diff --git a/hw/ppc_oldworld.c b/hw/ppc_oldworld.c index bb8c969ca2..df9c006aca 100644 --- a/hw/ppc_oldworld.c +++ b/hw/ppc_oldworld.c @@ -119,7 +119,7 @@ static int fw_cfg_boot_set(void *opaque, const char *boot_device) return 0; } -static void ppc_heathrow_init (ram_addr_t ram_size, +static void ppc_heathrow_init (a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, @@ -130,7 +130,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size, char *filename; qemu_irq *pic, **heathrow_irqs; int linux_boot, i; - ram_addr_t ram_offset, bios_offset, vga_bios_offset; + a_ram_addr ram_offset, bios_offset, vga_bios_offset; uint32_t kernel_base, initrd_base; int32_t kernel_size, initrd_size; PCIBus *pci_bus; diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c index 0525b1e030..62025bb1bc 100644 --- a/hw/ppc_prep.c +++ b/hw/ppc_prep.c @@ -112,7 +112,7 @@ static uint32_t speaker_ioport_read (void *opaque, uint32_t addr) /* PCI intack register */ /* Read-only register (?) */ static void _PPC_intack_write (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { #if 0 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, @@ -120,7 +120,7 @@ static void _PPC_intack_write (void *opaque, #endif } -static inline uint32_t _PPC_intack_read(target_phys_addr_t addr) +static inline uint32_t _PPC_intack_read(a_target_phys_addr addr) { uint32_t retval = 0; @@ -134,12 +134,12 @@ static inline uint32_t _PPC_intack_read(target_phys_addr_t addr) return retval; } -static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr) +static uint32_t PPC_intack_readb (void *opaque, a_target_phys_addr addr) { return _PPC_intack_read(addr); } -static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr) +static uint32_t PPC_intack_readw (void *opaque, a_target_phys_addr addr) { #ifdef TARGET_WORDS_BIGENDIAN return bswap16(_PPC_intack_read(addr)); @@ -148,7 +148,7 @@ static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr) #endif } -static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr) +static uint32_t PPC_intack_readl (void *opaque, a_target_phys_addr addr) { #ifdef TARGET_WORDS_BIGENDIAN return bswap32(_PPC_intack_read(addr)); @@ -197,14 +197,14 @@ static struct { } XCSR; static void PPC_XCSR_writeb (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, value); } static void PPC_XCSR_writew (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { #ifdef TARGET_WORDS_BIGENDIAN value = bswap16(value); @@ -214,7 +214,7 @@ static void PPC_XCSR_writew (void *opaque, } static void PPC_XCSR_writel (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { #ifdef TARGET_WORDS_BIGENDIAN value = bswap32(value); @@ -223,7 +223,7 @@ static void PPC_XCSR_writel (void *opaque, value); } -static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr) +static uint32_t PPC_XCSR_readb (void *opaque, a_target_phys_addr addr) { uint32_t retval = 0; @@ -233,7 +233,7 @@ static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr) return retval; } -static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr) +static uint32_t PPC_XCSR_readw (void *opaque, a_target_phys_addr addr) { uint32_t retval = 0; @@ -246,7 +246,7 @@ static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr) return retval; } -static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr) +static uint32_t PPC_XCSR_readl (void *opaque, a_target_phys_addr addr) { uint32_t retval = 0; @@ -273,25 +273,25 @@ static CPUReadMemoryFunc * const PPC_XCSR_read[] = { #endif /* Fake super-io ports for PREP platform (Intel 82378ZB) */ -typedef struct sysctrl_t { +typedef struct sysctrl { qemu_irq reset_irq; - m48t59_t *nvram; + a_m48t59 *nvram; uint8_t state; uint8_t syscontrol; uint8_t fake_io[2]; int contiguous_map; int endian; -} sysctrl_t; +} a_sysctrl; enum { STATE_HARDFILE = 0x01, }; -static sysctrl_t *sysctrl; +static a_sysctrl *sysctrl; static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val) { - sysctrl_t *sysctrl = opaque; + a_sysctrl *sysctrl = opaque; PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE, val); @@ -300,7 +300,7 @@ static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val) static uint32_t PREP_io_read (void *opaque, uint32_t addr) { - sysctrl_t *sysctrl = opaque; + a_sysctrl *sysctrl = opaque; PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE, sysctrl->fake_io[addr - 0x0398]); @@ -309,7 +309,7 @@ static uint32_t PREP_io_read (void *opaque, uint32_t addr) static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) { - sysctrl_t *sysctrl = opaque; + a_sysctrl *sysctrl = opaque; PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE, val); @@ -376,7 +376,7 @@ static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) { - sysctrl_t *sysctrl = opaque; + a_sysctrl *sysctrl = opaque; uint32_t retval = 0xFF; switch (addr) { @@ -440,8 +440,8 @@ static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) return retval; } -static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl, - target_phys_addr_t addr) +static inline a_target_phys_addr prep_IO_address(a_sysctrl *sysctrl, + a_target_phys_addr addr) { if (sysctrl->contiguous_map == 0) { /* 64 KB contiguous space for IOs */ @@ -454,18 +454,18 @@ static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl, return addr; } -static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr, +static void PPC_prep_io_writeb (void *opaque, a_target_phys_addr addr, uint32_t value) { - sysctrl_t *sysctrl = opaque; + a_sysctrl *sysctrl = opaque; addr = prep_IO_address(sysctrl, addr); cpu_outb(addr, value); } -static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr) +static uint32_t PPC_prep_io_readb (void *opaque, a_target_phys_addr addr) { - sysctrl_t *sysctrl = opaque; + a_sysctrl *sysctrl = opaque; uint32_t ret; addr = prep_IO_address(sysctrl, addr); @@ -474,10 +474,10 @@ static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr) return ret; } -static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr, +static void PPC_prep_io_writew (void *opaque, a_target_phys_addr addr, uint32_t value) { - sysctrl_t *sysctrl = opaque; + a_sysctrl *sysctrl = opaque; addr = prep_IO_address(sysctrl, addr); #ifdef TARGET_WORDS_BIGENDIAN @@ -487,9 +487,9 @@ static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr, cpu_outw(addr, value); } -static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr) +static uint32_t PPC_prep_io_readw (void *opaque, a_target_phys_addr addr) { - sysctrl_t *sysctrl = opaque; + a_sysctrl *sysctrl = opaque; uint32_t ret; addr = prep_IO_address(sysctrl, addr); @@ -502,10 +502,10 @@ static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr) return ret; } -static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr, +static void PPC_prep_io_writel (void *opaque, a_target_phys_addr addr, uint32_t value) { - sysctrl_t *sysctrl = opaque; + a_sysctrl *sysctrl = opaque; addr = prep_IO_address(sysctrl, addr); #ifdef TARGET_WORDS_BIGENDIAN @@ -515,9 +515,9 @@ static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr, cpu_outl(addr, value); } -static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr) +static uint32_t PPC_prep_io_readl (void *opaque, a_target_phys_addr addr) { - sysctrl_t *sysctrl = opaque; + a_sysctrl *sysctrl = opaque; uint32_t ret; addr = prep_IO_address(sysctrl, addr); @@ -545,7 +545,7 @@ static CPUReadMemoryFunc * const PPC_prep_io_read[] = { #define NVRAM_SIZE 0x2000 /* PowerPC PREP hardware initialisation */ -static void ppc_prep_init (ram_addr_t ram_size, +static void ppc_prep_init (a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, @@ -554,11 +554,11 @@ static void ppc_prep_init (ram_addr_t ram_size, { CPUState *env = NULL, *envs[MAX_CPUS]; char *filename; - nvram_t nvram; - m48t59_t *m48t59; + a_nvram nvram; + a_m48t59 *m48t59; int PPC_io_memory; int linux_boot, i, nb_nics1, bios_size; - ram_addr_t ram_offset, bios_offset; + a_ram_addr ram_offset, bios_offset; uint32_t kernel_base, kernel_size, initrd_base, initrd_size; PCIBus *pci_bus; qemu_irq *i8259; @@ -567,7 +567,7 @@ static void ppc_prep_init (ram_addr_t ram_size, DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; BlockDriverState *fd[MAX_FD]; - sysctrl = qemu_mallocz(sizeof(sysctrl_t)); + sysctrl = qemu_mallocz(sizeof(a_sysctrl)); linux_boot = (kernel_filename != NULL); @@ -606,7 +606,7 @@ static void ppc_prep_init (ram_addr_t ram_size, bios_size = -1; } if (bios_size > 0 && bios_size <= BIOS_SIZE) { - target_phys_addr_t bios_addr; + a_target_phys_addr bios_addr; bios_size = (bios_size + 0xfff) & ~0xfff; bios_addr = (uint32_t)(-bios_size); cpu_register_physical_memory(bios_addr, bios_size, diff --git a/hw/ppce500.h b/hw/ppce500.h index 24d49bb871..a9ed10c407 100644 --- a/hw/ppce500.h +++ b/hw/ppce500.h @@ -17,6 +17,6 @@ #if !defined(PPC_E500_H) #define PPC_E500_H -PCIBus *ppce500_pci_init(qemu_irq *pic, target_phys_addr_t registers); +PCIBus *ppce500_pci_init(qemu_irq *pic, a_target_phys_addr registers); #endif /* !defined(PPC_E500_H) */ diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c index 504419458b..1429de6eba 100644 --- a/hw/ppce500_mpc8544ds.c +++ b/hw/ppce500_mpc8544ds.c @@ -72,10 +72,10 @@ out: } #endif -static void *mpc8544_load_device_tree(target_phys_addr_t addr, +static void *mpc8544_load_device_tree(a_target_phys_addr addr, uint32_t ramsize, - target_phys_addr_t initrd_base, - target_phys_addr_t initrd_size, + a_target_phys_addr initrd_base, + a_target_phys_addr initrd_size, const char *kernel_cmdline) { void *fdt = NULL; @@ -151,7 +151,7 @@ out: return fdt; } -static void mpc8544ds_init(ram_addr_t ram_size, +static void mpc8544ds_init(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, @@ -162,8 +162,8 @@ static void mpc8544ds_init(ram_addr_t ram_size, CPUState *env; uint64_t elf_entry; uint64_t elf_lowaddr; - target_phys_addr_t entry=0; - target_phys_addr_t loadaddr=UIMAGE_LOAD_BASE; + a_target_phys_addr entry=0; + a_target_phys_addr loadaddr=UIMAGE_LOAD_BASE; target_long kernel_size=0; target_ulong dt_base=DTB_LOAD_BASE; target_ulong initrd_base=INITRD_LOAD_BASE; diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c index 64fccfdbc6..ae438d8724 100644 --- a/hw/ppce500_pci.c +++ b/hw/ppce500_pci.c @@ -17,7 +17,7 @@ #include "hw.h" #include "ppc.h" #include "ppce500.h" -typedef target_phys_addr_t pci_addr_t; +typedef a_target_phys_addr a_pci_addr; #include "pci.h" #include "pci_host.h" #include "bswap.h" @@ -85,7 +85,7 @@ struct PPCE500PCIState { typedef struct PPCE500PCIState PPCE500PCIState; -static uint32_t pcie500_cfgaddr_readl(void *opaque, target_phys_addr_t addr) +static uint32_t pcie500_cfgaddr_readl(void *opaque, a_target_phys_addr addr) { PPCE500PCIState *pci = opaque; @@ -100,7 +100,7 @@ static CPUReadMemoryFunc * const pcie500_cfgaddr_read[] = { &pcie500_cfgaddr_readl, }; -static void pcie500_cfgaddr_writel(void *opaque, target_phys_addr_t addr, +static void pcie500_cfgaddr_writel(void *opaque, a_target_phys_addr addr, uint32_t value) { PPCE500PCIState *controller = opaque; @@ -128,7 +128,7 @@ static CPUWriteMemoryFunc * const pcie500_cfgdata_write[] = { &pci_host_data_writel, }; -static uint32_t pci_reg_read4(void *opaque, target_phys_addr_t addr) +static uint32_t pci_reg_read4(void *opaque, a_target_phys_addr addr) { PPCE500PCIState *pci = opaque; unsigned long win; @@ -181,7 +181,7 @@ static CPUReadMemoryFunc * const e500_pci_reg_read[] = { &pci_reg_read4, }; -static void pci_reg_write4(void *opaque, target_phys_addr_t addr, +static void pci_reg_write4(void *opaque, a_target_phys_addr addr, uint32_t value) { PPCE500PCIState *pci = opaque; @@ -313,7 +313,7 @@ static int ppce500_pci_load(QEMUFile *f, void *opaque, int version_id) return 0; } -PCIBus *ppce500_pci_init(qemu_irq pci_irqs[4], target_phys_addr_t registers) +PCIBus *ppce500_pci_init(qemu_irq pci_irqs[4], a_target_phys_addr registers) { PPCE500PCIState *controller; PCIDevice *d; diff --git a/hw/prep_pci.c b/hw/prep_pci.c index 2d8a0fa956..cf46a3c61a 100644 --- a/hw/prep_pci.c +++ b/hw/prep_pci.c @@ -25,7 +25,7 @@ #include "hw.h" #include "pci.h" -typedef uint32_t pci_addr_t; +typedef uint32_t a_pci_addr; #include "pci_host.h" typedef PCIHostState PREPPCIState; @@ -42,7 +42,7 @@ static uint32_t pci_prep_addr_readl(void* opaque, uint32_t addr) return s->config_reg; } -static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr) +static inline uint32_t PPC_PCIIO_config(a_target_phys_addr addr) { int i; @@ -53,13 +53,13 @@ static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr) return (addr & 0x7ff) | (i << 11); } -static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val) +static void PPC_PCIIO_writeb (void *opaque, a_target_phys_addr addr, uint32_t val) { PREPPCIState *s = opaque; pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 1); } -static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val) +static void PPC_PCIIO_writew (void *opaque, a_target_phys_addr addr, uint32_t val) { PREPPCIState *s = opaque; #ifdef TARGET_WORDS_BIGENDIAN @@ -68,7 +68,7 @@ static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t va pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 2); } -static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val) +static void PPC_PCIIO_writel (void *opaque, a_target_phys_addr addr, uint32_t val) { PREPPCIState *s = opaque; #ifdef TARGET_WORDS_BIGENDIAN @@ -77,7 +77,7 @@ static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t va pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 4); } -static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr) +static uint32_t PPC_PCIIO_readb (void *opaque, a_target_phys_addr addr) { PREPPCIState *s = opaque; uint32_t val; @@ -85,7 +85,7 @@ static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr) return val; } -static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr) +static uint32_t PPC_PCIIO_readw (void *opaque, a_target_phys_addr addr) { PREPPCIState *s = opaque; uint32_t val; @@ -96,7 +96,7 @@ static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr) return val; } -static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr) +static uint32_t PPC_PCIIO_readl (void *opaque, a_target_phys_addr addr) { PREPPCIState *s = opaque; uint32_t val; @@ -63,15 +63,15 @@ # define PXA2XX_INTERNAL_SIZE 0x40000 /* pxa2xx_pic.c */ -qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env); +qemu_irq *pxa2xx_pic_init(a_target_phys_addr base, CPUState *env); /* pxa2xx_timer.c */ -void pxa25x_timer_init(target_phys_addr_t base, qemu_irq *irqs); -void pxa27x_timer_init(target_phys_addr_t base, qemu_irq *irqs, qemu_irq irq4); +void pxa25x_timer_init(a_target_phys_addr base, qemu_irq *irqs); +void pxa27x_timer_init(a_target_phys_addr base, qemu_irq *irqs, qemu_irq irq4); /* pxa2xx_gpio.c */ typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo; -PXA2xxGPIOInfo *pxa2xx_gpio_init(target_phys_addr_t base, +PXA2xxGPIOInfo *pxa2xx_gpio_init(a_target_phys_addr base, CPUState *env, qemu_irq *pic, int lines); qemu_irq *pxa2xx_gpio_in_get(PXA2xxGPIOInfo *s); void pxa2xx_gpio_out_set(PXA2xxGPIOInfo *s, @@ -80,29 +80,29 @@ void pxa2xx_gpio_read_notifier(PXA2xxGPIOInfo *s, qemu_irq handler); /* pxa2xx_dma.c */ typedef struct PXA2xxDMAState PXA2xxDMAState; -PXA2xxDMAState *pxa255_dma_init(target_phys_addr_t base, +PXA2xxDMAState *pxa255_dma_init(a_target_phys_addr base, qemu_irq irq); -PXA2xxDMAState *pxa27x_dma_init(target_phys_addr_t base, +PXA2xxDMAState *pxa27x_dma_init(a_target_phys_addr base, qemu_irq irq); void pxa2xx_dma_request(PXA2xxDMAState *s, int req_num, int on); /* pxa2xx_lcd.c */ typedef struct PXA2xxLCDState PXA2xxLCDState; -PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base, +PXA2xxLCDState *pxa2xx_lcdc_init(a_target_phys_addr base, qemu_irq irq); void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler); void pxa2xx_lcdc_oritentation(void *opaque, int angle); /* pxa2xx_mmci.c */ typedef struct PXA2xxMMCIState PXA2xxMMCIState; -PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base, +PXA2xxMMCIState *pxa2xx_mmci_init(a_target_phys_addr base, BlockDriverState *bd, qemu_irq irq, void *dma); void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly, qemu_irq coverswitch); /* pxa2xx_pcmcia.c */ typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState; -PXA2xxPCMCIAState *pxa2xx_pcmcia_init(target_phys_addr_t base); +PXA2xxPCMCIAState *pxa2xx_pcmcia_init(a_target_phys_addr base); int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card); int pxa2xx_pcmcia_dettach(void *opaque); void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq); @@ -113,14 +113,14 @@ struct keymap { int row; }; typedef struct PXA2xxKeyPadState PXA2xxKeyPadState; -PXA2xxKeyPadState *pxa27x_keypad_init(target_phys_addr_t base, +PXA2xxKeyPadState *pxa27x_keypad_init(a_target_phys_addr base, qemu_irq irq); void pxa27x_register_keypad(PXA2xxKeyPadState *kp, struct keymap *map, int size); /* pxa2xx.c */ typedef struct PXA2xxI2CState PXA2xxI2CState; -PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base, +PXA2xxI2CState *pxa2xx_i2c_init(a_target_phys_addr base, qemu_irq irq, uint32_t page_size); i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s); @@ -143,23 +143,23 @@ typedef struct { PXA2xxKeyPadState *kp; /* Power management */ - target_phys_addr_t pm_base; + a_target_phys_addr pm_base; uint32_t pm_regs[0x40]; /* Clock management */ - target_phys_addr_t cm_base; + a_target_phys_addr cm_base; uint32_t cm_regs[4]; uint32_t clkcfg; /* Memory management */ - target_phys_addr_t mm_base; + a_target_phys_addr mm_base; uint32_t mm_regs[0x1a]; /* Performance monitoring */ uint32_t pmnc; /* Real-Time clock */ - target_phys_addr_t rtc_base; + a_target_phys_addr rtc_base; uint32_t rttr; uint32_t rtsr; uint32_t rtar; @@ -214,7 +214,7 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision); PXA2xxState *pxa255_init(unsigned int sdram_size); /* usb-ohci.c */ -void usb_ohci_init_pxa(target_phys_addr_t base, int num_ports, int devfn, +void usb_ohci_init_pxa(a_target_phys_addr base, int num_ports, int devfn, qemu_irq irq); #endif /* PXA_H */ diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c index e38a12544a..3dcd2c88e7 100644 --- a/hw/pxa2xx.c +++ b/hw/pxa2xx.c @@ -17,7 +17,7 @@ #include "qemu-char.h" static struct { - target_phys_addr_t io_base; + a_target_phys_addr io_base; int irqn; } pxa255_serial[] = { { 0x40100000, PXA2XX_PIC_FFUART }, @@ -33,7 +33,7 @@ static struct { }; typedef struct PXASSPDef { - target_phys_addr_t io_base; + a_target_phys_addr io_base; int irqn; } PXASSPDef; @@ -88,7 +88,7 @@ static PXASSPDef pxa27x_ssp[] = { #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */ #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */ -static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr) +static uint32_t pxa2xx_pm_read(void *opaque, a_target_phys_addr addr) { PXA2xxState *s = (PXA2xxState *) opaque; @@ -106,7 +106,7 @@ static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr) return 0; } -static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr, +static void pxa2xx_pm_write(void *opaque, a_target_phys_addr addr, uint32_t value) { PXA2xxState *s = (PXA2xxState *) opaque; @@ -171,7 +171,7 @@ static int pxa2xx_pm_load(QEMUFile *f, void *opaque, int version_id) #define OSCC 0x08 /* Oscillator Configuration register */ #define CCSR 0x0c /* Core Clock Status register */ -static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr) +static uint32_t pxa2xx_cm_read(void *opaque, a_target_phys_addr addr) { PXA2xxState *s = (PXA2xxState *) opaque; @@ -191,7 +191,7 @@ static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr) return 0; } -static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr, +static void pxa2xx_cm_write(void *opaque, a_target_phys_addr addr, uint32_t value) { PXA2xxState *s = (PXA2xxState *) opaque; @@ -481,7 +481,7 @@ static void pxa2xx_cp14_write(void *opaque, int op2, int reg, int crm, #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */ #define SA1110 0x64 /* SA-1110 Memory Compatibility register */ -static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr) +static uint32_t pxa2xx_mm_read(void *opaque, a_target_phys_addr addr) { PXA2xxState *s = (PXA2xxState *) opaque; @@ -497,7 +497,7 @@ static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr) return 0; } -static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr, +static void pxa2xx_mm_write(void *opaque, a_target_phys_addr addr, uint32_t value) { PXA2xxState *s = (PXA2xxState *) opaque; @@ -656,7 +656,7 @@ static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s) pxa2xx_ssp_int_update(s); } -static uint32_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr) +static uint32_t pxa2xx_ssp_read(void *opaque, a_target_phys_addr addr) { PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; uint32_t retval; @@ -701,7 +701,7 @@ static uint32_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr) return 0; } -static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr, +static void pxa2xx_ssp_write(void *opaque, a_target_phys_addr addr, uint32_t value) { PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; @@ -1008,7 +1008,7 @@ static inline void pxa2xx_rtc_pi_tick(void *opaque) pxa2xx_rtc_int_update(s); } -static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr) +static uint32_t pxa2xx_rtc_read(void *opaque, a_target_phys_addr addr) { PXA2xxState *s = (PXA2xxState *) opaque; @@ -1053,7 +1053,7 @@ static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr) return 0; } -static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr, +static void pxa2xx_rtc_write(void *opaque, a_target_phys_addr addr, uint32_t value) { PXA2xxState *s = (PXA2xxState *) opaque; @@ -1263,7 +1263,7 @@ struct PXA2xxI2CState { PXA2xxI2CSlaveState *slave; i2c_bus *bus; qemu_irq irq; - target_phys_addr_t offset; + a_target_phys_addr offset; uint16_t control; uint16_t status; @@ -1343,7 +1343,7 @@ static int pxa2xx_i2c_tx(i2c_slave *i2c, uint8_t data) return 1; } -static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr) +static uint32_t pxa2xx_i2c_read(void *opaque, a_target_phys_addr addr) { PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; @@ -1370,7 +1370,7 @@ static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr) return 0; } -static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr, +static void pxa2xx_i2c_write(void *opaque, a_target_phys_addr addr, uint32_t value) { PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; @@ -1495,7 +1495,7 @@ static I2CSlaveInfo pxa2xx_i2c_slave_info = { .send = pxa2xx_i2c_tx }; -PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base, +PXA2xxI2CState *pxa2xx_i2c_init(a_target_phys_addr base, qemu_irq irq, uint32_t region_size) { int iomemtype; @@ -1582,7 +1582,7 @@ static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s) #define SADIV 0x60 /* Serial Audio Clock Divider register */ #define SADR 0x80 /* Serial Audio Data register */ -static uint32_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr) +static uint32_t pxa2xx_i2s_read(void *opaque, a_target_phys_addr addr) { PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; @@ -1613,7 +1613,7 @@ static uint32_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr) return 0; } -static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr, +static void pxa2xx_i2s_write(void *opaque, a_target_phys_addr addr, uint32_t value) { PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; @@ -1736,7 +1736,7 @@ static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx) pxa2xx_i2s_update(s); } -static PXA2xxI2SState *pxa2xx_i2s_init(target_phys_addr_t base, +static PXA2xxI2SState *pxa2xx_i2s_init(a_target_phys_addr base, qemu_irq irq, PXA2xxDMAState *dma) { int iomemtype; @@ -1830,7 +1830,7 @@ static inline void pxa2xx_fir_update(PXA2xxFIrState *s) #define ICSR1 0x18 /* FICP Status register 1 */ #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */ -static uint32_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr) +static uint32_t pxa2xx_fir_read(void *opaque, a_target_phys_addr addr) { PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; uint8_t ret; @@ -1867,7 +1867,7 @@ static uint32_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr) return 0; } -static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr, +static void pxa2xx_fir_write(void *opaque, a_target_phys_addr addr, uint32_t value) { PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; @@ -1994,7 +1994,7 @@ static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id) return 0; } -static PXA2xxFIrState *pxa2xx_fir_init(target_phys_addr_t base, +static PXA2xxFIrState *pxa2xx_fir_init(a_target_phys_addr base, qemu_irq irq, PXA2xxDMAState *dma, CharDriverState *chr) { diff --git a/hw/pxa2xx_dma.c b/hw/pxa2xx_dma.c index 66c2c30a8c..32b79d750a 100644 --- a/hw/pxa2xx_dma.c +++ b/hw/pxa2xx_dma.c @@ -12,9 +12,9 @@ #include "pxa.h" typedef struct { - target_phys_addr_t descr; - target_phys_addr_t src; - target_phys_addr_t dest; + a_target_phys_addr descr; + a_target_phys_addr src; + a_target_phys_addr dest; uint32_t cmd; uint32_t state; int request; @@ -148,7 +148,7 @@ static inline void pxa2xx_dma_descriptor_fetch( PXA2xxDMAState *s, int ch) { uint32_t desc[4]; - target_phys_addr_t daddr = s->chan[ch].descr & ~0xf; + a_target_phys_addr daddr = s->chan[ch].descr & ~0xf; if ((s->chan[ch].descr & DDADR_BREN) && (s->chan[ch].state & DCSR_CMPST)) daddr += 32; @@ -252,7 +252,7 @@ static void pxa2xx_dma_run(PXA2xxDMAState *s) } } -static uint32_t pxa2xx_dma_read(void *opaque, target_phys_addr_t offset) +static uint32_t pxa2xx_dma_read(void *opaque, a_target_phys_addr offset) { PXA2xxDMAState *s = (PXA2xxDMAState *) opaque; unsigned int channel; @@ -306,7 +306,7 @@ static uint32_t pxa2xx_dma_read(void *opaque, target_phys_addr_t offset) } static void pxa2xx_dma_write(void *opaque, - target_phys_addr_t offset, uint32_t value) + a_target_phys_addr offset, uint32_t value) { PXA2xxDMAState *s = (PXA2xxDMAState *) opaque; unsigned int channel; @@ -404,14 +404,14 @@ static void pxa2xx_dma_write(void *opaque, } } -static uint32_t pxa2xx_dma_readbad(void *opaque, target_phys_addr_t offset) +static uint32_t pxa2xx_dma_readbad(void *opaque, a_target_phys_addr offset) { hw_error("%s: Bad access width\n", __FUNCTION__); return 5; } static void pxa2xx_dma_writebad(void *opaque, - target_phys_addr_t offset, uint32_t value) + a_target_phys_addr offset, uint32_t value) { hw_error("%s: Bad access width\n", __FUNCTION__); } @@ -483,7 +483,7 @@ static int pxa2xx_dma_load(QEMUFile *f, void *opaque, int version_id) return 0; } -static PXA2xxDMAState *pxa2xx_dma_init(target_phys_addr_t base, +static PXA2xxDMAState *pxa2xx_dma_init(a_target_phys_addr base, qemu_irq irq, int channels) { int i, iomemtype; @@ -512,13 +512,13 @@ static PXA2xxDMAState *pxa2xx_dma_init(target_phys_addr_t base, return s; } -PXA2xxDMAState *pxa27x_dma_init(target_phys_addr_t base, +PXA2xxDMAState *pxa27x_dma_init(a_target_phys_addr base, qemu_irq irq) { return pxa2xx_dma_init(base, irq, PXA27X_DMA_NUM_CHANNELS); } -PXA2xxDMAState *pxa255_dma_init(target_phys_addr_t base, +PXA2xxDMAState *pxa255_dma_init(a_target_phys_addr base, qemu_irq irq) { return pxa2xx_dma_init(base, irq, PXA255_DMA_NUM_CHANNELS); diff --git a/hw/pxa2xx_gpio.c b/hw/pxa2xx_gpio.c index f354f4bd1f..5718aa104c 100644 --- a/hw/pxa2xx_gpio.c +++ b/hw/pxa2xx_gpio.c @@ -134,7 +134,7 @@ static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) { } } -static uint32_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset) +static uint32_t pxa2xx_gpio_read(void *opaque, a_target_phys_addr offset) { PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque; uint32_t ret; @@ -186,7 +186,7 @@ static uint32_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset) } static void pxa2xx_gpio_write(void *opaque, - target_phys_addr_t offset, uint32_t value) + a_target_phys_addr offset, uint32_t value) { PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque; int bank; @@ -294,7 +294,7 @@ static int pxa2xx_gpio_load(QEMUFile *f, void *opaque, int version_id) return 0; } -PXA2xxGPIOInfo *pxa2xx_gpio_init(target_phys_addr_t base, +PXA2xxGPIOInfo *pxa2xx_gpio_init(a_target_phys_addr base, CPUState *env, qemu_irq *pic, int lines) { int iomemtype; diff --git a/hw/pxa2xx_keypad.c b/hw/pxa2xx_keypad.c index 060df58445..a3481f4c62 100644 --- a/hw/pxa2xx_keypad.c +++ b/hw/pxa2xx_keypad.c @@ -154,7 +154,7 @@ out: return; } -static uint32_t pxa2xx_keypad_read(void *opaque, target_phys_addr_t offset) +static uint32_t pxa2xx_keypad_read(void *opaque, a_target_phys_addr offset) { PXA2xxKeyPadState *s = (PXA2xxKeyPadState *) opaque; uint32_t tmp; @@ -216,7 +216,7 @@ static uint32_t pxa2xx_keypad_read(void *opaque, target_phys_addr_t offset) } static void pxa2xx_keypad_write(void *opaque, - target_phys_addr_t offset, uint32_t value) + a_target_phys_addr offset, uint32_t value) { PXA2xxKeyPadState *s = (PXA2xxKeyPadState *) opaque; @@ -304,7 +304,7 @@ static int pxa2xx_keypad_load(QEMUFile *f, void *opaque, int version_id) return 0; } -PXA2xxKeyPadState *pxa27x_keypad_init(target_phys_addr_t base, +PXA2xxKeyPadState *pxa27x_keypad_init(a_target_phys_addr base, qemu_irq irq) { int iomemtype; diff --git a/hw/pxa2xx_lcd.c b/hw/pxa2xx_lcd.c index 930299abd3..127d0d72f2 100644 --- a/hw/pxa2xx_lcd.c +++ b/hw/pxa2xx_lcd.c @@ -51,15 +51,15 @@ struct PXA2xxLCDState { uint8_t bscntr; struct { - target_phys_addr_t branch; + a_target_phys_addr branch; int up; uint8_t palette[1024]; uint8_t pbuffer[1024]; - void (*redraw)(PXA2xxLCDState *s, target_phys_addr_t addr, + void (*redraw)(PXA2xxLCDState *s, a_target_phys_addr addr, int *miny, int *maxy); - target_phys_addr_t descriptor; - target_phys_addr_t source; + a_target_phys_addr descriptor; + a_target_phys_addr source; uint32_t id; uint32_t command; } dma_ch[7]; @@ -284,7 +284,7 @@ static inline void pxa2xx_dma_rdst_set(PXA2xxLCDState *s) static void pxa2xx_descriptor_load(PXA2xxLCDState *s) { PXAFrameDescriptor desc; - target_phys_addr_t descptr; + a_target_phys_addr descptr; int i; for (i = 0; i < PXA_LCDDMA_CHANS; i ++) { @@ -313,7 +313,7 @@ static void pxa2xx_descriptor_load(PXA2xxLCDState *s) } } -static uint32_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset) +static uint32_t pxa2xx_lcdc_read(void *opaque, a_target_phys_addr offset) { PXA2xxLCDState *s = (PXA2xxLCDState *) opaque; int ch; @@ -407,7 +407,7 @@ static uint32_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset) } static void pxa2xx_lcdc_write(void *opaque, - target_phys_addr_t offset, uint32_t value) + a_target_phys_addr offset, uint32_t value) { PXA2xxLCDState *s = (PXA2xxLCDState *) opaque; int ch; @@ -664,7 +664,7 @@ static void pxa2xx_palette_parse(PXA2xxLCDState *s, int ch, int bpp) } static void pxa2xx_lcdc_dma0_redraw_horiz(PXA2xxLCDState *s, - target_phys_addr_t addr, int *miny, int *maxy) + a_target_phys_addr addr, int *miny, int *maxy) { int src_width, dest_width; drawfn fn = NULL; @@ -691,7 +691,7 @@ static void pxa2xx_lcdc_dma0_redraw_horiz(PXA2xxLCDState *s, } static void pxa2xx_lcdc_dma0_redraw_vert(PXA2xxLCDState *s, - target_phys_addr_t addr, int *miny, int *maxy) + a_target_phys_addr addr, int *miny, int *maxy) { int src_width, dest_width; drawfn fn = NULL; @@ -741,7 +741,7 @@ static void pxa2xx_lcdc_resize(PXA2xxLCDState *s) static void pxa2xx_update_display(void *opaque) { PXA2xxLCDState *s = (PXA2xxLCDState *) opaque; - target_phys_addr_t fbptr; + a_target_phys_addr fbptr; int miny, maxy; int ch; if (!(s->control[0] & LCCR0_ENB)) @@ -917,7 +917,7 @@ static int pxa2xx_lcdc_load(QEMUFile *f, void *opaque, int version_id) #define BITS 32 #include "pxa2xx_template.h" -PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq) +PXA2xxLCDState *pxa2xx_lcdc_init(a_target_phys_addr base, qemu_irq irq) { int iomemtype; PXA2xxLCDState *s; diff --git a/hw/pxa2xx_mmci.c b/hw/pxa2xx_mmci.c index a415349a7e..33539de316 100644 --- a/hw/pxa2xx_mmci.c +++ b/hw/pxa2xx_mmci.c @@ -211,7 +211,7 @@ static void pxa2xx_mmci_wakequeues(PXA2xxMMCIState *s) pxa2xx_mmci_fifo_update(s); } -static uint32_t pxa2xx_mmci_read(void *opaque, target_phys_addr_t offset) +static uint32_t pxa2xx_mmci_read(void *opaque, a_target_phys_addr offset) { PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; uint32_t ret; @@ -273,7 +273,7 @@ static uint32_t pxa2xx_mmci_read(void *opaque, target_phys_addr_t offset) } static void pxa2xx_mmci_write(void *opaque, - target_phys_addr_t offset, uint32_t value) + a_target_phys_addr offset, uint32_t value) { PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; @@ -382,21 +382,21 @@ static void pxa2xx_mmci_write(void *opaque, } } -static uint32_t pxa2xx_mmci_readb(void *opaque, target_phys_addr_t offset) +static uint32_t pxa2xx_mmci_readb(void *opaque, a_target_phys_addr offset) { PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; s->ac_width = 1; return pxa2xx_mmci_read(opaque, offset); } -static uint32_t pxa2xx_mmci_readh(void *opaque, target_phys_addr_t offset) +static uint32_t pxa2xx_mmci_readh(void *opaque, a_target_phys_addr offset) { PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; s->ac_width = 2; return pxa2xx_mmci_read(opaque, offset); } -static uint32_t pxa2xx_mmci_readw(void *opaque, target_phys_addr_t offset) +static uint32_t pxa2xx_mmci_readw(void *opaque, a_target_phys_addr offset) { PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; s->ac_width = 4; @@ -410,7 +410,7 @@ static CPUReadMemoryFunc * const pxa2xx_mmci_readfn[] = { }; static void pxa2xx_mmci_writeb(void *opaque, - target_phys_addr_t offset, uint32_t value) + a_target_phys_addr offset, uint32_t value) { PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; s->ac_width = 1; @@ -418,7 +418,7 @@ static void pxa2xx_mmci_writeb(void *opaque, } static void pxa2xx_mmci_writeh(void *opaque, - target_phys_addr_t offset, uint32_t value) + a_target_phys_addr offset, uint32_t value) { PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; s->ac_width = 2; @@ -426,7 +426,7 @@ static void pxa2xx_mmci_writeh(void *opaque, } static void pxa2xx_mmci_writew(void *opaque, - target_phys_addr_t offset, uint32_t value) + a_target_phys_addr offset, uint32_t value) { PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; s->ac_width = 4; @@ -517,7 +517,7 @@ static int pxa2xx_mmci_load(QEMUFile *f, void *opaque, int version_id) return 0; } -PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base, +PXA2xxMMCIState *pxa2xx_mmci_init(a_target_phys_addr base, BlockDriverState *bd, qemu_irq irq, void *dma) { int iomemtype; diff --git a/hw/pxa2xx_pcmcia.c b/hw/pxa2xx_pcmcia.c index be1309f62e..5c8a7059b8 100644 --- a/hw/pxa2xx_pcmcia.c +++ b/hw/pxa2xx_pcmcia.c @@ -20,7 +20,7 @@ struct PXA2xxPCMCIAState { }; static uint32_t pxa2xx_pcmcia_common_read(void *opaque, - target_phys_addr_t offset) + a_target_phys_addr offset) { PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque; @@ -32,7 +32,7 @@ static uint32_t pxa2xx_pcmcia_common_read(void *opaque, } static void pxa2xx_pcmcia_common_write(void *opaque, - target_phys_addr_t offset, uint32_t value) + a_target_phys_addr offset, uint32_t value) { PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque; @@ -42,7 +42,7 @@ static void pxa2xx_pcmcia_common_write(void *opaque, } static uint32_t pxa2xx_pcmcia_attr_read(void *opaque, - target_phys_addr_t offset) + a_target_phys_addr offset) { PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque; @@ -54,7 +54,7 @@ static uint32_t pxa2xx_pcmcia_attr_read(void *opaque, } static void pxa2xx_pcmcia_attr_write(void *opaque, - target_phys_addr_t offset, uint32_t value) + a_target_phys_addr offset, uint32_t value) { PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque; @@ -64,7 +64,7 @@ static void pxa2xx_pcmcia_attr_write(void *opaque, } static uint32_t pxa2xx_pcmcia_io_read(void *opaque, - target_phys_addr_t offset) + a_target_phys_addr offset) { PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque; @@ -76,7 +76,7 @@ static uint32_t pxa2xx_pcmcia_io_read(void *opaque, } static void pxa2xx_pcmcia_io_write(void *opaque, - target_phys_addr_t offset, uint32_t value) + a_target_phys_addr offset, uint32_t value) { PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque; @@ -130,7 +130,7 @@ static void pxa2xx_pcmcia_set_irq(void *opaque, int line, int level) qemu_set_irq(s->irq, level); } -PXA2xxPCMCIAState *pxa2xx_pcmcia_init(target_phys_addr_t base) +PXA2xxPCMCIAState *pxa2xx_pcmcia_init(a_target_phys_addr base) { int iomemtype; PXA2xxPCMCIAState *s; diff --git a/hw/pxa2xx_pic.c b/hw/pxa2xx_pic.c index 0a98342328..c84d02f454 100644 --- a/hw/pxa2xx_pic.c +++ b/hw/pxa2xx_pic.c @@ -113,7 +113,7 @@ static inline uint32_t pxa2xx_pic_highest(PXA2xxPICState *s) { return ichp; } -static uint32_t pxa2xx_pic_mem_read(void *opaque, target_phys_addr_t offset) +static uint32_t pxa2xx_pic_mem_read(void *opaque, a_target_phys_addr offset) { PXA2xxPICState *s = (PXA2xxPICState *) opaque; @@ -152,7 +152,7 @@ static uint32_t pxa2xx_pic_mem_read(void *opaque, target_phys_addr_t offset) } } -static void pxa2xx_pic_mem_write(void *opaque, target_phys_addr_t offset, +static void pxa2xx_pic_mem_write(void *opaque, a_target_phys_addr offset, uint32_t value) { PXA2xxPICState *s = (PXA2xxPICState *) opaque; @@ -204,7 +204,7 @@ static const int pxa2xx_cp_reg_map[0x10] = { static uint32_t pxa2xx_pic_cp_read(void *opaque, int op2, int reg, int crm) { - target_phys_addr_t offset; + a_target_phys_addr offset; if (pxa2xx_cp_reg_map[reg] == -1) { printf("%s: Bad register 0x%x\n", __FUNCTION__, reg); @@ -218,7 +218,7 @@ static uint32_t pxa2xx_pic_cp_read(void *opaque, int op2, int reg, int crm) static void pxa2xx_pic_cp_write(void *opaque, int op2, int reg, int crm, uint32_t value) { - target_phys_addr_t offset; + a_target_phys_addr offset; if (pxa2xx_cp_reg_map[reg] == -1) { printf("%s: Bad register 0x%x\n", __FUNCTION__, reg); @@ -276,7 +276,7 @@ static int pxa2xx_pic_load(QEMUFile *f, void *opaque, int version_id) return 0; } -qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env) +qemu_irq *pxa2xx_pic_init(a_target_phys_addr base, CPUState *env) { PXA2xxPICState *s; int iomemtype; diff --git a/hw/pxa2xx_timer.c b/hw/pxa2xx_timer.c index d992cc3c43..c981eb2f39 100644 --- a/hw/pxa2xx_timer.c +++ b/hw/pxa2xx_timer.c @@ -134,7 +134,7 @@ static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n) qemu_mod_timer(s->tm4[n].tm.qtimer, new_qemu); } -static uint32_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset) +static uint32_t pxa2xx_timer_read(void *opaque, a_target_phys_addr offset) { pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque; int tm = 0; @@ -211,7 +211,7 @@ static uint32_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset) return 0; } -static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset, +static void pxa2xx_timer_write(void *opaque, a_target_phys_addr offset, uint32_t value) { int i, tm = 0; @@ -427,7 +427,7 @@ static int pxa2xx_timer_load(QEMUFile *f, void *opaque, int version_id) return 0; } -static pxa2xx_timer_info *pxa2xx_timer_init(target_phys_addr_t base, +static pxa2xx_timer_info *pxa2xx_timer_init(a_target_phys_addr base, qemu_irq *irqs) { int i; @@ -461,14 +461,14 @@ static pxa2xx_timer_info *pxa2xx_timer_init(target_phys_addr_t base, return s; } -void pxa25x_timer_init(target_phys_addr_t base, qemu_irq *irqs) +void pxa25x_timer_init(a_target_phys_addr base, qemu_irq *irqs) { pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs); s->freq = PXA25X_FREQ; s->tm4 = NULL; } -void pxa27x_timer_init(target_phys_addr_t base, +void pxa27x_timer_init(a_target_phys_addr base, qemu_irq *irqs, qemu_irq irq4) { pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs); diff --git a/hw/qdev-addr.c b/hw/qdev-addr.c index 305c2d37b0..32922363ee 100644 --- a/hw/qdev-addr.c +++ b/hw/qdev-addr.c @@ -6,7 +6,7 @@ static int parse_taddr(DeviceState *dev, Property *prop, const char *str) { - target_phys_addr_t *ptr = qdev_get_prop_ptr(dev, prop); + a_target_phys_addr *ptr = qdev_get_prop_ptr(dev, prop); *ptr = strtoull(str, NULL, 16); return 0; @@ -14,19 +14,19 @@ static int parse_taddr(DeviceState *dev, Property *prop, const char *str) static int print_taddr(DeviceState *dev, Property *prop, char *dest, size_t len) { - target_phys_addr_t *ptr = qdev_get_prop_ptr(dev, prop); + a_target_phys_addr *ptr = qdev_get_prop_ptr(dev, prop); return snprintf(dest, len, "0x" TARGET_FMT_plx, *ptr); } PropertyInfo qdev_prop_taddr = { .name = "taddr", .type = PROP_TYPE_TADDR, - .size = sizeof(target_phys_addr_t), + .size = sizeof(a_target_phys_addr), .parse = parse_taddr, .print = print_taddr, }; -void qdev_prop_set_taddr(DeviceState *dev, const char *name, target_phys_addr_t value) +void qdev_prop_set_taddr(DeviceState *dev, const char *name, a_target_phys_addr value) { qdev_prop_set(dev, name, &value, PROP_TYPE_TADDR); } diff --git a/hw/qdev-addr.h b/hw/qdev-addr.h index a0ddf3863c..5eb45b8d2b 100644 --- a/hw/qdev-addr.h +++ b/hw/qdev-addr.h @@ -1,5 +1,5 @@ #define DEFINE_PROP_TADDR(_n, _s, _f, _d) \ - DEFINE_PROP_DEFAULT(_n, _s, _f, _d, qdev_prop_taddr, target_phys_addr_t) + DEFINE_PROP_DEFAULT(_n, _s, _f, _d, qdev_prop_taddr, a_target_phys_addr) extern PropertyInfo qdev_prop_taddr; -void qdev_prop_set_taddr(DeviceState *dev, const char *name, target_phys_addr_t value); +void qdev_prop_set_taddr(DeviceState *dev, const char *name, a_target_phys_addr value); @@ -73,7 +73,7 @@ typedef struct { /* output pin */ qemu_irq irl; -} r2d_fpga_t; +} a_r2d_fpga; enum r2d_fpga_irq { PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T, @@ -97,7 +97,7 @@ static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = { [TP] = { 12, 1<<15 }, }; -static void update_irl(r2d_fpga_t *fpga) +static void update_irl(a_r2d_fpga *fpga) { int i, irl = 15; for (i = 0; i < NR_IRQS; i++) @@ -109,7 +109,7 @@ static void update_irl(r2d_fpga_t *fpga) static void r2d_fpga_irq_set(void *opaque, int n, int level) { - r2d_fpga_t *fpga = opaque; + a_r2d_fpga *fpga = opaque; if (level) fpga->irlmon |= irqtab[n].msk; else @@ -117,9 +117,9 @@ static void r2d_fpga_irq_set(void *opaque, int n, int level) update_irl(fpga); } -static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr) +static uint32_t r2d_fpga_read(void *opaque, a_target_phys_addr addr) { - r2d_fpga_t *s = opaque; + a_r2d_fpga *s = opaque; switch (addr) { case PA_IRLMSK: @@ -136,9 +136,9 @@ static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr) } static void -r2d_fpga_write(void *opaque, target_phys_addr_t addr, uint32_t value) +r2d_fpga_write(void *opaque, a_target_phys_addr addr, uint32_t value) { - r2d_fpga_t *s = opaque; + a_r2d_fpga *s = opaque; switch (addr) { case PA_IRLMSK: @@ -169,12 +169,12 @@ static CPUWriteMemoryFunc * const r2d_fpga_writefn[] = { NULL, }; -static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl) +static qemu_irq *r2d_fpga_init(a_target_phys_addr base, qemu_irq irl) { int iomemtype; - r2d_fpga_t *s; + a_r2d_fpga *s; - s = qemu_mallocz(sizeof(r2d_fpga_t)); + s = qemu_mallocz(sizeof(a_r2d_fpga)); s->irl = irl; @@ -197,14 +197,14 @@ static int r2d_pci_map_irq(PCIDevice *d, int irq_num) return intx[d->devfn >> 3]; } -static void r2d_init(ram_addr_t ram_size, +static void r2d_init(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { CPUState *env; struct SH7750State *s; - ram_addr_t sdram_addr; + a_ram_addr sdram_addr; qemu_irq *irq; PCIBus *pci; DriveInfo *dinfo; diff --git a/hw/rc4030.c b/hw/rc4030.c index c2b2a3eb56..c86eba7c42 100644 --- a/hw/rc4030.c +++ b/hw/rc4030.c @@ -109,7 +109,7 @@ static void set_next_tick(rc4030State *s) } /* called for accesses to rc4030 */ -static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr) +static uint32_t rc4030_readl(void *opaque, a_target_phys_addr addr) { rc4030State *s = opaque; uint32_t val; @@ -246,7 +246,7 @@ static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr) return val; } -static uint32_t rc4030_readw(void *opaque, target_phys_addr_t addr) +static uint32_t rc4030_readw(void *opaque, a_target_phys_addr addr) { uint32_t v = rc4030_readl(opaque, addr & ~0x3); if (addr & 0x2) @@ -255,13 +255,13 @@ static uint32_t rc4030_readw(void *opaque, target_phys_addr_t addr) return v & 0xffff; } -static uint32_t rc4030_readb(void *opaque, target_phys_addr_t addr) +static uint32_t rc4030_readb(void *opaque, a_target_phys_addr addr) { uint32_t v = rc4030_readl(opaque, addr & ~0x3); return (v >> (8 * (addr & 0x3))) & 0xff; } -static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val) +static void rc4030_writel(void *opaque, a_target_phys_addr addr, uint32_t val) { rc4030State *s = opaque; addr &= 0x3fff; @@ -304,7 +304,7 @@ static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val) case 0x0060: /* HACK */ if (s->cache_ltag == 0x80000001 && s->cache_bmask == 0xf0f0f0f) { - target_phys_addr_t dest = s->cache_ptag & ~0x1; + a_target_phys_addr dest = s->cache_ptag & ~0x1; dest += (s->cache_maint & 0x3) << 3; cpu_physical_memory_rw(dest, (uint8_t*)&val, 4, 1); } @@ -386,7 +386,7 @@ static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val) } } -static void rc4030_writew(void *opaque, target_phys_addr_t addr, uint32_t val) +static void rc4030_writew(void *opaque, a_target_phys_addr addr, uint32_t val) { uint32_t old_val = rc4030_readl(opaque, addr & ~0x3); @@ -397,7 +397,7 @@ static void rc4030_writew(void *opaque, target_phys_addr_t addr, uint32_t val) rc4030_writel(opaque, addr & ~0x3, val); } -static void rc4030_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) +static void rc4030_writeb(void *opaque, a_target_phys_addr addr, uint32_t val) { uint32_t old_val = rc4030_readl(opaque, addr & ~0x3); @@ -479,7 +479,7 @@ static void rc4030_periodic_timer(void *opaque) qemu_irq_raise(s->timer_irq); } -static uint32_t jazzio_readw(void *opaque, target_phys_addr_t addr) +static uint32_t jazzio_readw(void *opaque, a_target_phys_addr addr) { rc4030State *s = opaque; uint32_t val; @@ -517,14 +517,14 @@ static uint32_t jazzio_readw(void *opaque, target_phys_addr_t addr) return val; } -static uint32_t jazzio_readb(void *opaque, target_phys_addr_t addr) +static uint32_t jazzio_readb(void *opaque, a_target_phys_addr addr) { uint32_t v; v = jazzio_readw(opaque, addr & ~0x1); return (v >> (8 * (addr & 0x1))) & 0xff; } -static uint32_t jazzio_readl(void *opaque, target_phys_addr_t addr) +static uint32_t jazzio_readl(void *opaque, a_target_phys_addr addr) { uint32_t v; v = jazzio_readw(opaque, addr); @@ -532,7 +532,7 @@ static uint32_t jazzio_readl(void *opaque, target_phys_addr_t addr) return v; } -static void jazzio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) +static void jazzio_writew(void *opaque, a_target_phys_addr addr, uint32_t val) { rc4030State *s = opaque; addr &= 0xfff; @@ -551,7 +551,7 @@ static void jazzio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) } } -static void jazzio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) +static void jazzio_writeb(void *opaque, a_target_phys_addr addr, uint32_t val) { uint32_t old_val = jazzio_readw(opaque, addr & ~0x1); @@ -566,7 +566,7 @@ static void jazzio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) jazzio_writew(opaque, addr & ~0x1, val); } -static void jazzio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) +static void jazzio_writel(void *opaque, a_target_phys_addr addr, uint32_t val) { jazzio_writew(opaque, addr, val & 0xffff); jazzio_writew(opaque, addr + 2, (val >> 16) & 0xffff); @@ -676,11 +676,11 @@ static void rc4030_save(QEMUFile *f, void *opaque) qemu_put_be32(f, s->itr); } -void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write) +void rc4030_dma_memory_rw(void *opaque, a_target_phys_addr addr, uint8_t *buf, int len, int is_write) { rc4030State *s = opaque; - target_phys_addr_t entry_addr; - target_phys_addr_t phys_addr; + a_target_phys_addr entry_addr; + a_target_phys_addr phys_addr; dma_pagetable_entry entry; int index; int ncpy, i; @@ -717,7 +717,7 @@ void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, i static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, int is_write) { rc4030State *s = opaque; - target_phys_addr_t dma_addr; + a_target_phys_addr dma_addr; int dev_to_mem; s->dma_regs[n][DMA_REG_ENABLE] &= ~(DMA_FLAG_TC_INTR | DMA_FLAG_MEM_INTR | DMA_FLAG_ADDR_INTR); diff --git a/hw/realview.c b/hw/realview.c index a18e7735ca..ce1f113c6b 100644 --- a/hw/realview.c +++ b/hw/realview.c @@ -24,13 +24,13 @@ static struct arm_boot_info realview_binfo = { .board_id = 0x33b, }; -static void realview_init(ram_addr_t ram_size, +static void realview_init(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { CPUState *env; - ram_addr_t ram_offset; + a_ram_addr ram_offset; DeviceState *dev; qemu_irq *irqp; qemu_irq pic[64]; diff --git a/hw/realview_gic.c b/hw/realview_gic.c index bd02b095e8..df753c022d 100644 --- a/hw/realview_gic.c +++ b/hw/realview_gic.c @@ -26,13 +26,13 @@ typedef struct { int iomemtype; } RealViewGICState; -static uint32_t realview_gic_cpu_read(void *opaque, target_phys_addr_t offset) +static uint32_t realview_gic_cpu_read(void *opaque, a_target_phys_addr offset) { gic_state *s = (gic_state *)opaque; return gic_cpu_read(s, gic_get_current_cpu(), offset); } -static void realview_gic_cpu_write(void *opaque, target_phys_addr_t offset, +static void realview_gic_cpu_write(void *opaque, a_target_phys_addr offset, uint32_t value) { gic_state *s = (gic_state *)opaque; @@ -51,7 +51,7 @@ static CPUWriteMemoryFunc * const realview_gic_cpu_writefn[] = { realview_gic_cpu_write }; -static void realview_gic_map(SysBusDevice *dev, target_phys_addr_t base) +static void realview_gic_map(SysBusDevice *dev, a_target_phys_addr base) { RealViewGICState *s = FROM_SYSBUSGIC(RealViewGICState, dev); cpu_register_physical_memory(base, 0x1000, s->iomemtype); diff --git a/hw/rtl8139.c b/hw/rtl8139.c index 83cb1ff701..abaf39d597 100644 --- a/hw/rtl8139.c +++ b/hw/rtl8139.c @@ -335,7 +335,7 @@ typedef enum { CH_8100, CH_8100B_8139D, CH_8101, -} chip_t; +} e_chip; enum chip_flags { HasHltClk = (1 << 0), @@ -414,7 +414,7 @@ typedef struct RTL8139TallyCounters static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters); /* Writes tally counters to specified physical memory address */ -static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* counters); +static void RTL8139TallyCounters_physical_memory_write(a_target_phys_addr tc_addr, RTL8139TallyCounters* counters); /* Loads values of tally counters from VM state file */ static void RTL8139TallyCounters_load(QEMUFile* f, RTL8139TallyCounters *tally_counters); @@ -781,10 +781,10 @@ static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size) } #define MIN_BUF_SIZE 60 -static inline target_phys_addr_t rtl8139_addr64(uint32_t low, uint32_t high) +static inline a_target_phys_addr rtl8139_addr64(uint32_t low, uint32_t high) { #if TARGET_PHYS_ADDR_BITS > 32 - return low | ((target_phys_addr_t)high << 32); + return low | ((a_target_phys_addr)high << 32); #else return low; #endif @@ -959,7 +959,7 @@ static ssize_t rtl8139_do_receive(VLANClientState *vc, const uint8_t *buf, size_ /* w3 high 32bit of Rx buffer ptr */ int descriptor = s->currCPlusRxDesc; - target_phys_addr_t cplus_rx_ring_desc; + a_target_phys_addr cplus_rx_ring_desc; cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI); cplus_rx_ring_desc += 16 * descriptor; @@ -1017,7 +1017,7 @@ static ssize_t rtl8139_do_receive(VLANClientState *vc, const uint8_t *buf, size_ return size_; } - target_phys_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI); + a_target_phys_addr rx_addr = rtl8139_addr64(rxbufLO, rxbufHI); /* receive/copy to target memory */ cpu_physical_memory_write( rx_addr, buf, size ); @@ -1280,7 +1280,7 @@ static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters) counters->TxUndrn = 0; } -static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* tally_counters) +static void RTL8139TallyCounters_physical_memory_write(a_target_phys_addr tc_addr, RTL8139TallyCounters* tally_counters) { uint16_t val16; uint32_t val32; @@ -1913,7 +1913,7 @@ static int rtl8139_cplus_transmit_one(RTL8139State *s) int descriptor = s->currCPlusTxDesc; - target_phys_addr_t cplus_tx_ring_desc = + a_target_phys_addr cplus_tx_ring_desc = rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]); /* Normal priority ring */ @@ -1996,7 +1996,7 @@ static int rtl8139_cplus_transmit_one(RTL8139State *s) } int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK; - target_phys_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI); + a_target_phys_addr tx_addr = rtl8139_addr64(txbufLO, txbufHI); /* make sure we have enough space to assemble the packet */ if (!s->cplus_txbuffer) @@ -2386,7 +2386,7 @@ static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32 if (descriptor == 0 && (val & 0x8)) { - target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]); + a_target_phys_addr tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]); /* dump tally counters to specified memory location */ RTL8139TallyCounters_physical_memory_write( tc_addr, &s->tally_counters); @@ -3070,12 +3070,12 @@ static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr) /* */ -static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) +static void rtl8139_mmio_writeb(void *opaque, a_target_phys_addr addr, uint32_t val) { rtl8139_io_writeb(opaque, addr & 0xFF, val); } -static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) +static void rtl8139_mmio_writew(void *opaque, a_target_phys_addr addr, uint32_t val) { #ifdef TARGET_WORDS_BIGENDIAN val = bswap16(val); @@ -3083,7 +3083,7 @@ static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t rtl8139_io_writew(opaque, addr & 0xFF, val); } -static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) +static void rtl8139_mmio_writel(void *opaque, a_target_phys_addr addr, uint32_t val) { #ifdef TARGET_WORDS_BIGENDIAN val = bswap32(val); @@ -3091,12 +3091,12 @@ static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t rtl8139_io_writel(opaque, addr & 0xFF, val); } -static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr) +static uint32_t rtl8139_mmio_readb(void *opaque, a_target_phys_addr addr) { return rtl8139_io_readb(opaque, addr & 0xFF); } -static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr) +static uint32_t rtl8139_mmio_readw(void *opaque, a_target_phys_addr addr) { uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF); #ifdef TARGET_WORDS_BIGENDIAN @@ -3105,7 +3105,7 @@ static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr) return val; } -static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr) +static uint32_t rtl8139_mmio_readl(void *opaque, a_target_phys_addr addr) { uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF); #ifdef TARGET_WORDS_BIGENDIAN @@ -54,7 +54,7 @@ static void sbi_set_irq(void *opaque, int irq, int level) { } -static uint32_t sbi_mem_readl(void *opaque, target_phys_addr_t addr) +static uint32_t sbi_mem_readl(void *opaque, a_target_phys_addr addr) { SBIState *s = opaque; uint32_t saddr, ret; @@ -70,7 +70,7 @@ static uint32_t sbi_mem_readl(void *opaque, target_phys_addr_t addr) return ret; } -static void sbi_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) +static void sbi_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val) { SBIState *s = opaque; uint32_t saddr; @@ -1,7 +1,7 @@ /* esp.c */ #define ESP_MAX_DEVS 7 typedef void (*espdma_memory_read_write)(void *opaque, uint8_t *buf, int len); -void esp_init(target_phys_addr_t espaddr, int it_shift, +void esp_init(a_target_phys_addr espaddr, int it_shift, espdma_memory_read_write dma_memory_read, espdma_memory_read_write dma_memory_write, void *dma_opaque, qemu_irq irq, qemu_irq *reset); @@ -51,7 +51,7 @@ typedef enum { sd_r6 = 6, /* Published RCA response */ sd_r7, /* Operating voltage */ sd_r1b = -1, -} sd_rsp_type_t; +} e_sd_rsp_type; struct SDState { enum { @@ -130,7 +130,7 @@ static void sd_set_status(SDState *sd) sd->card_status |= sd->state << 9; } -static const sd_cmd_type_t sd_cmd_type[64] = { +static const e_sd_cmd_type sd_cmd_type[64] = { sd_bc, sd_none, sd_bcr, sd_bcr, sd_none, sd_none, sd_none, sd_ac, sd_bcr, sd_ac, sd_ac, sd_adtc, sd_ac, sd_ac, sd_none, sd_ac, sd_ac, sd_adtc, sd_adtc, sd_none, sd_none, sd_none, sd_none, sd_none, @@ -141,7 +141,7 @@ static const sd_cmd_type_t sd_cmd_type[64] = { sd_adtc, sd_none, sd_none, sd_none, sd_none, sd_none, sd_none, sd_none, }; -static const sd_cmd_type_t sd_acmd_type[64] = { +static const e_sd_cmd_type sd_acmd_type[64] = { sd_none, sd_none, sd_none, sd_none, sd_none, sd_none, sd_ac, sd_none, sd_none, sd_none, sd_none, sd_none, sd_none, sd_adtc, sd_none, sd_none, sd_none, sd_none, sd_none, sd_none, sd_none, sd_none, sd_adtc, sd_ac, @@ -579,7 +579,7 @@ static void sd_lock_command(SDState *sd) sd->card_status &= ~CARD_IS_LOCKED; } -static sd_rsp_type_t sd_normal_command(SDState *sd, +static e_sd_rsp_type sd_normal_command(SDState *sd, SDRequest req) { uint32_t rca = 0x0000; @@ -1118,7 +1118,7 @@ static sd_rsp_type_t sd_normal_command(SDState *sd, return sd_r0; } -static sd_rsp_type_t sd_app_command(SDState *sd, +static e_sd_rsp_type sd_app_command(SDState *sd, SDRequest req) { uint32_t rca; @@ -1231,7 +1231,7 @@ static sd_rsp_type_t sd_app_command(SDState *sd, int sd_do_command(SDState *sd, SDRequest *req, uint8_t *response) { uint32_t last_status = sd->card_status; - sd_rsp_type_t rtype; + e_sd_rsp_type rtype; int rsplen; if (!sd->bdrv || !bdrv_is_inserted(sd->bdrv) || !sd->enable) { @@ -57,7 +57,7 @@ typedef enum { sd_bcr, /* broadcast with response */ sd_ac, /* addressed -- no data transfer */ sd_adtc, /* addressed with data transfer */ -} sd_cmd_type_t; +} e_sd_cmd_type; typedef struct { uint8_t cmd; diff --git a/hw/serial.c b/hw/serial.c index 6e8c6e1656..3a84219422 100644 --- a/hw/serial.c +++ b/hw/serial.c @@ -749,14 +749,14 @@ SerialState *serial_init(int base, qemu_irq irq, int baudbase, } /* Memory mapped interface */ -static uint32_t serial_mm_readb(void *opaque, target_phys_addr_t addr) +static uint32_t serial_mm_readb(void *opaque, a_target_phys_addr addr) { SerialState *s = opaque; return serial_ioport_read(s, addr >> s->it_shift) & 0xFF; } -static void serial_mm_writeb(void *opaque, target_phys_addr_t addr, +static void serial_mm_writeb(void *opaque, a_target_phys_addr addr, uint32_t value) { SerialState *s = opaque; @@ -764,7 +764,7 @@ static void serial_mm_writeb(void *opaque, target_phys_addr_t addr, serial_ioport_write(s, addr >> s->it_shift, value & 0xFF); } -static uint32_t serial_mm_readw(void *opaque, target_phys_addr_t addr) +static uint32_t serial_mm_readw(void *opaque, a_target_phys_addr addr) { SerialState *s = opaque; uint32_t val; @@ -776,7 +776,7 @@ static uint32_t serial_mm_readw(void *opaque, target_phys_addr_t addr) return val; } -static void serial_mm_writew(void *opaque, target_phys_addr_t addr, +static void serial_mm_writew(void *opaque, a_target_phys_addr addr, uint32_t value) { SerialState *s = opaque; @@ -786,7 +786,7 @@ static void serial_mm_writew(void *opaque, target_phys_addr_t addr, serial_ioport_write(s, addr >> s->it_shift, value & 0xFFFF); } -static uint32_t serial_mm_readl(void *opaque, target_phys_addr_t addr) +static uint32_t serial_mm_readl(void *opaque, a_target_phys_addr addr) { SerialState *s = opaque; uint32_t val; @@ -798,7 +798,7 @@ static uint32_t serial_mm_readl(void *opaque, target_phys_addr_t addr) return val; } -static void serial_mm_writel(void *opaque, target_phys_addr_t addr, +static void serial_mm_writel(void *opaque, a_target_phys_addr addr, uint32_t value) { SerialState *s = opaque; @@ -820,7 +820,7 @@ static CPUWriteMemoryFunc * const serial_mm_write[] = { &serial_mm_writel, }; -SerialState *serial_mm_init (target_phys_addr_t base, int it_shift, +SerialState *serial_mm_init (a_target_phys_addr base, int it_shift, qemu_irq irq, int baudbase, CharDriverState *chr, int ioregister) { @@ -30,14 +30,14 @@ int sh7750_register_io_device(struct SH7750State *s, #define TMU012_FEAT_TOCR (1 << 0) #define TMU012_FEAT_3CHAN (1 << 1) #define TMU012_FEAT_EXTCLK (1 << 2) -void tmu012_init(target_phys_addr_t base, int feat, uint32_t freq, +void tmu012_init(a_target_phys_addr base, int feat, uint32_t freq, qemu_irq ch0_irq, qemu_irq ch1_irq, qemu_irq ch2_irq0, qemu_irq ch2_irq1); /* sh_serial.c */ #define SH_SERIAL_FEAT_SCIF (1 << 0) -void sh_serial_init (target_phys_addr_t base, int feat, +void sh_serial_init (a_target_phys_addr base, int feat, uint32_t freq, CharDriverState *chr, qemu_irq eri_source, qemu_irq rxi_source, diff --git a/hw/sh7750.c b/hw/sh7750.c index 933bbc0c7a..073da28f54 100644 --- a/hw/sh7750.c +++ b/hw/sh7750.c @@ -189,19 +189,19 @@ static void portb_changed(SH7750State * s, uint16_t prev) Memory **********************************************************************/ -static void error_access(const char *kind, target_phys_addr_t addr) +static void error_access(const char *kind, a_target_phys_addr addr) { fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") not supported\n", kind, regname(addr), addr); } -static void ignore_access(const char *kind, target_phys_addr_t addr) +static void ignore_access(const char *kind, a_target_phys_addr addr) { fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") ignored\n", kind, regname(addr), addr); } -static uint32_t sh7750_mem_readb(void *opaque, target_phys_addr_t addr) +static uint32_t sh7750_mem_readb(void *opaque, a_target_phys_addr addr) { switch (addr) { default: @@ -210,7 +210,7 @@ static uint32_t sh7750_mem_readb(void *opaque, target_phys_addr_t addr) } } -static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr) +static uint32_t sh7750_mem_readw(void *opaque, a_target_phys_addr addr) { SH7750State *s = opaque; @@ -244,7 +244,7 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr) } } -static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr) +static uint32_t sh7750_mem_readl(void *opaque, a_target_phys_addr addr) { SH7750State *s = opaque; @@ -293,7 +293,7 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr) #define is_in_sdrmx(a, x) (a >= SH7750_SDMR ## x ## _A7 \ && a <= (SH7750_SDMR ## x ## _A7 + SH7750_SDMR ## x ## _REGNB)) -static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr, +static void sh7750_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t mem_value) { @@ -306,7 +306,7 @@ static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr, assert(0); } -static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr, +static void sh7750_mem_writew(void *opaque, a_target_phys_addr addr, uint32_t mem_value) { SH7750State *s = opaque; @@ -358,7 +358,7 @@ static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr, } } -static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr, +static void sh7750_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t mem_value) { SH7750State *s = opaque; @@ -613,14 +613,14 @@ static struct intc_group groups_irl[] = { #define MM_UTLB_DATA (7) #define MM_REGION_TYPE(addr) ((addr & MM_REGION_MASK) >> 24) -static uint32_t invalid_read(void *opaque, target_phys_addr_t addr) +static uint32_t invalid_read(void *opaque, a_target_phys_addr addr) { assert(0); return 0; } -static uint32_t sh7750_mmct_readl(void *opaque, target_phys_addr_t addr) +static uint32_t sh7750_mmct_readl(void *opaque, a_target_phys_addr addr) { uint32_t ret = 0; @@ -650,13 +650,13 @@ static uint32_t sh7750_mmct_readl(void *opaque, target_phys_addr_t addr) return ret; } -static void invalid_write(void *opaque, target_phys_addr_t addr, +static void invalid_write(void *opaque, a_target_phys_addr addr, uint32_t mem_value) { assert(0); } -static void sh7750_mmct_writel(void *opaque, target_phys_addr_t addr, +static void sh7750_mmct_writel(void *opaque, a_target_phys_addr addr, uint32_t mem_value) { SH7750State *s = opaque; diff --git a/hw/sh7750_regnames.c b/hw/sh7750_regnames.c index 5a5a2d80de..be278bdb01 100644 --- a/hw/sh7750_regnames.c +++ b/hw/sh7750_regnames.c @@ -8,9 +8,9 @@ typedef struct { uint32_t regaddr; const char *regname; -} regname_t; +} a_regname; -static regname_t regnames[] = { +static a_regname regnames[] = { REGNAME(SH7750_PTEH_A7) REGNAME(SH7750_PTEL_A7) REGNAME(SH7750_PTEA_A7) diff --git a/hw/sh_intc.c b/hw/sh_intc.c index b6f45f0177..ccb13c6bac 100644 --- a/hw/sh_intc.c +++ b/hw/sh_intc.c @@ -219,7 +219,7 @@ static void sh_intc_toggle_mask(struct intc_desc *desc, intc_enum id, #endif } -static uint32_t sh_intc_read(void *opaque, target_phys_addr_t offset) +static uint32_t sh_intc_read(void *opaque, a_target_phys_addr offset) { struct intc_desc *desc = opaque; intc_enum *enum_ids = NULL; @@ -237,7 +237,7 @@ static uint32_t sh_intc_read(void *opaque, target_phys_addr_t offset) return *valuep; } -static void sh_intc_write(void *opaque, target_phys_addr_t offset, +static void sh_intc_write(void *opaque, a_target_phys_addr offset, uint32_t value) { struct intc_desc *desc = opaque; diff --git a/hw/sh_pci.c b/hw/sh_pci.c index 4277b01c9f..74d748bfe7 100644 --- a/hw/sh_pci.c +++ b/hw/sh_pci.c @@ -34,7 +34,7 @@ typedef struct { uint32_t iobr; } SHPCIC; -static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val) +static void sh_pci_reg_write (void *p, a_target_phys_addr addr, uint32_t val) { SHPCIC *pcic = p; switch(addr) { @@ -56,7 +56,7 @@ static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val) } } -static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr) +static uint32_t sh_pci_reg_read (void *p, a_target_phys_addr addr) { SHPCIC *pcic = p; switch(addr) { @@ -70,79 +70,79 @@ static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr) return 0; } -static void sh_pci_data_write (SHPCIC *pcic, target_phys_addr_t addr, +static void sh_pci_data_write (SHPCIC *pcic, a_target_phys_addr addr, uint32_t val, int size) { pci_data_write(pcic->bus, addr + pcic->mbr, val, size); } -static uint32_t sh_pci_mem_read (SHPCIC *pcic, target_phys_addr_t addr, +static uint32_t sh_pci_mem_read (SHPCIC *pcic, a_target_phys_addr addr, int size) { return pci_data_read(pcic->bus, addr + pcic->mbr, size); } -static void sh_pci_writeb (void *p, target_phys_addr_t addr, uint32_t val) +static void sh_pci_writeb (void *p, a_target_phys_addr addr, uint32_t val) { sh_pci_data_write(p, addr, val, 1); } -static void sh_pci_writew (void *p, target_phys_addr_t addr, uint32_t val) +static void sh_pci_writew (void *p, a_target_phys_addr addr, uint32_t val) { sh_pci_data_write(p, addr, val, 2); } -static void sh_pci_writel (void *p, target_phys_addr_t addr, uint32_t val) +static void sh_pci_writel (void *p, a_target_phys_addr addr, uint32_t val) { sh_pci_data_write(p, addr, val, 4); } -static uint32_t sh_pci_readb (void *p, target_phys_addr_t addr) +static uint32_t sh_pci_readb (void *p, a_target_phys_addr addr) { return sh_pci_mem_read(p, addr, 1); } -static uint32_t sh_pci_readw (void *p, target_phys_addr_t addr) +static uint32_t sh_pci_readw (void *p, a_target_phys_addr addr) { return sh_pci_mem_read(p, addr, 2); } -static uint32_t sh_pci_readl (void *p, target_phys_addr_t addr) +static uint32_t sh_pci_readl (void *p, a_target_phys_addr addr) { return sh_pci_mem_read(p, addr, 4); } -static int sh_pci_addr2port(SHPCIC *pcic, target_phys_addr_t addr) +static int sh_pci_addr2port(SHPCIC *pcic, a_target_phys_addr addr) { return addr + pcic->iobr; } -static void sh_pci_outb (void *p, target_phys_addr_t addr, uint32_t val) +static void sh_pci_outb (void *p, a_target_phys_addr addr, uint32_t val) { cpu_outb(sh_pci_addr2port(p, addr), val); } -static void sh_pci_outw (void *p, target_phys_addr_t addr, uint32_t val) +static void sh_pci_outw (void *p, a_target_phys_addr addr, uint32_t val) { cpu_outw(sh_pci_addr2port(p, addr), val); } -static void sh_pci_outl (void *p, target_phys_addr_t addr, uint32_t val) +static void sh_pci_outl (void *p, a_target_phys_addr addr, uint32_t val) { cpu_outl(sh_pci_addr2port(p, addr), val); } -static uint32_t sh_pci_inb (void *p, target_phys_addr_t addr) +static uint32_t sh_pci_inb (void *p, a_target_phys_addr addr) { return cpu_inb(sh_pci_addr2port(p, addr)); } -static uint32_t sh_pci_inw (void *p, target_phys_addr_t addr) +static uint32_t sh_pci_inw (void *p, a_target_phys_addr addr) { return cpu_inw(sh_pci_addr2port(p, addr)); } -static uint32_t sh_pci_inl (void *p, target_phys_addr_t addr) +static uint32_t sh_pci_inl (void *p, a_target_phys_addr addr) { return cpu_inl(sh_pci_addr2port(p, addr)); } diff --git a/hw/sh_serial.c b/hw/sh_serial.c index 2447b919b8..e47054441d 100644 --- a/hw/sh_serial.c +++ b/hw/sh_serial.c @@ -338,14 +338,14 @@ static void sh_serial_event(void *opaque, int event) sh_serial_receive_break(s); } -static uint32_t sh_serial_read (void *opaque, target_phys_addr_t addr) +static uint32_t sh_serial_read (void *opaque, a_target_phys_addr addr) { sh_serial_state *s = opaque; return sh_serial_ioport_read(s, addr); } static void sh_serial_write (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { sh_serial_state *s = opaque; sh_serial_ioport_write(s, addr, value); @@ -363,7 +363,7 @@ static CPUWriteMemoryFunc * const sh_serial_writefn[] = { &sh_serial_write, }; -void sh_serial_init (target_phys_addr_t base, int feat, +void sh_serial_init (a_target_phys_addr base, int feat, uint32_t freq, CharDriverState *chr, qemu_irq eri_source, qemu_irq rxi_source, diff --git a/hw/sh_timer.c b/hw/sh_timer.c index fd2146a0c9..057a5076ce 100644 --- a/hw/sh_timer.c +++ b/hw/sh_timer.c @@ -57,7 +57,7 @@ static void sh_timer_update(sh_timer_state *s) s->int_level = new_level; } -static uint32_t sh_timer_read(void *opaque, target_phys_addr_t offset) +static uint32_t sh_timer_read(void *opaque, a_target_phys_addr offset) { sh_timer_state *s = (sh_timer_state *)opaque; @@ -77,7 +77,7 @@ static uint32_t sh_timer_read(void *opaque, target_phys_addr_t offset) } } -static void sh_timer_write(void *opaque, target_phys_addr_t offset, +static void sh_timer_write(void *opaque, a_target_phys_addr offset, uint32_t value) { sh_timer_state *s = (sh_timer_state *)opaque; @@ -217,7 +217,7 @@ typedef struct { int feat; } tmu012_state; -static uint32_t tmu012_read(void *opaque, target_phys_addr_t offset) +static uint32_t tmu012_read(void *opaque, a_target_phys_addr offset) { tmu012_state *s = (tmu012_state *)opaque; @@ -247,7 +247,7 @@ static uint32_t tmu012_read(void *opaque, target_phys_addr_t offset) return 0; } -static void tmu012_write(void *opaque, target_phys_addr_t offset, +static void tmu012_write(void *opaque, a_target_phys_addr offset, uint32_t value) { tmu012_state *s = (tmu012_state *)opaque; @@ -303,7 +303,7 @@ static CPUWriteMemoryFunc * const tmu012_writefn[] = { tmu012_write }; -void tmu012_init(target_phys_addr_t base, int feat, uint32_t freq, +void tmu012_init(a_target_phys_addr base, int feat, uint32_t freq, qemu_irq ch0_irq, qemu_irq ch1_irq, qemu_irq ch2_irq0, qemu_irq ch2_irq1) { diff --git a/hw/sharpsl.h b/hw/sharpsl.h index c5ccf791f6..de4b3f21cb 100644 --- a/hw/sharpsl.h +++ b/hw/sharpsl.h @@ -12,13 +12,13 @@ /* zaurus.c */ typedef struct ScoopInfo ScoopInfo; ScoopInfo *scoop_init(PXA2xxState *cpu, - int instance, target_phys_addr_t target_base); + int instance, a_target_phys_addr target_base); void scoop_gpio_set(void *opaque, int line, int level); qemu_irq *scoop_gpio_in_get(ScoopInfo *s); void scoop_gpio_out_set(ScoopInfo *s, int line, qemu_irq handler); #define SL_PXA_PARAM_BASE 0xa0000a00 -void sl_bootparam_write(target_phys_addr_t ptr); +void sl_bootparam_write(a_target_phys_addr ptr); #endif @@ -47,7 +47,7 @@ void pic_info(Monitor *mon) /* XXXXX */ } -static void shix_init(ram_addr_t ram_size, +static void shix_init(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) diff --git a/hw/slavio_intctl.c b/hw/slavio_intctl.c index 6a95f9ef7d..a26ba06005 100644 --- a/hw/slavio_intctl.c +++ b/hw/slavio_intctl.c @@ -83,7 +83,7 @@ typedef struct SLAVIO_INTCTLState { static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs); // per-cpu interrupt controller -static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr) +static uint32_t slavio_intctl_mem_readl(void *opaque, a_target_phys_addr addr) { SLAVIO_CPUINTCTLState *s = opaque; uint32_t saddr, ret; @@ -102,7 +102,7 @@ static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr) return ret; } -static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, +static void slavio_intctl_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val) { SLAVIO_CPUINTCTLState *s = opaque; @@ -143,7 +143,7 @@ static CPUWriteMemoryFunc * const slavio_intctl_mem_write[3] = { }; // master system interrupt controller -static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr) +static uint32_t slavio_intctlm_mem_readl(void *opaque, a_target_phys_addr addr) { SLAVIO_INTCTLState *s = opaque; uint32_t saddr, ret; @@ -168,7 +168,7 @@ static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr) return ret; } -static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, +static void slavio_intctlm_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val) { SLAVIO_INTCTLState *s = opaque; diff --git a/hw/slavio_misc.c b/hw/slavio_misc.c index ca95b10581..fdcdc24911 100644 --- a/hw/slavio_misc.c +++ b/hw/slavio_misc.c @@ -109,7 +109,7 @@ static void slavio_set_power_fail(void *opaque, int irq, int power_failing) slavio_misc_update_irq(s); } -static void slavio_cfg_mem_writeb(void *opaque, target_phys_addr_t addr, +static void slavio_cfg_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val) { MiscState *s = opaque; @@ -119,7 +119,7 @@ static void slavio_cfg_mem_writeb(void *opaque, target_phys_addr_t addr, slavio_misc_update_irq(s); } -static uint32_t slavio_cfg_mem_readb(void *opaque, target_phys_addr_t addr) +static uint32_t slavio_cfg_mem_readb(void *opaque, a_target_phys_addr addr) { MiscState *s = opaque; uint32_t ret = 0; @@ -141,7 +141,7 @@ static CPUWriteMemoryFunc * const slavio_cfg_mem_write[3] = { NULL, }; -static void slavio_diag_mem_writeb(void *opaque, target_phys_addr_t addr, +static void slavio_diag_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val) { MiscState *s = opaque; @@ -150,7 +150,7 @@ static void slavio_diag_mem_writeb(void *opaque, target_phys_addr_t addr, s->diag = val & 0xff; } -static uint32_t slavio_diag_mem_readb(void *opaque, target_phys_addr_t addr) +static uint32_t slavio_diag_mem_readb(void *opaque, a_target_phys_addr addr) { MiscState *s = opaque; uint32_t ret = 0; @@ -172,7 +172,7 @@ static CPUWriteMemoryFunc * const slavio_diag_mem_write[3] = { NULL, }; -static void slavio_mdm_mem_writeb(void *opaque, target_phys_addr_t addr, +static void slavio_mdm_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val) { MiscState *s = opaque; @@ -181,7 +181,7 @@ static void slavio_mdm_mem_writeb(void *opaque, target_phys_addr_t addr, s->mctrl = val & 0xff; } -static uint32_t slavio_mdm_mem_readb(void *opaque, target_phys_addr_t addr) +static uint32_t slavio_mdm_mem_readb(void *opaque, a_target_phys_addr addr) { MiscState *s = opaque; uint32_t ret = 0; @@ -203,7 +203,7 @@ static CPUWriteMemoryFunc * const slavio_mdm_mem_write[3] = { NULL, }; -static void slavio_aux1_mem_writeb(void *opaque, target_phys_addr_t addr, +static void slavio_aux1_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val) { MiscState *s = opaque; @@ -220,7 +220,7 @@ static void slavio_aux1_mem_writeb(void *opaque, target_phys_addr_t addr, s->aux1 = val & 0xff; } -static uint32_t slavio_aux1_mem_readb(void *opaque, target_phys_addr_t addr) +static uint32_t slavio_aux1_mem_readb(void *opaque, a_target_phys_addr addr) { MiscState *s = opaque; uint32_t ret = 0; @@ -243,7 +243,7 @@ static CPUWriteMemoryFunc * const slavio_aux1_mem_write[3] = { NULL, }; -static void slavio_aux2_mem_writeb(void *opaque, target_phys_addr_t addr, +static void slavio_aux2_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val) { MiscState *s = opaque; @@ -259,7 +259,7 @@ static void slavio_aux2_mem_writeb(void *opaque, target_phys_addr_t addr, slavio_misc_update_irq(s); } -static uint32_t slavio_aux2_mem_readb(void *opaque, target_phys_addr_t addr) +static uint32_t slavio_aux2_mem_readb(void *opaque, a_target_phys_addr addr) { MiscState *s = opaque; uint32_t ret = 0; @@ -282,7 +282,7 @@ static CPUWriteMemoryFunc * const slavio_aux2_mem_write[3] = { NULL, }; -static void apc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) +static void apc_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val) { APCState *s = opaque; @@ -290,7 +290,7 @@ static void apc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) qemu_irq_raise(s->cpu_halt); } -static uint32_t apc_mem_readb(void *opaque, target_phys_addr_t addr) +static uint32_t apc_mem_readb(void *opaque, a_target_phys_addr addr) { uint32_t ret = 0; @@ -310,7 +310,7 @@ static CPUWriteMemoryFunc * const apc_mem_write[3] = { NULL, }; -static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr) +static uint32_t slavio_sysctrl_mem_readl(void *opaque, a_target_phys_addr addr) { MiscState *s = opaque; uint32_t ret = 0; @@ -326,7 +326,7 @@ static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr) return ret; } -static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr, +static void slavio_sysctrl_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val) { MiscState *s = opaque; @@ -356,7 +356,7 @@ static CPUWriteMemoryFunc * const slavio_sysctrl_mem_write[3] = { slavio_sysctrl_mem_writel, }; -static uint32_t slavio_led_mem_readw(void *opaque, target_phys_addr_t addr) +static uint32_t slavio_led_mem_readw(void *opaque, a_target_phys_addr addr) { MiscState *s = opaque; uint32_t ret = 0; @@ -372,7 +372,7 @@ static uint32_t slavio_led_mem_readw(void *opaque, target_phys_addr_t addr) return ret; } -static void slavio_led_mem_writew(void *opaque, target_phys_addr_t addr, +static void slavio_led_mem_writew(void *opaque, a_target_phys_addr addr, uint32_t val) { MiscState *s = opaque; diff --git a/hw/slavio_timer.c b/hw/slavio_timer.c index b745a4b1af..e94f439cef 100644 --- a/hw/slavio_timer.c +++ b/hw/slavio_timer.c @@ -133,7 +133,7 @@ static void slavio_timer_irq(void *opaque) } } -static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr) +static uint32_t slavio_timer_mem_readl(void *opaque, a_target_phys_addr addr) { TimerContext *tc = opaque; SLAVIO_TIMERState *s = tc->s; @@ -193,7 +193,7 @@ static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr) return ret; } -static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, +static void slavio_timer_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val) { TimerContext *tc = opaque; diff --git a/hw/sm501.c b/hw/sm501.c index 612a8e5c6d..44dc301cc6 100644 --- a/hw/sm501.c +++ b/hw/sm501.c @@ -451,10 +451,10 @@ typedef struct SM501State { DisplayState *ds; /* status & internal resources */ - target_phys_addr_t base; + a_target_phys_addr base; uint32_t local_mem_size_index; uint8_t * local_mem; - ram_addr_t local_mem_offset; + a_ram_addr local_mem_offset; uint32_t last_width; uint32_t last_height; @@ -526,7 +526,7 @@ static uint32_t get_local_mem_size_index(uint32_t size) return index; } -static uint32_t sm501_system_config_read(void *opaque, target_phys_addr_t addr) +static uint32_t sm501_system_config_read(void *opaque, a_target_phys_addr addr) { SM501State * s = (SM501State *)opaque; uint32_t ret = 0; @@ -579,7 +579,7 @@ static uint32_t sm501_system_config_read(void *opaque, target_phys_addr_t addr) } static void sm501_system_config_write(void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { SM501State * s = (SM501State *)opaque; SM501_DPRINTF("sm501 system config regs : write addr=%x, val=%x\n", @@ -638,7 +638,7 @@ static CPUWriteMemoryFunc * const sm501_system_config_writefn[] = { &sm501_system_config_write, }; -static uint32_t sm501_palette_read(void *opaque, target_phys_addr_t addr) +static uint32_t sm501_palette_read(void *opaque, a_target_phys_addr addr) { SM501State * s = (SM501State *)opaque; SM501_DPRINTF("sm501 palette read addr=%x\n", (int)addr); @@ -651,7 +651,7 @@ static uint32_t sm501_palette_read(void *opaque, target_phys_addr_t addr) } static void sm501_palette_write(void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { SM501State * s = (SM501State *)opaque; SM501_DPRINTF("sm501 palette write addr=%x, val=%x\n", @@ -664,7 +664,7 @@ static void sm501_palette_write(void *opaque, *(uint32_t*)&s->dc_palette[addr] = value; } -static uint32_t sm501_disp_ctrl_read(void *opaque, target_phys_addr_t addr) +static uint32_t sm501_disp_ctrl_read(void *opaque, a_target_phys_addr addr) { SM501State * s = (SM501State *)opaque; uint32_t ret = 0; @@ -759,7 +759,7 @@ static uint32_t sm501_disp_ctrl_read(void *opaque, target_phys_addr_t addr) } static void sm501_disp_ctrl_write(void *opaque, - target_phys_addr_t addr, + a_target_phys_addr addr, uint32_t value) { SM501State * s = (SM501State *)opaque; @@ -972,7 +972,7 @@ static void sm501_draw_crt(SM501State * s) int y_start = -1; int page_min = 0x7fffffff; int page_max = -1; - ram_addr_t offset = s->local_mem_offset; + a_ram_addr offset = s->local_mem_offset; /* choose draw_line function */ switch (s->dc_crt_control & 3) { @@ -1006,9 +1006,9 @@ static void sm501_draw_crt(SM501State * s) /* draw each line according to conditions */ for (y = 0; y < height; y++) { int update = full_update; - ram_addr_t page0 = offset & TARGET_PAGE_MASK; - ram_addr_t page1 = (offset + width * src_bpp - 1) & TARGET_PAGE_MASK; - ram_addr_t page; + a_ram_addr page0 = offset & TARGET_PAGE_MASK; + a_ram_addr page1 = (offset + width * src_bpp - 1) & TARGET_PAGE_MASK; + a_ram_addr page; /* check dirty flags for each line */ for (page = page0; page <= page1; page += TARGET_PAGE_SIZE) diff --git a/hw/smc91c111.c b/hw/smc91c111.c index a08bdb0a59..bc8e6c1bec 100644 --- a/hw/smc91c111.c +++ b/hw/smc91c111.c @@ -245,7 +245,7 @@ static void smc91c111_reset(smc91c111_state *s) #define SET_LOW(name, val) s->name = (s->name & 0xff00) | val #define SET_HIGH(name, val) s->name = (s->name & 0xff) | (val << 8) -static void smc91c111_writeb(void *opaque, target_phys_addr_t offset, +static void smc91c111_writeb(void *opaque, a_target_phys_addr offset, uint32_t value) { smc91c111_state *s = (smc91c111_state *)opaque; @@ -417,7 +417,7 @@ static void smc91c111_writeb(void *opaque, target_phys_addr_t offset, hw_error("smc91c111_write: Bad reg %d:%x\n", s->bank, (int)offset); } -static uint32_t smc91c111_readb(void *opaque, target_phys_addr_t offset) +static uint32_t smc91c111_readb(void *opaque, a_target_phys_addr offset) { smc91c111_state *s = (smc91c111_state *)opaque; @@ -558,14 +558,14 @@ static uint32_t smc91c111_readb(void *opaque, target_phys_addr_t offset) return 0; } -static void smc91c111_writew(void *opaque, target_phys_addr_t offset, +static void smc91c111_writew(void *opaque, a_target_phys_addr offset, uint32_t value) { smc91c111_writeb(opaque, offset, value & 0xff); smc91c111_writeb(opaque, offset + 1, value >> 8); } -static void smc91c111_writel(void *opaque, target_phys_addr_t offset, +static void smc91c111_writel(void *opaque, a_target_phys_addr offset, uint32_t value) { /* 32-bit writes to offset 0xc only actually write to the bank select @@ -575,7 +575,7 @@ static void smc91c111_writel(void *opaque, target_phys_addr_t offset, smc91c111_writew(opaque, offset + 2, value >> 16); } -static uint32_t smc91c111_readw(void *opaque, target_phys_addr_t offset) +static uint32_t smc91c111_readw(void *opaque, a_target_phys_addr offset) { uint32_t val; val = smc91c111_readb(opaque, offset); @@ -583,7 +583,7 @@ static uint32_t smc91c111_readw(void *opaque, target_phys_addr_t offset) return val; } -static uint32_t smc91c111_readl(void *opaque, target_phys_addr_t offset) +static uint32_t smc91c111_readl(void *opaque, a_target_phys_addr offset) { uint32_t val; val = smc91c111_readw(opaque, offset); diff --git a/hw/soc_dma.c b/hw/soc_dma.c index e116e6373a..50e9957ccd 100644 --- a/hw/soc_dma.c +++ b/hw/soc_dma.c @@ -64,7 +64,7 @@ struct dma_s { struct memmap_entry_s { enum soc_dma_port_type type; - target_phys_addr_t addr; + a_target_phys_addr addr; union { struct { void *opaque; @@ -105,7 +105,7 @@ static void soc_dma_ch_run(void *opaque) } static inline struct memmap_entry_s *soc_dma_lookup(struct dma_s *dma, - target_phys_addr_t addr) + a_target_phys_addr addr) { struct memmap_entry_s *lo; int hi; @@ -254,7 +254,7 @@ struct soc_dma_s *soc_dma_init(int n) return &s->soc; } -void soc_dma_port_add_fifo(struct soc_dma_s *soc, target_phys_addr_t virt_base, +void soc_dma_port_add_fifo(struct soc_dma_s *soc, a_target_phys_addr virt_base, soc_dma_io_t fn, void *opaque, int out) { struct memmap_entry_s *entry; @@ -307,7 +307,7 @@ void soc_dma_port_add_fifo(struct soc_dma_s *soc, target_phys_addr_t virt_base, } void soc_dma_port_add_mem(struct soc_dma_s *soc, uint8_t *phys_base, - target_phys_addr_t virt_base, size_t size) + a_target_phys_addr virt_base, size_t size) { struct memmap_entry_s *entry; struct dma_s *dma = (struct dma_s *) soc; diff --git a/hw/soc_dma.h b/hw/soc_dma.h index c0ebb8d715..ad188c97c0 100644 --- a/hw/soc_dma.h +++ b/hw/soc_dma.h @@ -49,7 +49,7 @@ struct soc_dma_ch_s { int bytes; /* Initialised by the DMA module, call soc_dma_ch_update after writing. */ enum soc_dma_access_type type[2]; - target_phys_addr_t vaddr[2]; /* Updated by .transfer_fn(). */ + a_target_phys_addr vaddr[2]; /* Updated by .transfer_fn(). */ /* Private */ void *paddr[2]; soc_dma_io_t io_fn[2]; @@ -89,25 +89,25 @@ void soc_dma_ch_update(struct soc_dma_ch_s *ch); void soc_dma_reset(struct soc_dma_s *s); struct soc_dma_s *soc_dma_init(int n); -void soc_dma_port_add_fifo(struct soc_dma_s *dma, target_phys_addr_t virt_base, +void soc_dma_port_add_fifo(struct soc_dma_s *dma, a_target_phys_addr virt_base, soc_dma_io_t fn, void *opaque, int out); void soc_dma_port_add_mem(struct soc_dma_s *dma, uint8_t *phys_base, - target_phys_addr_t virt_base, size_t size); + a_target_phys_addr virt_base, size_t size); static inline void soc_dma_port_add_fifo_in(struct soc_dma_s *dma, - target_phys_addr_t virt_base, soc_dma_io_t fn, void *opaque) + a_target_phys_addr virt_base, soc_dma_io_t fn, void *opaque) { return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 0); } static inline void soc_dma_port_add_fifo_out(struct soc_dma_s *dma, - target_phys_addr_t virt_base, soc_dma_io_t fn, void *opaque) + a_target_phys_addr virt_base, soc_dma_io_t fn, void *opaque) { return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 1); } static inline void soc_dma_port_add_mem_ram(struct soc_dma_s *dma, - ram_addr_t offset, target_phys_addr_t virt_base, size_t size) + a_ram_addr offset, a_target_phys_addr virt_base, size_t size) { return soc_dma_port_add_mem(dma, qemu_get_ram_ptr(offset), virt_base, size); } diff --git a/hw/sparc32_dma.c b/hw/sparc32_dma.c index aca37706f1..1a297b939f 100644 --- a/hw/sparc32_dma.c +++ b/hw/sparc32_dma.c @@ -70,7 +70,7 @@ struct DMAState { }; /* Note: on sparc, the lance 16 bit bus is swapped */ -void ledma_memory_read(void *opaque, target_phys_addr_t addr, +void ledma_memory_read(void *opaque, a_target_phys_addr addr, uint8_t *buf, int len, int do_bswap) { DMAState *s = opaque; @@ -91,7 +91,7 @@ void ledma_memory_read(void *opaque, target_phys_addr_t addr, } } -void ledma_memory_write(void *opaque, target_phys_addr_t addr, +void ledma_memory_write(void *opaque, a_target_phys_addr addr, uint8_t *buf, int len, int do_bswap) { DMAState *s = opaque; @@ -157,7 +157,7 @@ void espdma_memory_write(void *opaque, uint8_t *buf, int len) s->dmaregs[1] += len; } -static uint32_t dma_mem_readl(void *opaque, target_phys_addr_t addr) +static uint32_t dma_mem_readl(void *opaque, a_target_phys_addr addr) { DMAState *s = opaque; uint32_t saddr; @@ -169,7 +169,7 @@ static uint32_t dma_mem_readl(void *opaque, target_phys_addr_t addr) return s->dmaregs[saddr]; } -static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) +static void dma_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val) { DMAState *s = opaque; uint32_t saddr; diff --git a/hw/sparc32_dma.h b/hw/sparc32_dma.h index 8b72c37a98..050bf2adc9 100644 --- a/hw/sparc32_dma.h +++ b/hw/sparc32_dma.h @@ -2,9 +2,9 @@ #define SPARC32_DMA_H /* sparc32_dma.c */ -void ledma_memory_read(void *opaque, target_phys_addr_t addr, +void ledma_memory_read(void *opaque, a_target_phys_addr addr, uint8_t *buf, int len, int do_bswap); -void ledma_memory_write(void *opaque, target_phys_addr_t addr, +void ledma_memory_write(void *opaque, a_target_phys_addr addr, uint8_t *buf, int len, int do_bswap); void espdma_memory_read(void *opaque, uint8_t *buf, int len); void espdma_memory_write(void *opaque, uint8_t *buf, int len); diff --git a/hw/spitz.c b/hw/spitz.c index 564519b2c7..48409a66f8 100644 --- a/hw/spitz.c +++ b/hw/spitz.c @@ -50,7 +50,7 @@ typedef struct { ECCState ecc; } SLNANDState; -static uint32_t sl_readb(void *opaque, target_phys_addr_t addr) +static uint32_t sl_readb(void *opaque, a_target_phys_addr addr) { SLNANDState *s = (SLNANDState *) opaque; int ryby; @@ -88,7 +88,7 @@ static uint32_t sl_readb(void *opaque, target_phys_addr_t addr) return 0; } -static uint32_t sl_readl(void *opaque, target_phys_addr_t addr) +static uint32_t sl_readl(void *opaque, a_target_phys_addr addr) { SLNANDState *s = (SLNANDState *) opaque; @@ -99,7 +99,7 @@ static uint32_t sl_readl(void *opaque, target_phys_addr_t addr) return sl_readb(opaque, addr); } -static void sl_writeb(void *opaque, target_phys_addr_t addr, +static void sl_writeb(void *opaque, a_target_phys_addr addr, uint32_t value) { SLNANDState *s = (SLNANDState *) opaque; @@ -948,7 +948,7 @@ static struct arm_boot_info spitz_binfo = { .ram_size = 0x04000000, }; -static void spitz_common_init(ram_addr_t ram_size, +static void spitz_common_init(a_ram_addr ram_size, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model, enum spitz_model_e model, int arm_id) @@ -1004,7 +1004,7 @@ static void spitz_common_init(ram_addr_t ram_size, sl_bootparam_write(SL_PXA_PARAM_BASE); } -static void spitz_init(ram_addr_t ram_size, +static void spitz_init(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -1013,7 +1013,7 @@ static void spitz_init(ram_addr_t ram_size, kernel_cmdline, initrd_filename, cpu_model, spitz, 0x2c9); } -static void borzoi_init(ram_addr_t ram_size, +static void borzoi_init(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -1022,7 +1022,7 @@ static void borzoi_init(ram_addr_t ram_size, kernel_cmdline, initrd_filename, cpu_model, borzoi, 0x33f); } -static void akita_init(ram_addr_t ram_size, +static void akita_init(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -1031,7 +1031,7 @@ static void akita_init(ram_addr_t ram_size, kernel_cmdline, initrd_filename, cpu_model, akita, 0x2e8); } -static void terrier_init(ram_addr_t ram_size, +static void terrier_init(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) diff --git a/hw/stellaris.c b/hw/stellaris.c index bcde0a2977..3fd9300e48 100644 --- a/hw/stellaris.c +++ b/hw/stellaris.c @@ -140,7 +140,7 @@ static void gptm_tick(void *opaque) gptm_update_irq(s); } -static uint32_t gptm_read(void *opaque, target_phys_addr_t offset) +static uint32_t gptm_read(void *opaque, a_target_phys_addr offset) { gptm_state *s = (gptm_state *)opaque; @@ -188,7 +188,7 @@ static uint32_t gptm_read(void *opaque, target_phys_addr_t offset) } } -static void gptm_write(void *opaque, target_phys_addr_t offset, uint32_t value) +static void gptm_write(void *opaque, a_target_phys_addr offset, uint32_t value) { gptm_state *s = (gptm_state *)opaque; uint32_t oldval; @@ -422,7 +422,7 @@ static uint32_t pllcfg_fury[16] = { 0xb11c /* 8.192 Mhz */ }; -static uint32_t ssys_read(void *opaque, target_phys_addr_t offset) +static uint32_t ssys_read(void *opaque, a_target_phys_addr offset) { ssys_state *s = (ssys_state *)opaque; @@ -508,7 +508,7 @@ static void ssys_calculate_system_clock(ssys_state *s) system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1); } -static void ssys_write(void *opaque, target_phys_addr_t offset, uint32_t value) +static void ssys_write(void *opaque, a_target_phys_addr offset, uint32_t value) { ssys_state *s = (ssys_state *)opaque; @@ -701,7 +701,7 @@ typedef struct { #define STELLARIS_I2C_MCS_IDLE 0x20 #define STELLARIS_I2C_MCS_BUSBSY 0x40 -static uint32_t stellaris_i2c_read(void *opaque, target_phys_addr_t offset) +static uint32_t stellaris_i2c_read(void *opaque, a_target_phys_addr offset) { stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; @@ -737,7 +737,7 @@ static void stellaris_i2c_update(stellaris_i2c_state *s) qemu_set_irq(s->irq, level); } -static void stellaris_i2c_write(void *opaque, target_phys_addr_t offset, +static void stellaris_i2c_write(void *opaque, a_target_phys_addr offset, uint32_t value) { stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; @@ -1009,7 +1009,7 @@ static void stellaris_adc_reset(stellaris_adc_state *s) } } -static uint32_t stellaris_adc_read(void *opaque, target_phys_addr_t offset) +static uint32_t stellaris_adc_read(void *opaque, a_target_phys_addr offset) { stellaris_adc_state *s = (stellaris_adc_state *)opaque; @@ -1056,7 +1056,7 @@ static uint32_t stellaris_adc_read(void *opaque, target_phys_addr_t offset) } } -static void stellaris_adc_write(void *opaque, target_phys_addr_t offset, +static void stellaris_adc_write(void *opaque, a_target_phys_addr offset, uint32_t value) { stellaris_adc_state *s = (stellaris_adc_state *)opaque; @@ -1412,7 +1412,7 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model, } /* FIXME: Figure out how to generate these from stellaris_boards. */ -static void lm3s811evb_init(ram_addr_t ram_size, +static void lm3s811evb_init(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -1420,7 +1420,7 @@ static void lm3s811evb_init(ram_addr_t ram_size, stellaris_init(kernel_filename, cpu_model, &stellaris_boards[0]); } -static void lm3s6965evb_init(ram_addr_t ram_size, +static void lm3s6965evb_init(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) diff --git a/hw/stellaris_enet.c b/hw/stellaris_enet.c index 4596a699e0..4143b0e124 100644 --- a/hw/stellaris_enet.c +++ b/hw/stellaris_enet.c @@ -130,7 +130,7 @@ static int stellaris_enet_can_receive(VLANClientState *vc) return (s->np < 31); } -static uint32_t stellaris_enet_read(void *opaque, target_phys_addr_t offset) +static uint32_t stellaris_enet_read(void *opaque, a_target_phys_addr offset) { stellaris_enet_state *s = (stellaris_enet_state *)opaque; uint32_t val; @@ -197,7 +197,7 @@ static uint32_t stellaris_enet_read(void *opaque, target_phys_addr_t offset) } } -static void stellaris_enet_write(void *opaque, target_phys_addr_t offset, +static void stellaris_enet_write(void *opaque, a_target_phys_addr offset, uint32_t value) { stellaris_enet_state *s = (stellaris_enet_state *)opaque; diff --git a/hw/sun4c_intctl.c b/hw/sun4c_intctl.c index c0211370a7..e4174f0de8 100644 --- a/hw/sun4c_intctl.c +++ b/hw/sun4c_intctl.c @@ -60,7 +60,7 @@ typedef struct Sun4c_INTCTLState { static void sun4c_check_interrupts(void *opaque); -static uint32_t sun4c_intctl_mem_readb(void *opaque, target_phys_addr_t addr) +static uint32_t sun4c_intctl_mem_readb(void *opaque, a_target_phys_addr addr) { Sun4c_INTCTLState *s = opaque; uint32_t ret; @@ -71,7 +71,7 @@ static uint32_t sun4c_intctl_mem_readb(void *opaque, target_phys_addr_t addr) return ret; } -static void sun4c_intctl_mem_writeb(void *opaque, target_phys_addr_t addr, +static void sun4c_intctl_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val) { Sun4c_INTCTLState *s = opaque; diff --git a/hw/sun4m.c b/hw/sun4m.c index a869d15a81..1e7a7a9011 100644 --- a/hw/sun4m.c +++ b/hw/sun4m.c @@ -92,12 +92,12 @@ #define ESCC_CLOCK 4915200 struct sun4m_hwdef { - target_phys_addr_t iommu_base, slavio_base; - target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; - target_phys_addr_t serial_base, fd_base; - target_phys_addr_t idreg_base, dma_base, esp_base, le_base; - target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base; - target_phys_addr_t ecc_base; + a_target_phys_addr iommu_base, slavio_base; + a_target_phys_addr intctl_base, counter_base, nvram_base, ms_kb_base; + a_target_phys_addr serial_base, fd_base; + a_target_phys_addr idreg_base, dma_base, esp_base, le_base; + a_target_phys_addr tcx_base, cs_base, apc_base, aux1_base, aux2_base; + a_target_phys_addr ecc_base; uint32_t ecc_version; uint8_t nvram_machine_id; uint16_t machine_id; @@ -109,13 +109,13 @@ struct sun4m_hwdef { #define MAX_IOUNITS 5 struct sun4d_hwdef { - target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base; - target_phys_addr_t counter_base, nvram_base, ms_kb_base; - target_phys_addr_t serial_base; - target_phys_addr_t espdma_base, esp_base; - target_phys_addr_t ledma_base, le_base; - target_phys_addr_t tcx_base; - target_phys_addr_t sbi_base; + a_target_phys_addr iounit_bases[MAX_IOUNITS], slavio_base; + a_target_phys_addr counter_base, nvram_base, ms_kb_base; + a_target_phys_addr serial_base; + a_target_phys_addr espdma_base, esp_base; + a_target_phys_addr ledma_base, le_base; + a_target_phys_addr tcx_base; + a_target_phys_addr sbi_base; uint8_t nvram_machine_id; uint16_t machine_id; uint32_t iounit_version; @@ -124,11 +124,11 @@ struct sun4d_hwdef { }; struct sun4c_hwdef { - target_phys_addr_t iommu_base, slavio_base; - target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; - target_phys_addr_t serial_base, fd_base; - target_phys_addr_t idreg_base, dma_base, esp_base, le_base; - target_phys_addr_t tcx_base, aux1_base; + a_target_phys_addr iommu_base, slavio_base; + a_target_phys_addr intctl_base, counter_base, nvram_base, ms_kb_base; + a_target_phys_addr serial_base, fd_base; + a_target_phys_addr idreg_base, dma_base, esp_base, le_base; + a_target_phys_addr tcx_base, aux1_base; uint8_t nvram_machine_id; uint16_t machine_id; uint32_t iommu_version; @@ -164,8 +164,8 @@ static int fw_cfg_boot_set(void *opaque, const char *boot_device) return 0; } -static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline, - const char *boot_devices, ram_addr_t RAM_size, +static void nvram_init(a_m48t59 *nvram, uint8_t *macaddr, const char *cmdline, + const char *boot_devices, a_ram_addr RAM_size, uint32_t kernel_size, int width, int height, int depth, int nvram_machine_id, const char *arch) @@ -294,7 +294,7 @@ static void cpu_halt_signal(void *opaque, int irq, int level) static unsigned long sun4m_load_kernel(const char *kernel_filename, const char *initrd_filename, - ram_addr_t RAM_size) + a_ram_addr RAM_size) { int linux_boot; unsigned int i; @@ -352,7 +352,7 @@ static unsigned long sun4m_load_kernel(const char *kernel_filename, return kernel_size; } -static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq) +static void *iommu_init(a_target_phys_addr addr, uint32_t version, qemu_irq irq) { DeviceState *dev; SysBusDevice *s; @@ -367,7 +367,7 @@ static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq) return s; } -static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq, +static void *sparc32_dma_init(a_target_phys_addr daddr, qemu_irq parent_irq, void *iommu, qemu_irq *dev_irq) { DeviceState *dev; @@ -384,7 +384,7 @@ static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq, return s; } -static void lance_init(NICInfo *nd, target_phys_addr_t leaddr, +static void lance_init(NICInfo *nd, a_target_phys_addr leaddr, void *dma_opaque, qemu_irq irq) { DeviceState *dev; @@ -404,8 +404,8 @@ static void lance_init(NICInfo *nd, target_phys_addr_t leaddr, qdev_connect_gpio_out(dma_opaque, 0, reset); } -static DeviceState *slavio_intctl_init(target_phys_addr_t addr, - target_phys_addr_t addrg, +static DeviceState *slavio_intctl_init(a_target_phys_addr addr, + a_target_phys_addr addrg, qemu_irq **parent_irq) { DeviceState *dev; @@ -433,7 +433,7 @@ static DeviceState *slavio_intctl_init(target_phys_addr_t addr, #define SYS_TIMER_OFFSET 0x10000ULL #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) -static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq, +static void slavio_timer_init_all(a_target_phys_addr addr, qemu_irq master_irq, qemu_irq *cpu_irqs, unsigned int num_cpus) { DeviceState *dev; @@ -448,7 +448,7 @@ static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq, sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); for (i = 0; i < MAX_CPUS; i++) { - sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i)); + sysbus_mmio_map(s, i + 1, addr + (a_target_phys_addr)CPU_TIMER_OFFSET(i)); sysbus_connect_irq(s, i + 1, cpu_irqs[i]); } } @@ -459,9 +459,9 @@ static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq, #define MISC_MDM 0x01b00000 #define MISC_SYS 0x01f00000 -static void slavio_misc_init(target_phys_addr_t base, - target_phys_addr_t aux1_base, - target_phys_addr_t aux2_base, qemu_irq irq, +static void slavio_misc_init(a_target_phys_addr base, + a_target_phys_addr aux1_base, + a_target_phys_addr aux2_base, qemu_irq irq, qemu_irq fdc_tc) { DeviceState *dev; @@ -498,7 +498,7 @@ static void slavio_misc_init(target_phys_addr_t base, qemu_system_powerdown = qdev_get_gpio_in(dev, 0); } -static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version) +static void ecc_init(a_target_phys_addr base, qemu_irq irq, uint32_t version) { DeviceState *dev; SysBusDevice *s; @@ -514,7 +514,7 @@ static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version) } } -static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt) +static void apc_init(a_target_phys_addr power_base, qemu_irq cpu_halt) { DeviceState *dev; SysBusDevice *s; @@ -527,7 +527,7 @@ static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt) sysbus_connect_irq(s, 0, cpu_halt); } -static void tcx_init(target_phys_addr_t addr, int vram_size, int width, +static void tcx_init(a_target_phys_addr addr, int vram_size, int width, int height, int depth) { DeviceState *dev; @@ -563,7 +563,7 @@ static void tcx_init(target_phys_addr_t addr, int vram_size, int width, /* NCR89C100/MACIO Internal ID register */ static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; -static void idreg_init(target_phys_addr_t addr) +static void idreg_init(a_target_phys_addr addr) { DeviceState *dev; SysBusDevice *s; @@ -578,7 +578,7 @@ static void idreg_init(target_phys_addr_t addr) static int idreg_init1(SysBusDevice *dev) { - ram_addr_t idreg_offset; + a_ram_addr idreg_offset; idreg_offset = qemu_ram_alloc(sizeof(idreg_data)); sysbus_init_mmio(dev, sizeof(idreg_data), idreg_offset | IO_MEM_ROM); @@ -599,7 +599,7 @@ static void idreg_register_devices(void) device_init(idreg_register_devices); /* Boot PROM (OpenBIOS) */ -static void prom_init(target_phys_addr_t addr, const char *bios_name) +static void prom_init(a_target_phys_addr addr, const char *bios_name) { DeviceState *dev; SysBusDevice *s; @@ -635,7 +635,7 @@ static void prom_init(target_phys_addr_t addr, const char *bios_name) static int prom_init1(SysBusDevice *dev) { - ram_addr_t prom_offset; + a_ram_addr prom_offset; prom_offset = qemu_ram_alloc(PROM_SIZE_MAX); sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM); @@ -667,7 +667,7 @@ typedef struct RamDevice /* System RAM */ static int ram_init1(SysBusDevice *dev) { - ram_addr_t RAM_size, ram_offset; + a_ram_addr RAM_size, ram_offset; RamDevice *d = FROM_SYSBUS(RamDevice, dev); RAM_size = d->size; @@ -677,7 +677,7 @@ static int ram_init1(SysBusDevice *dev) return 0; } -static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size, +static void ram_init(a_target_phys_addr addr, a_ram_addr RAM_size, uint64_t max_mem) { DeviceState *dev; @@ -743,7 +743,7 @@ static CPUState *cpu_devinit(const char *cpu_model, unsigned int id, return env; } -static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size, +static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, a_ram_addr RAM_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, @@ -1129,7 +1129,7 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { }; /* SPARCstation 5 hardware initialisation */ -static void ss5_init(ram_addr_t RAM_size, +static void ss5_init(a_ram_addr RAM_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -1139,7 +1139,7 @@ static void ss5_init(ram_addr_t RAM_size, } /* SPARCstation 10 hardware initialisation */ -static void ss10_init(ram_addr_t RAM_size, +static void ss10_init(a_ram_addr RAM_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -1149,7 +1149,7 @@ static void ss10_init(ram_addr_t RAM_size, } /* SPARCserver 600MP hardware initialisation */ -static void ss600mp_init(ram_addr_t RAM_size, +static void ss600mp_init(a_ram_addr RAM_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, @@ -1160,7 +1160,7 @@ static void ss600mp_init(ram_addr_t RAM_size, } /* SPARCstation 20 hardware initialisation */ -static void ss20_init(ram_addr_t RAM_size, +static void ss20_init(a_ram_addr RAM_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -1170,7 +1170,7 @@ static void ss20_init(ram_addr_t RAM_size, } /* SPARCstation Voyager hardware initialisation */ -static void vger_init(ram_addr_t RAM_size, +static void vger_init(a_ram_addr RAM_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -1180,7 +1180,7 @@ static void vger_init(ram_addr_t RAM_size, } /* SPARCstation LX hardware initialisation */ -static void ss_lx_init(ram_addr_t RAM_size, +static void ss_lx_init(a_ram_addr RAM_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -1190,7 +1190,7 @@ static void ss_lx_init(ram_addr_t RAM_size, } /* SPARCstation 4 hardware initialisation */ -static void ss4_init(ram_addr_t RAM_size, +static void ss4_init(a_ram_addr RAM_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -1200,7 +1200,7 @@ static void ss4_init(ram_addr_t RAM_size, } /* SPARCClassic hardware initialisation */ -static void scls_init(ram_addr_t RAM_size, +static void scls_init(a_ram_addr RAM_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -1210,7 +1210,7 @@ static void scls_init(ram_addr_t RAM_size, } /* SPARCbook hardware initialisation */ -static void sbook_init(ram_addr_t RAM_size, +static void sbook_init(a_ram_addr RAM_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -1341,7 +1341,7 @@ static const struct sun4d_hwdef sun4d_hwdefs[] = { }, }; -static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq) +static DeviceState *sbi_init(a_target_phys_addr addr, qemu_irq **parent_irq) { DeviceState *dev; SysBusDevice *s; @@ -1361,7 +1361,7 @@ static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq) return dev; } -static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, +static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, a_ram_addr RAM_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, @@ -1403,7 +1403,7 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, } for (i = 0; i < MAX_IOUNITS; i++) - if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1) + if (hwdef->iounit_bases[i] != (a_target_phys_addr)-1) iounits[i] = iommu_init(hwdef->iounit_bases[i], hwdef->iounit_version, sbi_irq[0]); @@ -1472,7 +1472,7 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, } /* SPARCserver 1000 hardware initialisation */ -static void ss1000_init(ram_addr_t RAM_size, +static void ss1000_init(a_ram_addr RAM_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -1482,7 +1482,7 @@ static void ss1000_init(ram_addr_t RAM_size, } /* SPARCcenter 2000 hardware initialisation */ -static void ss2000_init(ram_addr_t RAM_size, +static void ss2000_init(a_ram_addr RAM_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -1530,7 +1530,7 @@ static const struct sun4c_hwdef sun4c_hwdefs[] = { }, }; -static DeviceState *sun4c_intctl_init(target_phys_addr_t addr, +static DeviceState *sun4c_intctl_init(a_target_phys_addr addr, qemu_irq *parent_irq) { DeviceState *dev; @@ -1550,7 +1550,7 @@ static DeviceState *sun4c_intctl_init(target_phys_addr_t addr, return dev; } -static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size, +static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, a_ram_addr RAM_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, @@ -1615,7 +1615,7 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size, slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc); - if (hwdef->fd_base != (target_phys_addr_t)-1) { + if (hwdef->fd_base != (a_target_phys_addr)-1) { /* there is zero or one floppy drive */ memset(fd, 0, sizeof(fd)); dinfo = drive_get(IF_FLOPPY, 0, 0); @@ -1664,7 +1664,7 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size, } /* SPARCstation 2 hardware initialisation */ -static void ss2_init(ram_addr_t RAM_size, +static void ss2_init(a_ram_addr RAM_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) diff --git a/hw/sun4m.h b/hw/sun4m.h index ce97ee5a79..694ef8b73f 100644 --- a/hw/sun4m.h +++ b/hw/sun4m.h @@ -6,17 +6,17 @@ /* Devices used by sparc32 system. */ /* iommu.c */ -void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr, +void sparc_iommu_memory_rw(void *opaque, a_target_phys_addr addr, uint8_t *buf, int len, int is_write); static inline void sparc_iommu_memory_read(void *opaque, - target_phys_addr_t addr, + a_target_phys_addr addr, uint8_t *buf, int len) { sparc_iommu_memory_rw(opaque, addr, buf, len, 0); } static inline void sparc_iommu_memory_write(void *opaque, - target_phys_addr_t addr, + a_target_phys_addr addr, uint8_t *buf, int len) { sparc_iommu_memory_rw(opaque, addr, buf, len, 1); diff --git a/hw/sun4u.c b/hw/sun4u.c index 2c97d9d702..d9ad12b78b 100644 --- a/hw/sun4u.c +++ b/hw/sun4u.c @@ -102,9 +102,9 @@ static int fw_cfg_boot_set(void *opaque, const char *boot_device) return 0; } -static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size, +static int sun4u_NVRAM_set_params (a_m48t59 *nvram, uint16_t NVRAM_size, const char *arch, - ram_addr_t RAM_size, + a_ram_addr RAM_size, const char *boot_devices, uint32_t kernel_image, uint32_t kernel_size, const char *cmdline, @@ -156,7 +156,7 @@ static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size, } static unsigned long sun4u_load_kernel(const char *kernel_filename, const char *initrd_filename, - ram_addr_t RAM_size, long *initrd_size) + a_ram_addr RAM_size, long *initrd_size) { int linux_boot; unsigned int i; @@ -410,7 +410,7 @@ static void pci_ebus_register(void) device_init(pci_ebus_register); /* Boot PROM (OpenBIOS) */ -static void prom_init(target_phys_addr_t addr, const char *bios_name) +static void prom_init(a_target_phys_addr addr, const char *bios_name) { DeviceState *dev; SysBusDevice *s; @@ -446,7 +446,7 @@ static void prom_init(target_phys_addr_t addr, const char *bios_name) static int prom_init1(SysBusDevice *dev) { - ram_addr_t prom_offset; + a_ram_addr prom_offset; prom_offset = qemu_ram_alloc(PROM_SIZE_MAX); sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM); @@ -479,7 +479,7 @@ typedef struct RamDevice /* System RAM */ static int ram_init1(SysBusDevice *dev) { - ram_addr_t RAM_size, ram_offset; + a_ram_addr RAM_size, ram_offset; RamDevice *d = FROM_SYSBUS(RamDevice, dev); RAM_size = d->size; @@ -489,7 +489,7 @@ static int ram_init1(SysBusDevice *dev) return 0; } -static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size) +static void ram_init(a_target_phys_addr addr, a_ram_addr RAM_size) { DeviceState *dev; SysBusDevice *s; @@ -560,14 +560,14 @@ static CPUState *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef) return env; } -static void sun4uv_init(ram_addr_t RAM_size, +static void sun4uv_init(a_ram_addr RAM_size, const char *boot_devices, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model, const struct hwdef *hwdef) { CPUState *env; - m48t59_t *nvram; + a_m48t59 *nvram; unsigned int i; long initrd_size, kernel_size; PCIBus *pci_bus, *pci_bus2, *pci_bus3; @@ -704,7 +704,7 @@ static const struct hwdef hwdefs[] = { }; /* Sun4u hardware initialisation */ -static void sun4u_init(ram_addr_t RAM_size, +static void sun4u_init(a_ram_addr RAM_size, const char *boot_devices, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -714,7 +714,7 @@ static void sun4u_init(ram_addr_t RAM_size, } /* Sun4v hardware initialisation */ -static void sun4v_init(ram_addr_t RAM_size, +static void sun4v_init(a_ram_addr RAM_size, const char *boot_devices, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -724,7 +724,7 @@ static void sun4v_init(ram_addr_t RAM_size, } /* Niagara hardware initialisation */ -static void niagara_init(ram_addr_t RAM_size, +static void niagara_init(a_ram_addr RAM_size, const char *boot_devices, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) diff --git a/hw/syborg.c b/hw/syborg.c index d8d38d48e4..a4c3039b15 100644 --- a/hw/syborg.c +++ b/hw/syborg.c @@ -30,7 +30,7 @@ static struct arm_boot_info syborg_binfo; -static void syborg_init(ram_addr_t ram_size, +static void syborg_init(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -38,7 +38,7 @@ static void syborg_init(ram_addr_t ram_size, CPUState *env; qemu_irq *cpu_pic; qemu_irq pic[64]; - ram_addr_t ram_addr; + a_ram_addr ram_addr; DeviceState *dev; int i; diff --git a/hw/syborg_fb.c b/hw/syborg_fb.c index 7be04a3526..766aa1af8f 100644 --- a/hw/syborg_fb.c +++ b/hw/syborg_fb.c @@ -285,7 +285,7 @@ static void syborg_fb_invalidate_display(void * opaque) s->need_update = 1; } -static uint32_t syborg_fb_read(void *opaque, target_phys_addr_t offset) +static uint32_t syborg_fb_read(void *opaque, a_target_phys_addr offset) { SyborgFBState *s = opaque; @@ -356,7 +356,7 @@ static uint32_t syborg_fb_read(void *opaque, target_phys_addr_t offset) } } -static void syborg_fb_write(void *opaque, target_phys_addr_t offset, +static void syborg_fb_write(void *opaque, a_target_phys_addr offset, uint32_t val) { SyborgFBState *s = opaque; diff --git a/hw/syborg_interrupt.c b/hw/syborg_interrupt.c index f3a1767296..ec95bfcc65 100644 --- a/hw/syborg_interrupt.c +++ b/hw/syborg_interrupt.c @@ -84,7 +84,7 @@ static void syborg_int_set_irq(void *opaque, int irq, int level) } } -static uint32_t syborg_int_read(void *opaque, target_phys_addr_t offset) +static uint32_t syborg_int_read(void *opaque, a_target_phys_addr offset) { SyborgIntState *s = (SyborgIntState *)opaque; int i; @@ -114,7 +114,7 @@ static uint32_t syborg_int_read(void *opaque, target_phys_addr_t offset) } } -static void syborg_int_write(void *opaque, target_phys_addr_t offset, uint32_t value) +static void syborg_int_write(void *opaque, a_target_phys_addr offset, uint32_t value) { SyborgIntState *s = (SyborgIntState *)opaque; int i; diff --git a/hw/syborg_keyboard.c b/hw/syborg_keyboard.c index 4a562f85de..01f6c7ef27 100644 --- a/hw/syborg_keyboard.c +++ b/hw/syborg_keyboard.c @@ -66,7 +66,7 @@ static void syborg_keyboard_update(SyborgKeyboardState *s) qemu_set_irq(s->irq, level); } -static uint32_t syborg_keyboard_read(void *opaque, target_phys_addr_t offset) +static uint32_t syborg_keyboard_read(void *opaque, a_target_phys_addr offset) { SyborgKeyboardState *s = (SyborgKeyboardState *)opaque; int c; @@ -103,7 +103,7 @@ static uint32_t syborg_keyboard_read(void *opaque, target_phys_addr_t offset) } } -static void syborg_keyboard_write(void *opaque, target_phys_addr_t offset, +static void syborg_keyboard_write(void *opaque, a_target_phys_addr offset, uint32_t value) { SyborgKeyboardState *s = (SyborgKeyboardState *)opaque; diff --git a/hw/syborg_pointer.c b/hw/syborg_pointer.c index 563d73067d..68a9a95cc5 100644 --- a/hw/syborg_pointer.c +++ b/hw/syborg_pointer.c @@ -57,7 +57,7 @@ static void syborg_pointer_update(SyborgPointerState *s) qemu_set_irq(s->irq, s->read_count && s->int_enabled); } -static uint32_t syborg_pointer_read(void *opaque, target_phys_addr_t offset) +static uint32_t syborg_pointer_read(void *opaque, a_target_phys_addr offset) { SyborgPointerState *s = (SyborgPointerState *)opaque; @@ -86,7 +86,7 @@ static uint32_t syborg_pointer_read(void *opaque, target_phys_addr_t offset) } } -static void syborg_pointer_write(void *opaque, target_phys_addr_t offset, +static void syborg_pointer_write(void *opaque, a_target_phys_addr offset, uint32_t value) { SyborgPointerState *s = (SyborgPointerState *)opaque; diff --git a/hw/syborg_rtc.c b/hw/syborg_rtc.c index b066213533..dc16ac6e3b 100644 --- a/hw/syborg_rtc.c +++ b/hw/syborg_rtc.c @@ -40,7 +40,7 @@ typedef struct { qemu_irq irq; } SyborgRTCState; -static uint32_t syborg_rtc_read(void *opaque, target_phys_addr_t offset) +static uint32_t syborg_rtc_read(void *opaque, a_target_phys_addr offset) { SyborgRTCState *s = (SyborgRTCState *)opaque; offset &= 0xfff; @@ -58,7 +58,7 @@ static uint32_t syborg_rtc_read(void *opaque, target_phys_addr_t offset) } } -static void syborg_rtc_write(void *opaque, target_phys_addr_t offset, uint32_t value) +static void syborg_rtc_write(void *opaque, a_target_phys_addr offset, uint32_t value) { SyborgRTCState *s = (SyborgRTCState *)opaque; uint64_t now; diff --git a/hw/syborg_serial.c b/hw/syborg_serial.c index cac00eac09..0b226e2321 100644 --- a/hw/syborg_serial.c +++ b/hw/syborg_serial.c @@ -152,7 +152,7 @@ static void dma_rx_start(SyborgSerialState *s, uint32_t len) syborg_serial_update(s); } -static uint32_t syborg_serial_read(void *opaque, target_phys_addr_t offset) +static uint32_t syborg_serial_read(void *opaque, a_target_phys_addr offset) { SyborgSerialState *s = (SyborgSerialState *)opaque; uint32_t c; @@ -191,7 +191,7 @@ static uint32_t syborg_serial_read(void *opaque, target_phys_addr_t offset) } } -static void syborg_serial_write(void *opaque, target_phys_addr_t offset, +static void syborg_serial_write(void *opaque, a_target_phys_addr offset, uint32_t value) { SyborgSerialState *s = (SyborgSerialState *)opaque; diff --git a/hw/syborg_timer.c b/hw/syborg_timer.c index 3e4a447610..08ab8cec6b 100644 --- a/hw/syborg_timer.c +++ b/hw/syborg_timer.c @@ -83,7 +83,7 @@ static void syborg_timer_tick(void *opaque) syborg_timer_update(s); } -static uint32_t syborg_timer_read(void *opaque, target_phys_addr_t offset) +static uint32_t syborg_timer_read(void *opaque, a_target_phys_addr offset) { SyborgTimerState *s = (SyborgTimerState *)opaque; @@ -113,7 +113,7 @@ static uint32_t syborg_timer_read(void *opaque, target_phys_addr_t offset) } } -static void syborg_timer_write(void *opaque, target_phys_addr_t offset, +static void syborg_timer_write(void *opaque, a_target_phys_addr offset, uint32_t value) { SyborgTimerState *s = (SyborgTimerState *)opaque; diff --git a/hw/syborg_virtio.c b/hw/syborg_virtio.c index c1faf3d1a0..fbc50760cc 100644 --- a/hw/syborg_virtio.c +++ b/hw/syborg_virtio.c @@ -67,7 +67,7 @@ typedef struct { uint32_t id; } SyborgVirtIOProxy; -static uint32_t syborg_virtio_readl(void *opaque, target_phys_addr_t offset) +static uint32_t syborg_virtio_readl(void *opaque, a_target_phys_addr offset) { SyborgVirtIOProxy *s = opaque; VirtIODevice *vdev = s->vdev; @@ -116,7 +116,7 @@ static uint32_t syborg_virtio_readl(void *opaque, target_phys_addr_t offset) return ret; } -static void syborg_virtio_writel(void *opaque, target_phys_addr_t offset, +static void syborg_virtio_writel(void *opaque, a_target_phys_addr offset, uint32_t value) { SyborgVirtIOProxy *s = opaque; @@ -165,7 +165,7 @@ static void syborg_virtio_writel(void *opaque, target_phys_addr_t offset, } } -static uint32_t syborg_virtio_readw(void *opaque, target_phys_addr_t offset) +static uint32_t syborg_virtio_readw(void *opaque, a_target_phys_addr offset) { SyborgVirtIOProxy *s = opaque; VirtIODevice *vdev = s->vdev; @@ -178,7 +178,7 @@ static uint32_t syborg_virtio_readw(void *opaque, target_phys_addr_t offset) return -1; } -static void syborg_virtio_writew(void *opaque, target_phys_addr_t offset, +static void syborg_virtio_writew(void *opaque, a_target_phys_addr offset, uint32_t value) { SyborgVirtIOProxy *s = opaque; @@ -192,7 +192,7 @@ static void syborg_virtio_writew(void *opaque, target_phys_addr_t offset, BADF("Bad halfword write offset 0x%x\n", (int)offset); } -static uint32_t syborg_virtio_readb(void *opaque, target_phys_addr_t offset) +static uint32_t syborg_virtio_readb(void *opaque, a_target_phys_addr offset) { SyborgVirtIOProxy *s = opaque; VirtIODevice *vdev = s->vdev; @@ -205,7 +205,7 @@ static uint32_t syborg_virtio_readb(void *opaque, target_phys_addr_t offset) return -1; } -static void syborg_virtio_writeb(void *opaque, target_phys_addr_t offset, +static void syborg_virtio_writeb(void *opaque, a_target_phys_addr offset, uint32_t value) { SyborgVirtIOProxy *s = opaque; diff --git a/hw/sysbus.c b/hw/sysbus.c index f6516fd1d7..d43660e126 100644 --- a/hw/sysbus.c +++ b/hw/sysbus.c @@ -38,7 +38,7 @@ void sysbus_connect_irq(SysBusDevice *dev, int n, qemu_irq irq) } } -void sysbus_mmio_map(SysBusDevice *dev, int n, target_phys_addr_t addr) +void sysbus_mmio_map(SysBusDevice *dev, int n, a_target_phys_addr addr) { assert(n >= 0 && n < dev->num_mmio); @@ -46,7 +46,7 @@ void sysbus_mmio_map(SysBusDevice *dev, int n, target_phys_addr_t addr) /* ??? region already mapped here. */ return; } - if (dev->mmio[n].addr != (target_phys_addr_t)-1) { + if (dev->mmio[n].addr != (a_target_phys_addr)-1) { /* Unregister previous mapping. */ cpu_register_physical_memory(dev->mmio[n].addr, dev->mmio[n].size, IO_MEM_UNASSIGNED); @@ -82,7 +82,7 @@ void sysbus_pass_irq(SysBusDevice *dev, SysBusDevice *target) } } -void sysbus_init_mmio(SysBusDevice *dev, target_phys_addr_t size, int iofunc) +void sysbus_init_mmio(SysBusDevice *dev, a_target_phys_addr size, int iofunc) { int n; @@ -93,7 +93,7 @@ void sysbus_init_mmio(SysBusDevice *dev, target_phys_addr_t size, int iofunc) dev->mmio[n].iofunc = iofunc; } -void sysbus_init_mmio_cb(SysBusDevice *dev, target_phys_addr_t size, +void sysbus_init_mmio_cb(SysBusDevice *dev, a_target_phys_addr size, mmio_mapfunc cb) { int n; @@ -133,7 +133,7 @@ void sysbus_register_dev(const char *name, size_t size, sysbus_initfn init) } DeviceState *sysbus_create_varargs(const char *name, - target_phys_addr_t addr, ...) + a_target_phys_addr addr, ...) { DeviceState *dev; SysBusDevice *s; @@ -144,7 +144,7 @@ DeviceState *sysbus_create_varargs(const char *name, dev = qdev_create(NULL, name); s = sysbus_from_qdev(dev); qdev_init(dev); - if (addr != (target_phys_addr_t)-1) { + if (addr != (a_target_phys_addr)-1) { sysbus_mmio_map(s, 0, addr); } va_start(va, addr); diff --git a/hw/sysbus.h b/hw/sysbus.h index 1a8f289c75..106d7197fe 100644 --- a/hw/sysbus.h +++ b/hw/sysbus.h @@ -9,7 +9,7 @@ #define QDEV_MAX_IRQ 256 typedef struct SysBusDevice SysBusDevice; -typedef void (*mmio_mapfunc)(SysBusDevice *dev, target_phys_addr_t addr); +typedef void (*mmio_mapfunc)(SysBusDevice *dev, a_target_phys_addr addr); struct SysBusDevice { DeviceState qdev; @@ -18,8 +18,8 @@ struct SysBusDevice { qemu_irq *irqp[QDEV_MAX_IRQ]; int num_mmio; struct { - target_phys_addr_t addr; - target_phys_addr_t size; + a_target_phys_addr addr; + a_target_phys_addr size; mmio_mapfunc cb; int iofunc; } mmio[QDEV_MAX_MMIO]; @@ -39,21 +39,21 @@ typedef struct { void sysbus_register_dev(const char *name, size_t size, sysbus_initfn init); void sysbus_register_withprop(SysBusDeviceInfo *info); void *sysbus_new(void); -void sysbus_init_mmio(SysBusDevice *dev, target_phys_addr_t size, int iofunc); -void sysbus_init_mmio_cb(SysBusDevice *dev, target_phys_addr_t size, +void sysbus_init_mmio(SysBusDevice *dev, a_target_phys_addr size, int iofunc); +void sysbus_init_mmio_cb(SysBusDevice *dev, a_target_phys_addr size, mmio_mapfunc cb); void sysbus_init_irq(SysBusDevice *dev, qemu_irq *p); void sysbus_pass_irq(SysBusDevice *dev, SysBusDevice *target); void sysbus_connect_irq(SysBusDevice *dev, int n, qemu_irq irq); -void sysbus_mmio_map(SysBusDevice *dev, int n, target_phys_addr_t addr); +void sysbus_mmio_map(SysBusDevice *dev, int n, a_target_phys_addr addr); /* Legacy helper function for creating devices. */ DeviceState *sysbus_create_varargs(const char *name, - target_phys_addr_t addr, ...); + a_target_phys_addr addr, ...); static inline DeviceState *sysbus_create_simple(const char *name, - target_phys_addr_t addr, + a_target_phys_addr addr, qemu_irq irq) { return sysbus_create_varargs(name, addr, irq, NULL); diff --git a/hw/tc58128.c b/hw/tc58128.c index 264aa028da..92adca46b0 100644 --- a/hw/tc58128.c +++ b/hw/tc58128.c @@ -13,11 +13,11 @@ #define RDY2 0x8000 #define RDY(n) ((n) == 0 ? RDY1 : RDY2) -typedef enum { WAIT, READ1, READ2, READ3 } state_t; +typedef enum { WAIT, READ1, READ2, READ3 } e_state; typedef struct { uint8_t *flash_contents; - state_t state; + e_state state; uint32_t address; uint8_t address_cycle; } tc58128_dev; diff --git a/hw/tc6393xb.c b/hw/tc6393xb.c index e0c5e5f087..103f5bc50c 100644 --- a/hw/tc6393xb.c +++ b/hw/tc6393xb.c @@ -122,7 +122,7 @@ struct TC6393xbState { ECCState ecc; DisplayState *ds; - ram_addr_t vram_addr; + a_ram_addr vram_addr; uint16_t *vram_ptr; uint32_t scr_width, scr_height; /* in pixels */ qemu_irq l3v; @@ -211,7 +211,7 @@ static void tc6393xb_sub_irq(void *opaque, int line, int level) { case SCR_ ##N(1): return s->scr.N[1]; \ case SCR_ ##N(2): return s->scr.N[2] -static uint32_t tc6393xb_scr_readb(TC6393xbState *s, target_phys_addr_t addr) +static uint32_t tc6393xb_scr_readb(TC6393xbState *s, a_target_phys_addr addr) { switch (addr) { case SCR_REVID: @@ -272,7 +272,7 @@ static uint32_t tc6393xb_scr_readb(TC6393xbState *s, target_phys_addr_t addr) case SCR_ ##N(1): s->scr.N[1] = value; return; \ case SCR_ ##N(2): s->scr.N[2] = value; return -static void tc6393xb_scr_writeb(TC6393xbState *s, target_phys_addr_t addr, uint32_t value) +static void tc6393xb_scr_writeb(TC6393xbState *s, a_target_phys_addr addr, uint32_t value) { switch (addr) { SCR_REG_B(ISR); @@ -323,7 +323,7 @@ static void tc6393xb_nand_irq(TC6393xbState *s) { (s->nand.imr & 0x80) && (s->nand.imr & s->nand.isr)); } -static uint32_t tc6393xb_nand_cfg_readb(TC6393xbState *s, target_phys_addr_t addr) { +static uint32_t tc6393xb_nand_cfg_readb(TC6393xbState *s, a_target_phys_addr addr) { switch (addr) { case NAND_CFG_COMMAND: return s->nand_enable ? 2 : 0; @@ -336,7 +336,7 @@ static uint32_t tc6393xb_nand_cfg_readb(TC6393xbState *s, target_phys_addr_t add fprintf(stderr, "tc6393xb_nand_cfg: unhandled read at %08x\n", (uint32_t) addr); return 0; } -static void tc6393xb_nand_cfg_writeb(TC6393xbState *s, target_phys_addr_t addr, uint32_t value) { +static void tc6393xb_nand_cfg_writeb(TC6393xbState *s, a_target_phys_addr addr, uint32_t value) { switch (addr) { case NAND_CFG_COMMAND: s->nand_enable = (value & 0x2); @@ -353,7 +353,7 @@ static void tc6393xb_nand_cfg_writeb(TC6393xbState *s, target_phys_addr_t addr, (uint32_t) addr, value & 0xff); } -static uint32_t tc6393xb_nand_readb(TC6393xbState *s, target_phys_addr_t addr) { +static uint32_t tc6393xb_nand_readb(TC6393xbState *s, a_target_phys_addr addr) { switch (addr) { case NAND_DATA + 0: case NAND_DATA + 1: @@ -372,7 +372,7 @@ static uint32_t tc6393xb_nand_readb(TC6393xbState *s, target_phys_addr_t addr) { fprintf(stderr, "tc6393xb_nand: unhandled read at %08x\n", (uint32_t) addr); return 0; } -static void tc6393xb_nand_writeb(TC6393xbState *s, target_phys_addr_t addr, uint32_t value) { +static void tc6393xb_nand_writeb(TC6393xbState *s, a_target_phys_addr addr, uint32_t value) { // fprintf(stderr, "tc6393xb_nand: write at %08x: %02x\n", // (uint32_t) addr, value & 0xff); switch (addr) { @@ -495,7 +495,7 @@ static void tc6393xb_update_display(void *opaque) } -static uint32_t tc6393xb_readb(void *opaque, target_phys_addr_t addr) { +static uint32_t tc6393xb_readb(void *opaque, a_target_phys_addr addr) { TC6393xbState *s = opaque; switch (addr >> 8) { @@ -516,7 +516,7 @@ static uint32_t tc6393xb_readb(void *opaque, target_phys_addr_t addr) { return 0; } -static void tc6393xb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) { +static void tc6393xb_writeb(void *opaque, a_target_phys_addr addr, uint32_t value) { TC6393xbState *s = opaque; switch (addr >> 8) { @@ -535,13 +535,13 @@ static void tc6393xb_writeb(void *opaque, target_phys_addr_t addr, uint32_t valu (uint32_t) addr, value & 0xff); } -static uint32_t tc6393xb_readw(void *opaque, target_phys_addr_t addr) +static uint32_t tc6393xb_readw(void *opaque, a_target_phys_addr addr) { return (tc6393xb_readb(opaque, addr) & 0xff) | (tc6393xb_readb(opaque, addr + 1) << 8); } -static uint32_t tc6393xb_readl(void *opaque, target_phys_addr_t addr) +static uint32_t tc6393xb_readl(void *opaque, a_target_phys_addr addr) { return (tc6393xb_readb(opaque, addr) & 0xff) | ((tc6393xb_readb(opaque, addr + 1) & 0xff) << 8) | @@ -549,13 +549,13 @@ static uint32_t tc6393xb_readl(void *opaque, target_phys_addr_t addr) ((tc6393xb_readb(opaque, addr + 3) & 0xff) << 24); } -static void tc6393xb_writew(void *opaque, target_phys_addr_t addr, uint32_t value) +static void tc6393xb_writew(void *opaque, a_target_phys_addr addr, uint32_t value) { tc6393xb_writeb(opaque, addr, value); tc6393xb_writeb(opaque, addr + 1, value >> 8); } -static void tc6393xb_writel(void *opaque, target_phys_addr_t addr, uint32_t value) +static void tc6393xb_writel(void *opaque, a_target_phys_addr addr, uint32_t value) { tc6393xb_writeb(opaque, addr, value); tc6393xb_writeb(opaque, addr + 1, value >> 8); @@ -37,11 +37,11 @@ typedef struct TCXState { SysBusDevice busdev; - target_phys_addr_t addr; + a_target_phys_addr addr; DisplayState *ds; uint8_t *vram; uint32_t *vram24, *cplane; - ram_addr_t vram_offset, vram24_offset, cplane_offset; + a_ram_addr vram_offset, vram24_offset, cplane_offset; uint32_t vram_size; uint16_t width, height, depth; uint8_t r[256], g[256], b[256]; @@ -175,8 +175,8 @@ static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d, } } -static inline int check_dirty(ram_addr_t page, ram_addr_t page24, - ram_addr_t cpage) +static inline int check_dirty(a_ram_addr page, a_ram_addr page24, + a_ram_addr cpage) { int ret; unsigned int off; @@ -189,9 +189,9 @@ static inline int check_dirty(ram_addr_t page, ram_addr_t page24, return ret; } -static inline void reset_dirty(TCXState *ts, ram_addr_t page_min, - ram_addr_t page_max, ram_addr_t page24, - ram_addr_t cpage) +static inline void reset_dirty(TCXState *ts, a_ram_addr page_min, + a_ram_addr page_max, a_ram_addr page24, + a_ram_addr cpage) { cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE, VGA_DIRTY_FLAG); @@ -210,7 +210,7 @@ static inline void reset_dirty(TCXState *ts, ram_addr_t page_min, static void tcx_update_display(void *opaque) { TCXState *ts = opaque; - ram_addr_t page, page_min, page_max; + a_ram_addr page, page_min, page_max; int y, y_start, dd, ds; uint8_t *d, *s; void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width); @@ -288,7 +288,7 @@ static void tcx_update_display(void *opaque) static void tcx24_update_display(void *opaque) { TCXState *ts = opaque; - ram_addr_t page, page_min, page_max, cpage, page24; + a_ram_addr page, page_min, page_max, cpage, page24; int y, y_start, dd, ds; uint8_t *d, *s; uint32_t *cptr, *s24; @@ -428,12 +428,12 @@ static void tcx_reset(void *opaque) s->dac_state = 0; } -static uint32_t tcx_dac_readl(void *opaque, target_phys_addr_t addr) +static uint32_t tcx_dac_readl(void *opaque, a_target_phys_addr addr) { return 0; } -static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val) +static void tcx_dac_writel(void *opaque, a_target_phys_addr addr, uint32_t val) { TCXState *s = opaque; @@ -481,12 +481,12 @@ static CPUWriteMemoryFunc * const tcx_dac_write[3] = { tcx_dac_writel, }; -static uint32_t tcx_dummy_readl(void *opaque, target_phys_addr_t addr) +static uint32_t tcx_dummy_readl(void *opaque, a_target_phys_addr addr) { return 0; } -static void tcx_dummy_writel(void *opaque, target_phys_addr_t addr, +static void tcx_dummy_writel(void *opaque, a_target_phys_addr addr, uint32_t val) { } @@ -507,7 +507,7 @@ static int tcx_init1(SysBusDevice *dev) { TCXState *s = FROM_SYSBUS(TCXState, dev); int io_memory, dummy_memory; - ram_addr_t vram_offset; + a_ram_addr vram_offset; int size; uint8_t *vram_base; @@ -200,7 +200,7 @@ static struct arm_boot_info tosa_binfo = { .ram_size = 0x04000000, }; -static void tosa_init(ram_addr_t ram_size, +static void tosa_init(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) diff --git a/hw/tusb6010.c b/hw/tusb6010.c index 3887233339..e47085d946 100644 --- a/hw/tusb6010.c +++ b/hw/tusb6010.c @@ -289,7 +289,7 @@ static void tusb_gpio_intr_update(TUSBState *s) extern CPUReadMemoryFunc * const musb_read[]; extern CPUWriteMemoryFunc * const musb_write[]; -static uint32_t tusb_async_readb(void *opaque, target_phys_addr_t addr) +static uint32_t tusb_async_readb(void *opaque, a_target_phys_addr addr) { TUSBState *s = (TUSBState *) opaque; @@ -306,7 +306,7 @@ static uint32_t tusb_async_readb(void *opaque, target_phys_addr_t addr) return 0; } -static uint32_t tusb_async_readh(void *opaque, target_phys_addr_t addr) +static uint32_t tusb_async_readh(void *opaque, a_target_phys_addr addr) { TUSBState *s = (TUSBState *) opaque; @@ -323,7 +323,7 @@ static uint32_t tusb_async_readh(void *opaque, target_phys_addr_t addr) return 0; } -static uint32_t tusb_async_readw(void *opaque, target_phys_addr_t addr) +static uint32_t tusb_async_readw(void *opaque, a_target_phys_addr addr) { TUSBState *s = (TUSBState *) opaque; int offset = addr & 0xfff; @@ -447,7 +447,7 @@ static uint32_t tusb_async_readw(void *opaque, target_phys_addr_t addr) return 0; } -static void tusb_async_writeb(void *opaque, target_phys_addr_t addr, +static void tusb_async_writeb(void *opaque, a_target_phys_addr addr, uint32_t value) { TUSBState *s = (TUSBState *) opaque; @@ -468,7 +468,7 @@ static void tusb_async_writeb(void *opaque, target_phys_addr_t addr, } } -static void tusb_async_writeh(void *opaque, target_phys_addr_t addr, +static void tusb_async_writeh(void *opaque, a_target_phys_addr addr, uint32_t value) { TUSBState *s = (TUSBState *) opaque; @@ -489,7 +489,7 @@ static void tusb_async_writeh(void *opaque, target_phys_addr_t addr, } } -static void tusb_async_writew(void *opaque, target_phys_addr_t addr, +static void tusb_async_writew(void *opaque, a_target_phys_addr addr, uint32_t value) { TUSBState *s = (TUSBState *) opaque; diff --git a/hw/unin_pci.c b/hw/unin_pci.c index a202153922..76a5f2e61e 100644 --- a/hw/unin_pci.c +++ b/hw/unin_pci.c @@ -35,7 +35,7 @@ #define UNIN_DPRINTF(fmt, ...) #endif -typedef target_phys_addr_t pci_addr_t; +typedef a_target_phys_addr a_pci_addr; #include "pci_host.h" typedef struct UNINState { @@ -43,7 +43,7 @@ typedef struct UNINState { PCIHostState host_state; } UNINState; -static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr, +static void pci_unin_main_config_writel (void *opaque, a_target_phys_addr addr, uint32_t val) { UNINState *s = opaque; @@ -57,7 +57,7 @@ static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr, } static uint32_t pci_unin_main_config_readl (void *opaque, - target_phys_addr_t addr) + a_target_phys_addr addr) { UNINState *s = opaque; uint32_t val; @@ -95,7 +95,7 @@ static CPUReadMemoryFunc * const pci_unin_main_read[] = { &pci_host_data_readl, }; -static void pci_unin_config_writel (void *opaque, target_phys_addr_t addr, +static void pci_unin_config_writel (void *opaque, a_target_phys_addr addr, uint32_t val) { UNINState *s = opaque; @@ -104,7 +104,7 @@ static void pci_unin_config_writel (void *opaque, target_phys_addr_t addr, } static uint32_t pci_unin_config_readl (void *opaque, - target_phys_addr_t addr) + a_target_phys_addr addr) { UNINState *s = opaque; diff --git a/hw/usb-musb.c b/hw/usb-musb.c index 9eb0d6361f..12544764e8 100644 --- a/hw/usb-musb.c +++ b/hw/usb-musb.c @@ -1142,7 +1142,7 @@ static void musb_ep_writeh(void *opaque, int ep, int addr, uint16_t value) } /* Generic control */ -static uint32_t musb_readb(void *opaque, target_phys_addr_t addr) +static uint32_t musb_readb(void *opaque, a_target_phys_addr addr) { MUSBState *s = (MUSBState *) opaque; int ep, i; @@ -1200,7 +1200,7 @@ static uint32_t musb_readb(void *opaque, target_phys_addr_t addr) }; } -static void musb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) +static void musb_writeb(void *opaque, a_target_phys_addr addr, uint32_t value) { MUSBState *s = (MUSBState *) opaque; int ep; @@ -1281,7 +1281,7 @@ static void musb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) }; } -static uint32_t musb_readh(void *opaque, target_phys_addr_t addr) +static uint32_t musb_readh(void *opaque, a_target_phys_addr addr) { MUSBState *s = (MUSBState *) opaque; int ep, i; @@ -1331,7 +1331,7 @@ static uint32_t musb_readh(void *opaque, target_phys_addr_t addr) }; } -static void musb_writeh(void *opaque, target_phys_addr_t addr, uint32_t value) +static void musb_writeh(void *opaque, a_target_phys_addr addr, uint32_t value) { MUSBState *s = (MUSBState *) opaque; int ep; @@ -1381,7 +1381,7 @@ static void musb_writeh(void *opaque, target_phys_addr_t addr, uint32_t value) }; } -static uint32_t musb_readw(void *opaque, target_phys_addr_t addr) +static uint32_t musb_readw(void *opaque, a_target_phys_addr addr) { MUSBState *s = (MUSBState *) opaque; MUSBEndPoint *ep; @@ -1410,7 +1410,7 @@ static uint32_t musb_readw(void *opaque, target_phys_addr_t addr) }; } -static void musb_writew(void *opaque, target_phys_addr_t addr, uint32_t value) +static void musb_writew(void *opaque, a_target_phys_addr addr, uint32_t value) { MUSBState *s = (MUSBState *) opaque; MUSBEndPoint *ep; diff --git a/hw/usb-ohci.c b/hw/usb-ohci.c index 6e428c4fda..3062e5b41e 100644 --- a/hw/usb-ohci.c +++ b/hw/usb-ohci.c @@ -111,7 +111,7 @@ typedef struct { uint32_t htest; /* SM501 local memory offset */ - target_phys_addr_t localmem_base; + a_target_phys_addr localmem_base; /* Active packets. */ uint32_t old_ctl; @@ -1398,7 +1398,7 @@ static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val) return; } -static uint32_t ohci_mem_read(void *ptr, target_phys_addr_t addr) +static uint32_t ohci_mem_read(void *ptr, a_target_phys_addr addr) { OHCIState *ohci = ptr; uint32_t retval; @@ -1522,7 +1522,7 @@ static uint32_t ohci_mem_read(void *ptr, target_phys_addr_t addr) return retval; } -static void ohci_mem_write(void *ptr, target_phys_addr_t addr, uint32_t val) +static void ohci_mem_write(void *ptr, a_target_phys_addr addr, uint32_t val) { OHCIState *ohci = ptr; @@ -1739,7 +1739,7 @@ void usb_ohci_init_pci(struct PCIBus *bus, int devfn) pci_create_simple(bus, devfn, "OHCI USB PCI"); } -void usb_ohci_init_pxa(target_phys_addr_t base, int num_ports, int devfn, +void usb_ohci_init_pxa(a_target_phys_addr base, int num_ports, int devfn, qemu_irq irq) { OHCIState *ohci = (OHCIState *)qemu_mallocz(sizeof(OHCIState)); diff --git a/hw/versatile_pci.c b/hw/versatile_pci.c index a0d7d07ad2..c16061b2b1 100644 --- a/hw/versatile_pci.c +++ b/hw/versatile_pci.c @@ -17,18 +17,18 @@ typedef struct { int mem_config; } PCIVPBState; -static inline uint32_t vpb_pci_config_addr(target_phys_addr_t addr) +static inline uint32_t vpb_pci_config_addr(a_target_phys_addr addr) { return addr & 0xffffff; } -static void pci_vpb_config_writeb (void *opaque, target_phys_addr_t addr, +static void pci_vpb_config_writeb (void *opaque, a_target_phys_addr addr, uint32_t val) { pci_data_write(opaque, vpb_pci_config_addr (addr), val, 1); } -static void pci_vpb_config_writew (void *opaque, target_phys_addr_t addr, +static void pci_vpb_config_writew (void *opaque, a_target_phys_addr addr, uint32_t val) { #ifdef TARGET_WORDS_BIGENDIAN @@ -37,7 +37,7 @@ static void pci_vpb_config_writew (void *opaque, target_phys_addr_t addr, pci_data_write(opaque, vpb_pci_config_addr (addr), val, 2); } -static void pci_vpb_config_writel (void *opaque, target_phys_addr_t addr, +static void pci_vpb_config_writel (void *opaque, a_target_phys_addr addr, uint32_t val) { #ifdef TARGET_WORDS_BIGENDIAN @@ -46,14 +46,14 @@ static void pci_vpb_config_writel (void *opaque, target_phys_addr_t addr, pci_data_write(opaque, vpb_pci_config_addr (addr), val, 4); } -static uint32_t pci_vpb_config_readb (void *opaque, target_phys_addr_t addr) +static uint32_t pci_vpb_config_readb (void *opaque, a_target_phys_addr addr) { uint32_t val; val = pci_data_read(opaque, vpb_pci_config_addr (addr), 1); return val; } -static uint32_t pci_vpb_config_readw (void *opaque, target_phys_addr_t addr) +static uint32_t pci_vpb_config_readw (void *opaque, a_target_phys_addr addr) { uint32_t val; val = pci_data_read(opaque, vpb_pci_config_addr (addr), 2); @@ -63,7 +63,7 @@ static uint32_t pci_vpb_config_readw (void *opaque, target_phys_addr_t addr) return val; } -static uint32_t pci_vpb_config_readl (void *opaque, target_phys_addr_t addr) +static uint32_t pci_vpb_config_readl (void *opaque, a_target_phys_addr addr) { uint32_t val; val = pci_data_read(opaque, vpb_pci_config_addr (addr), 4); @@ -97,7 +97,7 @@ static void pci_vpb_set_irq(void *opaque, int irq_num, int level) qemu_set_irq(pic[irq_num], level); } -static void pci_vpb_map(SysBusDevice *dev, target_phys_addr_t base) +static void pci_vpb_map(SysBusDevice *dev, a_target_phys_addr base) { PCIVPBState *s = (PCIVPBState *)dev; /* Selfconfig area. */ diff --git a/hw/versatilepb.c b/hw/versatilepb.c index 29b85ae7b8..8450a3393b 100644 --- a/hw/versatilepb.c +++ b/hw/versatilepb.c @@ -61,7 +61,7 @@ static void vpb_sic_set_irq(void *opaque, int irq, int level) vpb_sic_update(s); } -static uint32_t vpb_sic_read(void *opaque, target_phys_addr_t offset) +static uint32_t vpb_sic_read(void *opaque, a_target_phys_addr offset) { vpb_sic_state *s = (vpb_sic_state *)opaque; @@ -82,7 +82,7 @@ static uint32_t vpb_sic_read(void *opaque, target_phys_addr_t offset) } } -static void vpb_sic_write(void *opaque, target_phys_addr_t offset, +static void vpb_sic_write(void *opaque, a_target_phys_addr offset, uint32_t value) { vpb_sic_state *s = (vpb_sic_state *)opaque; @@ -155,14 +155,14 @@ static int vpb_sic_init(SysBusDevice *dev) static struct arm_boot_info versatile_binfo; -static void versatile_init(ram_addr_t ram_size, +static void versatile_init(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model, int board_id) { CPUState *env; - ram_addr_t ram_offset; + a_ram_addr ram_offset; qemu_irq *cpu_pic; qemu_irq pic[32]; qemu_irq sic[32]; @@ -288,7 +288,7 @@ static void versatile_init(ram_addr_t ram_size, arm_load_kernel(env, &versatile_binfo); } -static void vpb_init(ram_addr_t ram_size, +static void vpb_init(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -299,7 +299,7 @@ static void vpb_init(ram_addr_t ram_size, initrd_filename, cpu_model, 0x183); } -static void vab_init(ram_addr_t ram_size, +static void vab_init(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) diff --git a/hw/vga-isa-mm.c b/hw/vga-isa-mm.c index f8fc940ed4..5b03a74cc3 100644 --- a/hw/vga-isa-mm.c +++ b/hw/vga-isa-mm.c @@ -34,7 +34,7 @@ typedef struct ISAVGAMMState { } ISAVGAMMState; /* Memory mapped interface */ -static uint32_t vga_mm_readb (void *opaque, target_phys_addr_t addr) +static uint32_t vga_mm_readb (void *opaque, a_target_phys_addr addr) { ISAVGAMMState *s = opaque; @@ -42,14 +42,14 @@ static uint32_t vga_mm_readb (void *opaque, target_phys_addr_t addr) } static void vga_mm_writeb (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { ISAVGAMMState *s = opaque; vga_ioport_write(&s->vga, addr >> s->it_shift, value & 0xff); } -static uint32_t vga_mm_readw (void *opaque, target_phys_addr_t addr) +static uint32_t vga_mm_readw (void *opaque, a_target_phys_addr addr) { ISAVGAMMState *s = opaque; @@ -57,14 +57,14 @@ static uint32_t vga_mm_readw (void *opaque, target_phys_addr_t addr) } static void vga_mm_writew (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { ISAVGAMMState *s = opaque; vga_ioport_write(&s->vga, addr >> s->it_shift, value & 0xffff); } -static uint32_t vga_mm_readl (void *opaque, target_phys_addr_t addr) +static uint32_t vga_mm_readl (void *opaque, a_target_phys_addr addr) { ISAVGAMMState *s = opaque; @@ -72,7 +72,7 @@ static uint32_t vga_mm_readl (void *opaque, target_phys_addr_t addr) } static void vga_mm_writel (void *opaque, - target_phys_addr_t addr, uint32_t value) + a_target_phys_addr addr, uint32_t value) { ISAVGAMMState *s = opaque; @@ -91,8 +91,8 @@ static CPUWriteMemoryFunc * const vga_mm_write_ctrl[] = { &vga_mm_writel, }; -static void vga_mm_init(ISAVGAMMState *s, target_phys_addr_t vram_base, - target_phys_addr_t ctrl_base, int it_shift) +static void vga_mm_init(ISAVGAMMState *s, a_target_phys_addr vram_base, + a_target_phys_addr ctrl_base, int it_shift) { int s_ioport_ctrl, vga_io_memory; @@ -108,8 +108,8 @@ static void vga_mm_init(ISAVGAMMState *s, target_phys_addr_t vram_base, qemu_register_coalesced_mmio(vram_base + 0x000a0000, 0x20000); } -int isa_vga_mm_init(target_phys_addr_t vram_base, - target_phys_addr_t ctrl_base, int it_shift) +int isa_vga_mm_init(a_target_phys_addr vram_base, + a_target_phys_addr ctrl_base, int it_shift) { ISAVGAMMState *s; @@ -702,7 +702,7 @@ static void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val) #endif /* called for accesses between 0xa0000 and 0xc0000 */ -uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr) +uint32_t vga_mem_readb(void *opaque, a_target_phys_addr addr) { VGACommonState *s = opaque; int memory_map_mode, plane; @@ -758,7 +758,7 @@ uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr) return ret; } -static uint32_t vga_mem_readw(void *opaque, target_phys_addr_t addr) +static uint32_t vga_mem_readw(void *opaque, a_target_phys_addr addr) { uint32_t v; #ifdef TARGET_WORDS_BIGENDIAN @@ -771,7 +771,7 @@ static uint32_t vga_mem_readw(void *opaque, target_phys_addr_t addr) return v; } -static uint32_t vga_mem_readl(void *opaque, target_phys_addr_t addr) +static uint32_t vga_mem_readl(void *opaque, a_target_phys_addr addr) { uint32_t v; #ifdef TARGET_WORDS_BIGENDIAN @@ -789,7 +789,7 @@ static uint32_t vga_mem_readl(void *opaque, target_phys_addr_t addr) } /* called for accesses between 0xa0000 and 0xc0000 */ -void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) +void vga_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val) { VGACommonState *s = opaque; int memory_map_mode, plane, write_mode, b, func_select, mask; @@ -923,7 +923,7 @@ void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) } } -static void vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) +static void vga_mem_writew(void *opaque, a_target_phys_addr addr, uint32_t val) { #ifdef TARGET_WORDS_BIGENDIAN vga_mem_writeb(opaque, addr, (val >> 8) & 0xff); @@ -934,7 +934,7 @@ static void vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) #endif } -static void vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) +static void vga_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val) { #ifdef TARGET_WORDS_BIGENDIAN vga_mem_writeb(opaque, addr, (val >> 24) & 0xff); @@ -1583,7 +1583,7 @@ static void vga_draw_graphic(VGACommonState *s, int full_update) { int y1, y, update, linesize, y_start, double_scan, mask, depth; int width, height, shift_control, line_offset, bwidth, bits; - ram_addr_t page0, page1, page_min, page_max; + a_ram_addr page0, page1, page_min, page_max; int disp_width, multi_scan, multi_run; uint8_t *d; uint32_t v, addr1, addr; @@ -1947,13 +1947,13 @@ static void vga_reset(void *opaque) ((v & 0x00000800) << 10) | ((v & 0x00007000) >> 1)) /* relay text rendering to the display driver * instead of doing a full vga_update_display() */ -static void vga_update_text(void *opaque, console_ch_t *chardata) +static void vga_update_text(void *opaque, a_console_ch *chardata) { VGACommonState *s = opaque; int graphic_mode, i, cursor_offset, cursor_visible; int cw, cheight, width, height, size, c_min, c_max; uint32_t *src; - console_ch_t *dst, val; + a_console_ch *dst, val; char msg_buffer[80]; int full_update = 0; diff --git a/hw/vga_int.h b/hw/vga_int.h index c162c07103..8740f2a2fb 100644 --- a/hw/vga_int.h +++ b/hw/vga_int.h @@ -100,7 +100,7 @@ typedef void (* vga_update_retrace_info_fn)(struct VGACommonState *s); typedef struct VGACommonState { uint8_t *vram_ptr; - ram_addr_t vram_offset; + a_ram_addr vram_offset; unsigned int vram_size; uint32_t lfb_addr; uint32_t lfb_end; @@ -196,8 +196,8 @@ void vga_common_save(QEMUFile *f, void *opaque); int vga_common_load(QEMUFile *f, void *opaque, int version_id); uint32_t vga_ioport_read(void *opaque, uint32_t addr); void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val); -uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr); -void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val); +uint32_t vga_mem_readb(void *opaque, a_target_phys_addr addr); +void vga_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val); void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2); int ppm_save(const char *filename, struct DisplaySurface *ds); diff --git a/hw/virtio-balloon.c b/hw/virtio-balloon.c index cfd3b413ff..d535ef54fa 100644 --- a/hw/virtio-balloon.c +++ b/hw/virtio-balloon.c @@ -84,10 +84,10 @@ static void virtio_balloon_handle_output(VirtIODevice *vdev, VirtQueue *vq) while (memcpy_from_iovector(&pfn, offset, 4, elem.out_sg, elem.out_num) == 4) { - ram_addr_t pa; - ram_addr_t addr; + a_ram_addr pa; + a_ram_addr addr; - pa = (ram_addr_t)ldl_p(&pfn) << VIRTIO_BALLOON_PFN_SHIFT; + pa = (a_ram_addr)ldl_p(&pfn) << VIRTIO_BALLOON_PFN_SHIFT; offset += 4; addr = cpu_get_physical_page_desc(pa); @@ -129,7 +129,7 @@ static uint32_t virtio_balloon_get_features(VirtIODevice *vdev) return 0; } -static ram_addr_t virtio_balloon_to_target(void *opaque, ram_addr_t target) +static a_ram_addr virtio_balloon_to_target(void *opaque, a_ram_addr target) { VirtIOBalloon *dev = opaque; diff --git a/hw/virtio-pci.c b/hw/virtio-pci.c index bd5a7c4d3a..7e0c750826 100644 --- a/hw/virtio-pci.c +++ b/hw/virtio-pci.c @@ -166,7 +166,7 @@ static void virtio_ioport_write(void *opaque, uint32_t addr, uint32_t val) { VirtIOPCIProxy *proxy = opaque; VirtIODevice *vdev = proxy->vdev; - target_phys_addr_t pa; + a_target_phys_addr pa; switch (addr) { case VIRTIO_PCI_GUEST_FEATURES: @@ -182,7 +182,7 @@ static void virtio_ioport_write(void *opaque, uint32_t addr, uint32_t val) vdev->features = val; break; case VIRTIO_PCI_QUEUE_PFN: - pa = (target_phys_addr_t)val << VIRTIO_PCI_QUEUE_ADDR_SHIFT; + pa = (a_target_phys_addr)val << VIRTIO_PCI_QUEUE_ADDR_SHIFT; if (pa == 0) virtio_pci_reset(proxy); else diff --git a/hw/virtio.c b/hw/virtio.c index 337ff27ba9..99ee021a55 100644 --- a/hw/virtio.c +++ b/hw/virtio.c @@ -57,15 +57,15 @@ typedef struct VRingUsed typedef struct VRing { unsigned int num; - target_phys_addr_t desc; - target_phys_addr_t avail; - target_phys_addr_t used; + a_target_phys_addr desc; + a_target_phys_addr avail; + a_target_phys_addr used; } VRing; struct VirtQueue { VRing vring; - target_phys_addr_t pa; + a_target_phys_addr pa; uint16_t last_avail_idx; int inuse; uint16_t vector; @@ -77,7 +77,7 @@ struct VirtQueue /* virt queue functions */ static void virtqueue_init(VirtQueue *vq) { - target_phys_addr_t pa = vq->pa; + a_target_phys_addr pa = vq->pa; vq->vring.desc = pa; vq->vring.avail = pa + vq->vring.num * sizeof(VRingDesc); @@ -86,93 +86,93 @@ static void virtqueue_init(VirtQueue *vq) VIRTIO_PCI_VRING_ALIGN); } -static inline uint64_t vring_desc_addr(target_phys_addr_t desc_pa, int i) +static inline uint64_t vring_desc_addr(a_target_phys_addr desc_pa, int i) { - target_phys_addr_t pa; + a_target_phys_addr pa; pa = desc_pa + sizeof(VRingDesc) * i + offsetof(VRingDesc, addr); return ldq_phys(pa); } -static inline uint32_t vring_desc_len(target_phys_addr_t desc_pa, int i) +static inline uint32_t vring_desc_len(a_target_phys_addr desc_pa, int i) { - target_phys_addr_t pa; + a_target_phys_addr pa; pa = desc_pa + sizeof(VRingDesc) * i + offsetof(VRingDesc, len); return ldl_phys(pa); } -static inline uint16_t vring_desc_flags(target_phys_addr_t desc_pa, int i) +static inline uint16_t vring_desc_flags(a_target_phys_addr desc_pa, int i) { - target_phys_addr_t pa; + a_target_phys_addr pa; pa = desc_pa + sizeof(VRingDesc) * i + offsetof(VRingDesc, flags); return lduw_phys(pa); } -static inline uint16_t vring_desc_next(target_phys_addr_t desc_pa, int i) +static inline uint16_t vring_desc_next(a_target_phys_addr desc_pa, int i) { - target_phys_addr_t pa; + a_target_phys_addr pa; pa = desc_pa + sizeof(VRingDesc) * i + offsetof(VRingDesc, next); return lduw_phys(pa); } static inline uint16_t vring_avail_flags(VirtQueue *vq) { - target_phys_addr_t pa; + a_target_phys_addr pa; pa = vq->vring.avail + offsetof(VRingAvail, flags); return lduw_phys(pa); } static inline uint16_t vring_avail_idx(VirtQueue *vq) { - target_phys_addr_t pa; + a_target_phys_addr pa; pa = vq->vring.avail + offsetof(VRingAvail, idx); return lduw_phys(pa); } static inline uint16_t vring_avail_ring(VirtQueue *vq, int i) { - target_phys_addr_t pa; + a_target_phys_addr pa; pa = vq->vring.avail + offsetof(VRingAvail, ring[i]); return lduw_phys(pa); } static inline void vring_used_ring_id(VirtQueue *vq, int i, uint32_t val) { - target_phys_addr_t pa; + a_target_phys_addr pa; pa = vq->vring.used + offsetof(VRingUsed, ring[i].id); stl_phys(pa, val); } static inline void vring_used_ring_len(VirtQueue *vq, int i, uint32_t val) { - target_phys_addr_t pa; + a_target_phys_addr pa; pa = vq->vring.used + offsetof(VRingUsed, ring[i].len); stl_phys(pa, val); } static uint16_t vring_used_idx(VirtQueue *vq) { - target_phys_addr_t pa; + a_target_phys_addr pa; pa = vq->vring.used + offsetof(VRingUsed, idx); return lduw_phys(pa); } static inline void vring_used_idx_increment(VirtQueue *vq, uint16_t val) { - target_phys_addr_t pa; + a_target_phys_addr pa; pa = vq->vring.used + offsetof(VRingUsed, idx); stw_phys(pa, vring_used_idx(vq) + val); } static inline void vring_used_flags_set_bit(VirtQueue *vq, int mask) { - target_phys_addr_t pa; + a_target_phys_addr pa; pa = vq->vring.used + offsetof(VRingUsed, flags); stw_phys(pa, lduw_phys(pa) | mask); } static inline void vring_used_flags_unset_bit(VirtQueue *vq, int mask) { - target_phys_addr_t pa; + a_target_phys_addr pa; pa = vq->vring.used + offsetof(VRingUsed, flags); stw_phys(pa, lduw_phys(pa) & ~mask); } @@ -270,7 +270,7 @@ static unsigned int virtqueue_get_head(VirtQueue *vq, unsigned int idx) return head; } -static unsigned virtqueue_next_desc(target_phys_addr_t desc_pa, +static unsigned virtqueue_next_desc(a_target_phys_addr desc_pa, unsigned int i, unsigned int max) { unsigned int next; @@ -302,7 +302,7 @@ int virtqueue_avail_bytes(VirtQueue *vq, int in_bytes, int out_bytes) total_bufs = in_total = out_total = 0; while (virtqueue_num_heads(vq, idx)) { unsigned int max, num_bufs, indirect = 0; - target_phys_addr_t desc_pa; + a_target_phys_addr desc_pa; int i; max = vq->vring.num; @@ -359,8 +359,8 @@ int virtqueue_avail_bytes(VirtQueue *vq, int in_bytes, int out_bytes) int virtqueue_pop(VirtQueue *vq, VirtQueueElement *elem) { unsigned int i, head, max; - target_phys_addr_t desc_pa = vq->vring.desc; - target_phys_addr_t len; + a_target_phys_addr desc_pa = vq->vring.desc; + a_target_phys_addr len; if (!virtqueue_num_heads(vq, vq->last_avail_idx)) return 0; @@ -537,13 +537,13 @@ void virtio_config_writel(VirtIODevice *vdev, uint32_t addr, uint32_t data) vdev->set_config(vdev, vdev->config); } -void virtio_queue_set_addr(VirtIODevice *vdev, int n, target_phys_addr_t addr) +void virtio_queue_set_addr(VirtIODevice *vdev, int n, a_target_phys_addr addr) { vdev->vq[n].pa = addr; virtqueue_init(&vdev->vq[n]); } -target_phys_addr_t virtio_queue_get_addr(VirtIODevice *vdev, int n) +a_target_phys_addr virtio_queue_get_addr(VirtIODevice *vdev, int n) { return vdev->vq[n].pa; } diff --git a/hw/virtio.h b/hw/virtio.h index 0f9be7d106..920ccddd57 100644 --- a/hw/virtio.h +++ b/hw/virtio.h @@ -54,7 +54,7 @@ struct VirtQueue; -static inline target_phys_addr_t vring_align(target_phys_addr_t addr, +static inline a_target_phys_addr vring_align(a_target_phys_addr addr, unsigned long align) { return (addr + align - 1) & ~(align - 1); @@ -70,7 +70,7 @@ typedef struct VirtQueueElement unsigned int index; unsigned int out_num; unsigned int in_num; - target_phys_addr_t in_addr[VIRTQUEUE_MAX_SIZE]; + a_target_phys_addr in_addr[VIRTQUEUE_MAX_SIZE]; struct iovec in_sg[VIRTQUEUE_MAX_SIZE]; struct iovec out_sg[VIRTQUEUE_MAX_SIZE]; } VirtQueueElement; @@ -149,8 +149,8 @@ uint32_t virtio_config_readl(VirtIODevice *vdev, uint32_t addr); void virtio_config_writeb(VirtIODevice *vdev, uint32_t addr, uint32_t data); void virtio_config_writew(VirtIODevice *vdev, uint32_t addr, uint32_t data); void virtio_config_writel(VirtIODevice *vdev, uint32_t addr, uint32_t data); -void virtio_queue_set_addr(VirtIODevice *vdev, int n, target_phys_addr_t addr); -target_phys_addr_t virtio_queue_get_addr(VirtIODevice *vdev, int n); +void virtio_queue_set_addr(VirtIODevice *vdev, int n, a_target_phys_addr addr); +a_target_phys_addr virtio_queue_get_addr(VirtIODevice *vdev, int n); int virtio_queue_get_num(VirtIODevice *vdev, int n); void virtio_queue_notify(VirtIODevice *vdev, int n); uint16_t virtio_queue_vector(VirtIODevice *vdev, int n); diff --git a/hw/vmware_vga.c b/hw/vmware_vga.c index a273f35930..6489e9a8d1 100644 --- a/hw/vmware_vga.c +++ b/hw/vmware_vga.c @@ -58,10 +58,10 @@ struct vmsvga_state_s { #ifndef EMBED_STDVGA DisplayState *ds; int vram_size; - ram_addr_t vram_offset; + a_ram_addr vram_offset; uint8_t *vram_ptr; #endif - target_phys_addr_t vram_base; + a_target_phys_addr vram_base; int index; int scratch_size; @@ -991,7 +991,7 @@ static void vmsvga_screen_dump(void *opaque, const char *filename) } } -static void vmsvga_text_update(void *opaque, console_ch_t *chardata) +static void vmsvga_text_update(void *opaque, a_console_ch *chardata) { struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; @@ -1000,7 +1000,7 @@ static void vmsvga_text_update(void *opaque, console_ch_t *chardata) } #ifdef DIRECT_VRAM -static uint32_t vmsvga_vram_readb(void *opaque, target_phys_addr_t addr) +static uint32_t vmsvga_vram_readb(void *opaque, a_target_phys_addr addr) { struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; if (addr < s->fb_size) @@ -1009,7 +1009,7 @@ static uint32_t vmsvga_vram_readb(void *opaque, target_phys_addr_t addr) return *(uint8_t *) (s->vram_ptr + addr); } -static uint32_t vmsvga_vram_readw(void *opaque, target_phys_addr_t addr) +static uint32_t vmsvga_vram_readw(void *opaque, a_target_phys_addr addr) { struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; if (addr < s->fb_size) @@ -1018,7 +1018,7 @@ static uint32_t vmsvga_vram_readw(void *opaque, target_phys_addr_t addr) return *(uint16_t *) (s->vram_ptr + addr); } -static uint32_t vmsvga_vram_readl(void *opaque, target_phys_addr_t addr) +static uint32_t vmsvga_vram_readl(void *opaque, a_target_phys_addr addr) { struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; if (addr < s->fb_size) @@ -1027,7 +1027,7 @@ static uint32_t vmsvga_vram_readl(void *opaque, target_phys_addr_t addr) return *(uint32_t *) (s->vram_ptr + addr); } -static void vmsvga_vram_writeb(void *opaque, target_phys_addr_t addr, +static void vmsvga_vram_writeb(void *opaque, a_target_phys_addr addr, uint32_t value) { struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; @@ -1037,7 +1037,7 @@ static void vmsvga_vram_writeb(void *opaque, target_phys_addr_t addr, *(uint8_t *) (s->vram_ptr + addr) = value; } -static void vmsvga_vram_writew(void *opaque, target_phys_addr_t addr, +static void vmsvga_vram_writew(void *opaque, a_target_phys_addr addr, uint32_t value) { struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; @@ -1047,7 +1047,7 @@ static void vmsvga_vram_writew(void *opaque, target_phys_addr_t addr, *(uint16_t *) (s->vram_ptr + addr) = value; } -static void vmsvga_vram_writel(void *opaque, target_phys_addr_t addr, +static void vmsvga_vram_writel(void *opaque, a_target_phys_addr addr, uint32_t value) { struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque; @@ -1198,7 +1198,7 @@ static void pci_vmsvga_map_mem(PCIDevice *pci_dev, int region_num, { struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev; struct vmsvga_state_s *s = &d->chip; - ram_addr_t iomemtype; + a_ram_addr iomemtype; s->vram_base = addr; #ifdef DIRECT_VRAM diff --git a/hw/wdt_i6300esb.c b/hw/wdt_i6300esb.c index 3abaa87cf0..2d23404f38 100644 --- a/hw/wdt_i6300esb.c +++ b/hw/wdt_i6300esb.c @@ -247,14 +247,14 @@ static uint32_t i6300esb_config_read(PCIDevice *dev, uint32_t addr, int len) } } -static uint32_t i6300esb_mem_readb(void *vp, target_phys_addr_t addr) +static uint32_t i6300esb_mem_readb(void *vp, a_target_phys_addr addr) { i6300esb_debug ("addr = %x\n", (int) addr); return 0; } -static uint32_t i6300esb_mem_readw(void *vp, target_phys_addr_t addr) +static uint32_t i6300esb_mem_readw(void *vp, a_target_phys_addr addr) { uint32_t data = 0; I6300State *d = (I6300State *) vp; @@ -272,14 +272,14 @@ static uint32_t i6300esb_mem_readw(void *vp, target_phys_addr_t addr) return data; } -static uint32_t i6300esb_mem_readl(void *vp, target_phys_addr_t addr) +static uint32_t i6300esb_mem_readl(void *vp, a_target_phys_addr addr) { i6300esb_debug("addr = %x\n", (int) addr); return 0; } -static void i6300esb_mem_writeb(void *vp, target_phys_addr_t addr, uint32_t val) +static void i6300esb_mem_writeb(void *vp, a_target_phys_addr addr, uint32_t val) { I6300State *d = (I6300State *) vp; @@ -291,7 +291,7 @@ static void i6300esb_mem_writeb(void *vp, target_phys_addr_t addr, uint32_t val) d->unlock_state = 2; } -static void i6300esb_mem_writew(void *vp, target_phys_addr_t addr, uint32_t val) +static void i6300esb_mem_writew(void *vp, a_target_phys_addr addr, uint32_t val) { I6300State *d = (I6300State *) vp; @@ -324,7 +324,7 @@ static void i6300esb_mem_writew(void *vp, target_phys_addr_t addr, uint32_t val) } } -static void i6300esb_mem_writel(void *vp, target_phys_addr_t addr, uint32_t val) +static void i6300esb_mem_writel(void *vp, a_target_phys_addr addr, uint32_t val) { I6300State *d = (I6300State *) vp; diff --git a/hw/xen_machine_pv.c b/hw/xen_machine_pv.c index 162f88db33..2199e22fbe 100644 --- a/hw/xen_machine_pv.c +++ b/hw/xen_machine_pv.c @@ -32,7 +32,7 @@ uint32_t xen_domid; enum xen_mode xen_mode = XEN_EMULATE; -static void xen_init_pv(ram_addr_t ram_size, +static void xen_init_pv(a_ram_addr ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, diff --git a/hw/xilinx.h b/hw/xilinx.h index 070679c24f..a128f9cd97 100644 --- a/hw/xilinx.h +++ b/hw/xilinx.h @@ -3,7 +3,7 @@ qemu_irq *microblaze_pic_init_cpu(CPUState *env); static inline DeviceState * -xilinx_intc_create(target_phys_addr_t base, qemu_irq irq, int kind_of_intr) +xilinx_intc_create(a_target_phys_addr base, qemu_irq irq, int kind_of_intr) { DeviceState *dev; @@ -17,7 +17,7 @@ xilinx_intc_create(target_phys_addr_t base, qemu_irq irq, int kind_of_intr) /* OPB Timer/Counter. */ static inline DeviceState * -xilinx_timer_create(target_phys_addr_t base, qemu_irq irq, int nr, int freq) +xilinx_timer_create(a_target_phys_addr base, qemu_irq irq, int nr, int freq) { DeviceState *dev; @@ -32,7 +32,7 @@ xilinx_timer_create(target_phys_addr_t base, qemu_irq irq, int nr, int freq) /* XPS Ethernet Lite MAC. */ static inline DeviceState * -xilinx_ethlite_create(NICInfo *nd, target_phys_addr_t base, qemu_irq irq, +xilinx_ethlite_create(NICInfo *nd, a_target_phys_addr base, qemu_irq irq, int txpingpong, int rxpingpong) { DeviceState *dev; diff --git a/hw/xilinx_ethlite.c b/hw/xilinx_ethlite.c index 9b0074c788..27959070e6 100644 --- a/hw/xilinx_ethlite.c +++ b/hw/xilinx_ethlite.c @@ -70,7 +70,7 @@ static inline void eth_pulse_irq(struct xlx_ethlite *s) } } -static uint32_t eth_readl (void *opaque, target_phys_addr_t addr) +static uint32_t eth_readl (void *opaque, a_target_phys_addr addr) { struct xlx_ethlite *s = opaque; uint32_t r = 0; @@ -103,7 +103,7 @@ static uint32_t eth_readl (void *opaque, target_phys_addr_t addr) } static void -eth_writel (void *opaque, target_phys_addr_t addr, uint32_t value) +eth_writel (void *opaque, a_target_phys_addr addr, uint32_t value) { struct xlx_ethlite *s = opaque; unsigned int base = 0; diff --git a/hw/xilinx_intc.c b/hw/xilinx_intc.c index 8ef6474fba..aae3a03046 100644 --- a/hw/xilinx_intc.c +++ b/hw/xilinx_intc.c @@ -72,7 +72,7 @@ static void update_irq(struct xlx_pic *p) } } -static uint32_t pic_readl (void *opaque, target_phys_addr_t addr) +static uint32_t pic_readl (void *opaque, a_target_phys_addr addr) { struct xlx_pic *p = opaque; uint32_t r = 0; @@ -91,7 +91,7 @@ static uint32_t pic_readl (void *opaque, target_phys_addr_t addr) } static void -pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value) +pic_writel (void *opaque, a_target_phys_addr addr, uint32_t value) { struct xlx_pic *p = opaque; diff --git a/hw/xilinx_timer.c b/hw/xilinx_timer.c index e2d9541cda..68d6c1886e 100644 --- a/hw/xilinx_timer.c +++ b/hw/xilinx_timer.c @@ -66,7 +66,7 @@ struct timerblock struct xlx_timer *timers; }; -static inline unsigned int timer_from_addr(target_phys_addr_t addr) +static inline unsigned int timer_from_addr(a_target_phys_addr addr) { /* Timers get a 4x32bit control reg area each. */ return addr >> 2; @@ -86,7 +86,7 @@ static void timer_update_irq(struct timerblock *t) qemu_set_irq(t->irq, !!irq); } -static uint32_t timer_readl (void *opaque, target_phys_addr_t addr) +static uint32_t timer_readl (void *opaque, a_target_phys_addr addr) { struct timerblock *t = opaque; struct xlx_timer *xt; @@ -135,7 +135,7 @@ static void timer_enable(struct xlx_timer *xt) } static void -timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value) +timer_writel (void *opaque, a_target_phys_addr addr, uint32_t value) { struct timerblock *t = opaque; struct xlx_timer *xt; diff --git a/hw/xilinx_uartlite.c b/hw/xilinx_uartlite.c index adab759fdb..7f2e664b40 100644 --- a/hw/xilinx_uartlite.c +++ b/hw/xilinx_uartlite.c @@ -82,7 +82,7 @@ static void uart_update_status(struct xlx_uartlite *s) s->regs[R_STATUS] = r; } -static uint32_t uart_readl (void *opaque, target_phys_addr_t addr) +static uint32_t uart_readl (void *opaque, a_target_phys_addr addr) { struct xlx_uartlite *s = opaque; uint32_t r = 0; @@ -107,7 +107,7 @@ static uint32_t uart_readl (void *opaque, target_phys_addr_t addr) } static void -uart_writel (void *opaque, target_phys_addr_t addr, uint32_t value) +uart_writel (void *opaque, a_target_phys_addr addr, uint32_t value) { struct xlx_uartlite *s = opaque; unsigned char ch = value; diff --git a/hw/zaurus.c b/hw/zaurus.c index db6ba75ced..4ad84ee1ff 100644 --- a/hw/zaurus.c +++ b/hw/zaurus.c @@ -66,7 +66,7 @@ static inline void scoop_gpio_handler_update(ScoopInfo *s) { s->prev_level = level; } -static uint32_t scoop_readb(void *opaque, target_phys_addr_t addr) +static uint32_t scoop_readb(void *opaque, a_target_phys_addr addr) { ScoopInfo *s = (ScoopInfo *) opaque; @@ -99,7 +99,7 @@ static uint32_t scoop_readb(void *opaque, target_phys_addr_t addr) return 0; } -static void scoop_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) +static void scoop_writeb(void *opaque, a_target_phys_addr addr, uint32_t value) { ScoopInfo *s = (ScoopInfo *) opaque; value &= 0xffff; @@ -217,7 +217,7 @@ static int scoop_load(QEMUFile *f, void *opaque, int version_id) ScoopInfo *scoop_init(PXA2xxState *cpu, int instance, - target_phys_addr_t target_base) { + a_target_phys_addr target_base) { int iomemtype; ScoopInfo *s; @@ -270,7 +270,7 @@ static struct __attribute__ ((__packed__)) sl_param_info { .phadadj = 0x01, }; -void sl_bootparam_write(target_phys_addr_t ptr) +void sl_bootparam_write(a_target_phys_addr ptr) { cpu_physical_memory_write(ptr, (void *)&zaurus_bootparam, sizeof(struct sl_param_info)); diff --git a/ioport-user.c b/ioport-user.c index 03fac22d22..4b2c64b8c9 100644 --- a/ioport-user.c +++ b/ioport-user.c @@ -23,37 +23,37 @@ #include "qemu-common.h" #include "ioport.h" -void cpu_outb(pio_addr_t addr, uint8_t val) +void cpu_outb(a_pio_addr addr, uint8_t val) { fprintf(stderr, "outb: port=0x%04"FMT_pioaddr", data=%02"PRIx8"\n", addr, val); } -void cpu_outw(pio_addr_t addr, uint16_t val) +void cpu_outw(a_pio_addr addr, uint16_t val) { fprintf(stderr, "outw: port=0x%04"FMT_pioaddr", data=%04"PRIx16"\n", addr, val); } -void cpu_outl(pio_addr_t addr, uint32_t val) +void cpu_outl(a_pio_addr addr, uint32_t val) { fprintf(stderr, "outl: port=0x%04"FMT_pioaddr", data=%08"PRIx32"\n", addr, val); } -uint8_t cpu_inb(pio_addr_t addr) +uint8_t cpu_inb(a_pio_addr addr) { fprintf(stderr, "inb: port=0x%04"FMT_pioaddr"\n", addr); return 0; } -uint16_t cpu_inw(pio_addr_t addr) +uint16_t cpu_inw(a_pio_addr addr) { fprintf(stderr, "inw: port=0x%04"FMT_pioaddr"\n", addr); return 0; } -uint32_t cpu_inl(pio_addr_t addr) +uint32_t cpu_inl(a_pio_addr addr) { fprintf(stderr, "inl: port=0x%04"FMT_pioaddr"\n", addr); return 0; @@ -136,7 +136,7 @@ static int ioport_bsize(int size, int *bsize) } /* size is the word size in byte */ -int register_ioport_read(pio_addr_t start, int length, int size, +int register_ioport_read(a_pio_addr start, int length, int size, IOPortReadFunc *func, void *opaque) { int i, bsize; @@ -155,7 +155,7 @@ int register_ioport_read(pio_addr_t start, int length, int size, } /* size is the word size in byte */ -int register_ioport_write(pio_addr_t start, int length, int size, +int register_ioport_write(a_pio_addr start, int length, int size, IOPortWriteFunc *func, void *opaque) { int i, bsize; @@ -173,7 +173,7 @@ int register_ioport_write(pio_addr_t start, int length, int size, return 0; } -void isa_unassign_ioport(pio_addr_t start, int length) +void isa_unassign_ioport(a_pio_addr start, int length) { int i; @@ -192,25 +192,25 @@ void isa_unassign_ioport(pio_addr_t start, int length) /***********************************************************/ -void cpu_outb(pio_addr_t addr, uint8_t val) +void cpu_outb(a_pio_addr addr, uint8_t val) { LOG_IOPORT("outb: %04"FMT_pioaddr" %02"PRIx8"\n", addr, val); ioport_write(0, addr, val); } -void cpu_outw(pio_addr_t addr, uint16_t val) +void cpu_outw(a_pio_addr addr, uint16_t val) { LOG_IOPORT("outw: %04"FMT_pioaddr" %04"PRIx16"\n", addr, val); ioport_write(1, addr, val); } -void cpu_outl(pio_addr_t addr, uint32_t val) +void cpu_outl(a_pio_addr addr, uint32_t val) { LOG_IOPORT("outl: %04"FMT_pioaddr" %08"PRIx32"\n", addr, val); ioport_write(2, addr, val); } -uint8_t cpu_inb(pio_addr_t addr) +uint8_t cpu_inb(a_pio_addr addr) { uint8_t val; val = ioport_read(0, addr); @@ -218,7 +218,7 @@ uint8_t cpu_inb(pio_addr_t addr) return val; } -uint16_t cpu_inw(pio_addr_t addr) +uint16_t cpu_inw(a_pio_addr addr) { uint16_t val; val = ioport_read(1, addr); @@ -226,7 +226,7 @@ uint16_t cpu_inw(pio_addr_t addr) return val; } -uint32_t cpu_inl(pio_addr_t addr) +uint32_t cpu_inl(a_pio_addr addr) { uint32_t val; val = ioport_read(2, addr); @@ -26,7 +26,7 @@ #include "qemu-common.h" -typedef uint32_t pio_addr_t; +typedef uint32_t a_pio_addr; #define FMT_pioaddr PRIx32 #define MAX_IOPORTS (64 * 1024) @@ -36,18 +36,18 @@ typedef uint32_t pio_addr_t; typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data); typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address); -int register_ioport_read(pio_addr_t start, int length, int size, +int register_ioport_read(a_pio_addr start, int length, int size, IOPortReadFunc *func, void *opaque); -int register_ioport_write(pio_addr_t start, int length, int size, +int register_ioport_write(a_pio_addr start, int length, int size, IOPortWriteFunc *func, void *opaque); -void isa_unassign_ioport(pio_addr_t start, int length); +void isa_unassign_ioport(a_pio_addr start, int length); -void cpu_outb(pio_addr_t addr, uint8_t val); -void cpu_outw(pio_addr_t addr, uint16_t val); -void cpu_outl(pio_addr_t addr, uint32_t val); -uint8_t cpu_inb(pio_addr_t addr); -uint16_t cpu_inw(pio_addr_t addr); -uint32_t cpu_inl(pio_addr_t addr); +void cpu_outb(a_pio_addr addr, uint8_t val); +void cpu_outw(a_pio_addr addr, uint16_t val); +void cpu_outl(a_pio_addr addr, uint32_t val); +uint8_t cpu_inb(a_pio_addr addr); +uint16_t cpu_inw(a_pio_addr addr); +uint32_t cpu_inl(a_pio_addr addr); #endif /* IOPORT_H */ @@ -25,10 +25,10 @@ #include "keymaps.h" #include "sysemu.h" -static int get_keysym(const name2keysym_t *table, +static int get_keysym(const a_name2keysym *table, const char *name) { - const name2keysym_t *p; + const a_name2keysym *p; for(p = table; p->name != NULL; p++) { if (!strcmp(p->name, name)) return p->keysym; @@ -59,9 +59,9 @@ static void add_to_key_range(struct key_range **krp, int code) { } } -static kbd_layout_t *parse_keyboard_layout(const name2keysym_t *table, +static a_kbd_layout *parse_keyboard_layout(const a_name2keysym *table, const char *language, - kbd_layout_t * k) + a_kbd_layout * k) { FILE *f; char * filename; @@ -71,7 +71,7 @@ static kbd_layout_t *parse_keyboard_layout(const name2keysym_t *table, filename = qemu_find_file(QEMU_FILE_TYPE_KEYMAP, language); if (!k) - k = qemu_mallocz(sizeof(kbd_layout_t)); + k = qemu_mallocz(sizeof(a_kbd_layout)); if (!(filename && (f = fopen(filename, "r")))) { fprintf(stderr, "Could not read keymap file: '%s'\n", language); @@ -142,7 +142,7 @@ static kbd_layout_t *parse_keyboard_layout(const name2keysym_t *table, } -void *init_keyboard_layout(const name2keysym_t *table, const char *language) +void *init_keyboard_layout(const a_name2keysym *table, const char *language) { return parse_keyboard_layout(table, language, NULL); } @@ -150,7 +150,7 @@ void *init_keyboard_layout(const name2keysym_t *table, const char *language) int keysym2scancode(void *kbd_layout, int keysym) { - kbd_layout_t *k = kbd_layout; + a_kbd_layout *k = kbd_layout; if (keysym < MAX_NORMAL_KEYCODE) { if (k->keysym2keycode[keysym] == 0) fprintf(stderr, "Warning: no scancode found for keysym %d\n", @@ -171,7 +171,7 @@ int keysym2scancode(void *kbd_layout, int keysym) int keycode_is_keypad(void *kbd_layout, int keycode) { - kbd_layout_t *k = kbd_layout; + a_kbd_layout *k = kbd_layout; struct key_range *kr; for (kr = k->keypad_range; kr; kr = kr->next) @@ -182,7 +182,7 @@ int keycode_is_keypad(void *kbd_layout, int keycode) int keysym_is_numlock(void *kbd_layout, int keysym) { - kbd_layout_t *k = kbd_layout; + a_kbd_layout *k = kbd_layout; struct key_range *kr; for (kr = k->numlock_range; kr; kr = kr->next) @@ -30,7 +30,7 @@ typedef struct { const char* name; int keysym; -} name2keysym_t; +} a_name2keysym; struct key_range { int start; @@ -49,10 +49,10 @@ typedef struct { int extra_count; struct key_range *keypad_range; struct key_range *numlock_range; -} kbd_layout_t; +} a_kbd_layout; -void *init_keyboard_layout(const name2keysym_t *table, const char *language); +void *init_keyboard_layout(const a_name2keysym *table, const char *language); int keysym2scancode(void *kbd_layout, int keysym); int keycode_is_keypad(void *kbd_layout, int keycode); int keysym_is_numlock(void *kbd_layout, int keysym); @@ -41,9 +41,9 @@ typedef struct KVMSlot { - target_phys_addr_t start_addr; - ram_addr_t memory_size; - ram_addr_t phys_offset; + a_target_phys_addr start_addr; + a_ram_addr memory_size; + a_ram_addr phys_offset; int slot; int flags; } KVMSlot; @@ -87,8 +87,8 @@ static KVMSlot *kvm_alloc_slot(KVMState *s) } static KVMSlot *kvm_lookup_matching_slot(KVMState *s, - target_phys_addr_t start_addr, - target_phys_addr_t end_addr) + a_target_phys_addr start_addr, + a_target_phys_addr end_addr) { int i; @@ -108,8 +108,8 @@ static KVMSlot *kvm_lookup_matching_slot(KVMState *s, * Find overlapping slot with lowest start address */ static KVMSlot *kvm_lookup_overlapping_slot(KVMState *s, - target_phys_addr_t start_addr, - target_phys_addr_t end_addr) + a_target_phys_addr start_addr, + a_target_phys_addr end_addr) { KVMSlot *found = NULL; int i; @@ -230,8 +230,8 @@ int kvm_get_mp_state(CPUState *env) /* * dirty pages logging control */ -static int kvm_dirty_pages_log_change(target_phys_addr_t phys_addr, - ram_addr_t size, int flags, int mask) +static int kvm_dirty_pages_log_change(a_target_phys_addr phys_addr, + a_ram_addr size, int flags, int mask) { KVMState *s = kvm_state; KVMSlot *mem = kvm_lookup_matching_slot(s, phys_addr, phys_addr + size); @@ -240,7 +240,7 @@ static int kvm_dirty_pages_log_change(target_phys_addr_t phys_addr, if (mem == NULL) { fprintf(stderr, "BUG: %s: invalid parameters " TARGET_FMT_plx "-" TARGET_FMT_plx "\n", __func__, phys_addr, - (target_phys_addr_t)(phys_addr + size - 1)); + (a_target_phys_addr)(phys_addr + size - 1)); return -EINVAL; } @@ -260,14 +260,14 @@ static int kvm_dirty_pages_log_change(target_phys_addr_t phys_addr, return kvm_set_user_memory_region(s, mem); } -int kvm_log_start(target_phys_addr_t phys_addr, ram_addr_t size) +int kvm_log_start(a_target_phys_addr phys_addr, a_ram_addr size) { return kvm_dirty_pages_log_change(phys_addr, size, KVM_MEM_LOG_DIRTY_PAGES, KVM_MEM_LOG_DIRTY_PAGES); } -int kvm_log_stop(target_phys_addr_t phys_addr, ram_addr_t size) +int kvm_log_stop(a_target_phys_addr phys_addr, a_ram_addr size) { return kvm_dirty_pages_log_change(phys_addr, size, 0, @@ -309,13 +309,13 @@ static int test_le_bit(unsigned long nr, unsigned char *addr) * @start_add: start of logged region. * @end_addr: end of logged region. */ -int kvm_physical_sync_dirty_bitmap(target_phys_addr_t start_addr, - target_phys_addr_t end_addr) +int kvm_physical_sync_dirty_bitmap(a_target_phys_addr start_addr, + a_target_phys_addr end_addr) { KVMState *s = kvm_state; unsigned long size, allocated_size = 0; - target_phys_addr_t phys_addr; - ram_addr_t addr; + a_target_phys_addr phys_addr; + a_ram_addr addr; KVMDirtyLog d; KVMSlot *mem; int ret = 0; @@ -361,7 +361,7 @@ int kvm_physical_sync_dirty_bitmap(target_phys_addr_t start_addr, return ret; } -int kvm_coalesce_mmio_region(target_phys_addr_t start, ram_addr_t size) +int kvm_coalesce_mmio_region(a_target_phys_addr start, a_ram_addr size) { int ret = -ENOSYS; #ifdef KVM_CAP_COALESCED_MMIO @@ -380,7 +380,7 @@ int kvm_coalesce_mmio_region(target_phys_addr_t start, ram_addr_t size) return ret; } -int kvm_uncoalesce_mmio_region(target_phys_addr_t start, ram_addr_t size) +int kvm_uncoalesce_mmio_region(a_target_phys_addr start, a_ram_addr size) { int ret = -ENOSYS; #ifdef KVM_CAP_COALESCED_MMIO @@ -684,12 +684,12 @@ int kvm_cpu_exec(CPUState *env) return ret; } -void kvm_set_phys_mem(target_phys_addr_t start_addr, - ram_addr_t size, - ram_addr_t phys_offset) +void kvm_set_phys_mem(a_target_phys_addr start_addr, + a_ram_addr size, + a_ram_addr phys_offset) { KVMState *s = kvm_state; - ram_addr_t flags = phys_offset & ~TARGET_PAGE_MASK; + a_ram_addr flags = phys_offset & ~TARGET_PAGE_MASK; KVMSlot *mem, old; int err; @@ -782,7 +782,7 @@ void kvm_set_phys_mem(target_phys_addr_t start_addr, /* register suffix slot */ if (old.start_addr + old.memory_size > start_addr + size) { - ram_addr_t size_delta; + a_ram_addr size_delta; mem = kvm_alloc_slot(s); mem->start_addr = start_addr + size; @@ -35,23 +35,23 @@ int kvm_init_vcpu(CPUState *env); int kvm_cpu_exec(CPUState *env); -void kvm_set_phys_mem(target_phys_addr_t start_addr, - ram_addr_t size, - ram_addr_t phys_offset); +void kvm_set_phys_mem(a_target_phys_addr start_addr, + a_ram_addr size, + a_ram_addr phys_offset); -int kvm_physical_sync_dirty_bitmap(target_phys_addr_t start_addr, - target_phys_addr_t end_addr); +int kvm_physical_sync_dirty_bitmap(a_target_phys_addr start_addr, + a_target_phys_addr end_addr); -int kvm_log_start(target_phys_addr_t phys_addr, ram_addr_t size); -int kvm_log_stop(target_phys_addr_t phys_addr, ram_addr_t size); +int kvm_log_start(a_target_phys_addr phys_addr, a_ram_addr size); +int kvm_log_stop(a_target_phys_addr phys_addr, a_ram_addr size); int kvm_set_migration_log(int enable); int kvm_has_sync_mmu(void); void kvm_setup_guest_memory(void *start, size_t size); -int kvm_coalesce_mmio_region(target_phys_addr_t start, ram_addr_t size); -int kvm_uncoalesce_mmio_region(target_phys_addr_t start, ram_addr_t size); +int kvm_coalesce_mmio_region(a_target_phys_addr start, a_ram_addr size); +int kvm_uncoalesce_mmio_region(a_target_phys_addr start, a_ram_addr size); int kvm_insert_breakpoint(CPUState *current_env, target_ulong addr, target_ulong len, int type); diff --git a/linux-user/alpha/target_signal.h b/linux-user/alpha/target_signal.h index 2382ffdb6e..d73c44eb5e 100644 --- a/linux-user/alpha/target_signal.h +++ b/linux-user/alpha/target_signal.h @@ -9,7 +9,7 @@ typedef struct target_sigaltstack { abi_ulong ss_sp; abi_long ss_flags; abi_ulong ss_size; -} target_stack_t; +} a_target_stack; /* diff --git a/linux-user/alpha/termbits.h b/linux-user/alpha/termbits.h index 6406b6a799..56ab3eb432 100644 --- a/linux-user/alpha/termbits.h +++ b/linux-user/alpha/termbits.h @@ -1,17 +1,17 @@ -typedef unsigned char target_cc_t; -typedef unsigned int target_speed_t; -typedef unsigned int target_tcflag_t; +typedef unsigned char a_target_cc; +typedef unsigned int a_target_speed; +typedef unsigned int a_target_tcflag; #define TARGET_NCCS 19 struct target_termios { - target_tcflag_t c_iflag; /* input mode flags */ - target_tcflag_t c_oflag; /* output mode flags */ - target_tcflag_t c_cflag; /* control mode flags */ - target_tcflag_t c_lflag; /* local mode flags */ - target_cc_t c_cc[TARGET_NCCS]; /* control characters */ - target_cc_t c_line; /* line discipline (== c_cc[19]) */ - target_speed_t c_ispeed; /* input speed */ - target_speed_t c_ospeed; /* output speed */ + a_target_tcflag c_iflag; /* input mode flags */ + a_target_tcflag c_oflag; /* output mode flags */ + a_target_tcflag c_cflag; /* control mode flags */ + a_target_tcflag c_lflag; /* local mode flags */ + a_target_cc c_cc[TARGET_NCCS]; /* control characters */ + a_target_cc c_line; /* line discipline (== c_cc[19]) */ + a_target_speed c_ispeed; /* input speed */ + a_target_speed c_ospeed; /* output speed */ }; /* c_cc characters */ diff --git a/linux-user/arm/target_signal.h b/linux-user/arm/target_signal.h index 2b3281312b..71cc0c4321 100644 --- a/linux-user/arm/target_signal.h +++ b/linux-user/arm/target_signal.h @@ -9,7 +9,7 @@ typedef struct target_sigaltstack { abi_ulong ss_sp; abi_long ss_flags; abi_ulong ss_size; -} target_stack_t; +} a_target_stack; /* diff --git a/linux-user/cris/target_signal.h b/linux-user/cris/target_signal.h index 5611840f83..d0e7aec7dc 100644 --- a/linux-user/cris/target_signal.h +++ b/linux-user/cris/target_signal.h @@ -9,7 +9,7 @@ typedef struct target_sigaltstack { abi_ulong ss_sp; abi_ulong ss_size; abi_long ss_flags; -} target_stack_t; +} a_target_stack; /* diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 07277a6a22..8f2049b2b2 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -134,13 +134,13 @@ static inline void init_thread(struct target_pt_regs *regs, struct image_info *i regs->rip = infop->entry; } -typedef target_ulong target_elf_greg_t; -typedef uint32_t target_uid_t; -typedef uint32_t target_gid_t; -typedef int32_t target_pid_t; +typedef target_ulong a_target_elf_greg; +typedef uint32_t a_target_uid; +typedef uint32_t a_target_gid; +typedef int32_t a_target_pid; #define ELF_NREG 27 -typedef target_elf_greg_t target_elf_gregset_t[ELF_NREG]; +typedef a_target_elf_greg a_target_elf_gregset[ELF_NREG]; /* * Note that ELF_NREG should be 29 as there should be place for @@ -149,7 +149,7 @@ typedef target_elf_greg_t target_elf_gregset_t[ELF_NREG]; * * See linux kernel: arch/x86/include/asm/elf.h */ -static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUState *env) +static void elf_core_copy_regs(a_target_elf_gregset *regs, const CPUState *env) { (*regs)[0] = env->regs[15]; (*regs)[1] = env->regs[14]; @@ -211,13 +211,13 @@ static inline void init_thread(struct target_pt_regs *regs, struct image_info *i regs->edx = 0; } -typedef target_ulong target_elf_greg_t; -typedef uint16_t target_uid_t; -typedef uint16_t target_gid_t; -typedef int32_t target_pid_t; +typedef target_ulong a_target_elf_greg; +typedef uint16_t a_target_uid; +typedef uint16_t a_target_gid; +typedef int32_t a_target_pid; #define ELF_NREG 17 -typedef target_elf_greg_t target_elf_gregset_t[ELF_NREG]; +typedef a_target_elf_greg a_target_elf_gregset[ELF_NREG]; /* * Note that ELF_NREG should be 19 as there should be place for @@ -226,7 +226,7 @@ typedef target_elf_greg_t target_elf_gregset_t[ELF_NREG]; * * See linux kernel: arch/x86/include/asm/elf.h */ -static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUState *env) +static void elf_core_copy_regs(a_target_elf_gregset *regs, const CPUState *env) { (*regs)[0] = env->regs[R_EBX]; (*regs)[1] = env->regs[R_ECX]; @@ -286,15 +286,15 @@ static inline void init_thread(struct target_pt_regs *regs, struct image_info *i regs->ARM_r10 = infop->start_data; } -typedef uint32_t target_elf_greg_t; -typedef uint16_t target_uid_t; -typedef uint16_t target_gid_t; -typedef int32_t target_pid_t; +typedef uint32_t a_target_elf_greg; +typedef uint16_t a_target_uid; +typedef uint16_t a_target_gid; +typedef int32_t a_target_pid; #define ELF_NREG 18 -typedef target_elf_greg_t target_elf_gregset_t[ELF_NREG]; +typedef a_target_elf_greg a_target_elf_gregset[ELF_NREG]; -static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUState *env) +static void elf_core_copy_regs(a_target_elf_gregset *regs, const CPUState *env) { (*regs)[0] = env->regs[0]; (*regs)[1] = env->regs[1]; @@ -1768,21 +1768,21 @@ int load_elf_binary(struct linux_binprm * bprm, struct target_pt_regs * regs, * Next you define type of register set used for dumping. ELF specification * says that it needs to be array of elf_greg_t that has size of ELF_NREG. * - * typedef <target_regtype> target_elf_greg_t; + * typedef <target_regtype> a_target_elf_greg; * #define ELF_NREG <number of registers> - * typedef taret_elf_greg_t target_elf_gregset_t[ELF_NREG]; + * typedef a_taret_elf_greg a_target_elf_gregset[ELF_NREG]; * * Then define following types to match target types. Actual types can * be found from linux kernel (arch/<ARCH>/include/asm/posix_types.h): * - * typedef <target_uid_type> target_uid_t; - * typedef <target_gid_type> target_gid_t; - * typedef <target_pid_type> target_pid_t; + * typedef <target_uid_type> a_target_uid; + * typedef <target_gid_type> a_target_gid; + * typedef <target_pid_type> a_target_pid; * * Last step is to implement target specific function that copies registers * from given cpu into just specified register set. Prototype is: * - * static void elf_core_copy_regs(taret_elf_gregset_t *regs, + * static void elf_core_copy_regs(a_taret_elf_gregset *regs, * const CPUState *env); * * Parameters: @@ -1814,15 +1814,15 @@ struct target_elf_prstatus { short pr_cursig; /* Current signal */ target_ulong pr_sigpend; /* XXX */ target_ulong pr_sighold; /* XXX */ - target_pid_t pr_pid; - target_pid_t pr_ppid; - target_pid_t pr_pgrp; - target_pid_t pr_sid; + a_target_pid pr_pid; + a_target_pid pr_ppid; + a_target_pid pr_pgrp; + a_target_pid pr_sid; struct target_timeval pr_utime; /* XXX User time */ struct target_timeval pr_stime; /* XXX System time */ struct target_timeval pr_cutime; /* XXX Cumulative user time */ struct target_timeval pr_cstime; /* XXX Cumulative system time */ - target_elf_gregset_t pr_reg; /* GP registers */ + a_target_elf_gregset pr_reg; /* GP registers */ int pr_fpvalid; /* XXX */ }; @@ -1834,9 +1834,9 @@ struct target_elf_prpsinfo { char pr_zomb; /* zombie */ char pr_nice; /* nice val */ target_ulong pr_flag; /* flags */ - target_uid_t pr_uid; - target_gid_t pr_gid; - target_pid_t pr_pid, pr_ppid, pr_pgrp, pr_sid; + a_target_uid pr_uid; + a_target_gid pr_gid; + a_target_pid pr_pid, pr_ppid, pr_pgrp, pr_sid; /* Lots missing */ char pr_fname[16]; /* filename of executable */ char pr_psargs[ELF_PRARGSZ]; /* initial part of arg list */ diff --git a/linux-user/i386/target_signal.h b/linux-user/i386/target_signal.h index 9baf7fbeb5..da86689f1f 100644 --- a/linux-user/i386/target_signal.h +++ b/linux-user/i386/target_signal.h @@ -9,7 +9,7 @@ typedef struct target_sigaltstack { abi_ulong ss_sp; abi_long ss_flags; abi_ulong ss_size; -} target_stack_t; +} a_target_stack; /* diff --git a/linux-user/m68k/target_signal.h b/linux-user/m68k/target_signal.h index 479758a421..964c55bce5 100644 --- a/linux-user/m68k/target_signal.h +++ b/linux-user/m68k/target_signal.h @@ -9,7 +9,7 @@ typedef struct target_sigaltstack { abi_ulong ss_sp; abi_long ss_flags; abi_ulong ss_size; -} target_stack_t; +} a_target_stack; /* diff --git a/linux-user/main.c b/linux-user/main.c index 81a1ada50b..4474c9003b 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -303,7 +303,7 @@ void cpu_loop(CPUX86State *env) { int trapnr; abi_ulong pc; - target_siginfo_t info; + a_target_siginfo info; for(;;) { trapnr = cpu_x86_exec(env); @@ -528,7 +528,7 @@ void cpu_loop(CPUARMState *env) { int trapnr; unsigned int n, insn; - target_siginfo_t info; + a_target_siginfo info; uint32_t addr; for(;;) { @@ -856,7 +856,7 @@ static void flush_windows(CPUSPARCState *env) void cpu_loop (CPUSPARCState *env) { int trapnr, ret; - target_siginfo_t info; + a_target_siginfo info; while (1) { trapnr = cpu_sparc_exec (env); @@ -1015,12 +1015,12 @@ uint32_t cpu_ppc601_load_rtcl (CPUState *env) } /* XXX: to be fixed */ -int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp) +int ppc_dcr_read (a_ppc_dcr *dcr_env, int dcrn, target_ulong *valp) { return -1; } -int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val) +int ppc_dcr_write (a_ppc_dcr *dcr_env, int dcrn, target_ulong val) { return -1; } @@ -1093,7 +1093,7 @@ static int do_store_exclusive(CPUPPCState *env) void cpu_loop(CPUPPCState *env) { - target_siginfo_t info; + a_target_siginfo info; int trapnr; uint32_t ret; @@ -1890,7 +1890,7 @@ static int do_store_exclusive(CPUMIPSState *env) void cpu_loop(CPUMIPSState *env) { - target_siginfo_t info; + a_target_siginfo info; int trapnr, ret; unsigned int syscall_num; @@ -1999,7 +1999,7 @@ void cpu_loop(CPUMIPSState *env) void cpu_loop (CPUState *env) { int trapnr, ret; - target_siginfo_t info; + a_target_siginfo info; while (1) { trapnr = cpu_sh4_exec (env); @@ -2057,7 +2057,7 @@ void cpu_loop (CPUState *env) void cpu_loop (CPUState *env) { int trapnr, ret; - target_siginfo_t info; + a_target_siginfo info; while (1) { trapnr = cpu_cris_exec (env); @@ -2114,7 +2114,7 @@ void cpu_loop (CPUState *env) void cpu_loop (CPUState *env) { int trapnr, ret; - target_siginfo_t info; + a_target_siginfo info; while (1) { trapnr = cpu_mb_exec (env); @@ -2176,7 +2176,7 @@ void cpu_loop(CPUM68KState *env) { int trapnr; unsigned int n; - target_siginfo_t info; + a_target_siginfo info; TaskState *ts = env->opaque; for(;;) { @@ -2266,7 +2266,7 @@ void cpu_loop(CPUM68KState *env) void cpu_loop (CPUState *env) { int trapnr; - target_siginfo_t info; + a_target_siginfo info; while (1) { trapnr = cpu_alpha_exec (env); diff --git a/linux-user/microblaze/target_signal.h b/linux-user/microblaze/target_signal.h index 3d1f7a7238..a91b21dbdb 100644 --- a/linux-user/microblaze/target_signal.h +++ b/linux-user/microblaze/target_signal.h @@ -9,7 +9,7 @@ typedef struct target_sigaltstack { abi_ulong ss_sp; abi_ulong ss_size; abi_long ss_flags; -} target_stack_t; +} a_target_stack; /* diff --git a/linux-user/mips/target_signal.h b/linux-user/mips/target_signal.h index 6e1dc8b6e6..13c2d1987a 100644 --- a/linux-user/mips/target_signal.h +++ b/linux-user/mips/target_signal.h @@ -9,7 +9,7 @@ typedef struct target_sigaltstack { abi_long ss_sp; abi_ulong ss_size; abi_long ss_flags; -} target_stack_t; +} a_target_stack; /* diff --git a/linux-user/mips64/target_signal.h b/linux-user/mips64/target_signal.h index 6e1dc8b6e6..13c2d1987a 100644 --- a/linux-user/mips64/target_signal.h +++ b/linux-user/mips64/target_signal.h @@ -9,7 +9,7 @@ typedef struct target_sigaltstack { abi_long ss_sp; abi_ulong ss_size; abi_long ss_flags; -} target_stack_t; +} a_target_stack; /* diff --git a/linux-user/mipsn32/target_signal.h b/linux-user/mipsn32/target_signal.h index ff20d9e33e..8946792a9a 100644 --- a/linux-user/mipsn32/target_signal.h +++ b/linux-user/mipsn32/target_signal.h @@ -9,7 +9,7 @@ typedef struct target_sigaltstack { int32_t ss_sp; uint32_t ss_size; int32_t ss_flags; -} target_stack_t; +} a_target_stack; /* diff --git a/linux-user/ppc/target_signal.h b/linux-user/ppc/target_signal.h index a93b5cf1df..e25d776e40 100644 --- a/linux-user/ppc/target_signal.h +++ b/linux-user/ppc/target_signal.h @@ -9,7 +9,7 @@ typedef struct target_sigaltstack { abi_ulong ss_sp; int ss_flags; abi_ulong ss_size; -} target_stack_t; +} a_target_stack; /* diff --git a/linux-user/qemu.h b/linux-user/qemu.h index d129debb1f..8151c1b4b0 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -78,7 +78,7 @@ struct vm86_saved_state { struct sigqueue { struct sigqueue *next; - target_siginfo_t info; + a_target_siginfo info; }; struct emulated_sigtable { @@ -207,9 +207,9 @@ extern int do_strace; /* signal.c */ void process_pending_signals(CPUState *cpu_env); void signal_init(void); -int queue_signal(CPUState *env, int sig, target_siginfo_t *info); -void host_to_target_siginfo(target_siginfo_t *tinfo, const siginfo_t *info); -void target_to_host_siginfo(siginfo_t *info, const target_siginfo_t *tinfo); +int queue_signal(CPUState *env, int sig, a_target_siginfo *info); +void host_to_target_siginfo(a_target_siginfo *tinfo, const siginfo_t *info); +void target_to_host_siginfo(siginfo_t *info, const a_target_siginfo *tinfo); int target_to_host_signal(int sig); int host_to_target_signal(int sig); long do_sigreturn(CPUState *env); diff --git a/linux-user/sh4/target_signal.h b/linux-user/sh4/target_signal.h index e148da0925..a241a89e13 100644 --- a/linux-user/sh4/target_signal.h +++ b/linux-user/sh4/target_signal.h @@ -9,7 +9,7 @@ typedef struct target_sigaltstack { abi_ulong ss_sp; abi_long ss_flags; abi_ulong ss_size; -} target_stack_t; +} a_target_stack; /* diff --git a/linux-user/signal.c b/linux-user/signal.c index 2df17aa21b..a840ccf6f3 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -115,26 +115,26 @@ int target_to_host_signal(int sig) return target_to_host_signal_table[sig]; } -static inline void target_sigemptyset(target_sigset_t *set) +static inline void target_sigemptyset(a_target_sigset *set) { memset(set, 0, sizeof(*set)); } -static inline void target_sigaddset(target_sigset_t *set, int signum) +static inline void target_sigaddset(a_target_sigset *set, int signum) { signum--; abi_ulong mask = (abi_ulong)1 << (signum % TARGET_NSIG_BPW); set->sig[signum / TARGET_NSIG_BPW] |= mask; } -static inline int target_sigismember(const target_sigset_t *set, int signum) +static inline int target_sigismember(const a_target_sigset *set, int signum) { signum--; abi_ulong mask = (abi_ulong)1 << (signum % TARGET_NSIG_BPW); return ((set->sig[signum / TARGET_NSIG_BPW] & mask) != 0); } -static void host_to_target_sigset_internal(target_sigset_t *d, +static void host_to_target_sigset_internal(a_target_sigset *d, const sigset_t *s) { int i; @@ -146,9 +146,9 @@ static void host_to_target_sigset_internal(target_sigset_t *d, } } -void host_to_target_sigset(target_sigset_t *d, const sigset_t *s) +void host_to_target_sigset(a_target_sigset *d, const sigset_t *s) { - target_sigset_t d1; + a_target_sigset d1; int i; host_to_target_sigset_internal(&d1, s); @@ -157,7 +157,7 @@ void host_to_target_sigset(target_sigset_t *d, const sigset_t *s) } static void target_to_host_sigset_internal(sigset_t *d, - const target_sigset_t *s) + const a_target_sigset *s) { int i; sigemptyset(d); @@ -168,9 +168,9 @@ static void target_to_host_sigset_internal(sigset_t *d, } } -void target_to_host_sigset(sigset_t *d, const target_sigset_t *s) +void target_to_host_sigset(sigset_t *d, const a_target_sigset *s) { - target_sigset_t s1; + a_target_sigset s1; int i; for(i = 0;i < TARGET_NSIG_WORDS; i++) @@ -181,7 +181,7 @@ void target_to_host_sigset(sigset_t *d, const target_sigset_t *s) void host_to_target_old_sigset(abi_ulong *old_sigset, const sigset_t *sigset) { - target_sigset_t d; + a_target_sigset d; host_to_target_sigset(&d, sigset); *old_sigset = d.sig[0]; } @@ -189,7 +189,7 @@ void host_to_target_old_sigset(abi_ulong *old_sigset, void target_to_host_old_sigset(sigset_t *sigset, const abi_ulong *old_sigset) { - target_sigset_t d; + a_target_sigset d; int i; d.sig[0] = *old_sigset; @@ -200,7 +200,7 @@ void target_to_host_old_sigset(sigset_t *sigset, /* siginfo conversion */ -static inline void host_to_target_siginfo_noswap(target_siginfo_t *tinfo, +static inline void host_to_target_siginfo_noswap(a_target_siginfo *tinfo, const siginfo_t *info) { int sig; @@ -224,8 +224,8 @@ static inline void host_to_target_siginfo_noswap(target_siginfo_t *tinfo, } } -static void tswap_siginfo(target_siginfo_t *tinfo, - const target_siginfo_t *info) +static void tswap_siginfo(a_target_siginfo *tinfo, + const a_target_siginfo *info) { int sig; sig = info->si_signo; @@ -247,7 +247,7 @@ static void tswap_siginfo(target_siginfo_t *tinfo, } -void host_to_target_siginfo(target_siginfo_t *tinfo, const siginfo_t *info) +void host_to_target_siginfo(a_target_siginfo *tinfo, const siginfo_t *info) { host_to_target_siginfo_noswap(tinfo, info); tswap_siginfo(tinfo, tinfo); @@ -255,7 +255,7 @@ void host_to_target_siginfo(target_siginfo_t *tinfo, const siginfo_t *info) /* XXX: we support only POSIX RT signals are used. */ /* XXX: find a solution for 64 bit (additional malloced data is needed) */ -void target_to_host_siginfo(siginfo_t *info, const target_siginfo_t *tinfo) +void target_to_host_siginfo(siginfo_t *info, const a_target_siginfo *tinfo) { info->si_signo = tswap32(tinfo->si_signo); info->si_errno = tswap32(tinfo->si_errno); @@ -417,7 +417,7 @@ static void QEMU_NORETURN force_sig(int sig) /* queue a signal so that it will be send to the virtual CPU as soon as possible */ -int queue_signal(CPUState *env, int sig, target_siginfo_t *info) +int queue_signal(CPUState *env, int sig, a_target_siginfo *info) { TaskState *ts = env->opaque; struct emulated_sigtable *k; @@ -485,7 +485,7 @@ static void host_signal_handler(int host_signum, siginfo_t *info, void *puc) { int sig; - target_siginfo_t tinfo; + a_target_siginfo tinfo; /* the CPU emulator uses some host signals to detect exceptions, we forward to it some signals */ @@ -630,8 +630,8 @@ int do_sigaction(int sig, const struct target_sigaction *act, return ret; } -static inline int copy_siginfo_to_user(target_siginfo_t *tinfo, - const target_siginfo_t *info) +static inline int copy_siginfo_to_user(a_target_siginfo *tinfo, + const a_target_siginfo *info) { tswap_siginfo(tinfo, info); return 0; @@ -714,9 +714,9 @@ struct target_sigcontext { struct target_ucontext { abi_ulong tuc_flags; abi_ulong tuc_link; - target_stack_t tuc_stack; + a_target_stack tuc_stack; struct target_sigcontext tuc_mcontext; - target_sigset_t tuc_sigmask; /* mask last for extensibility */ + a_target_sigset tuc_sigmask; /* mask last for extensibility */ }; struct sigframe @@ -815,7 +815,7 @@ get_sigframe(struct target_sigaction *ka, CPUX86State *env, size_t frame_size) /* compare linux/arch/i386/kernel/signal.c:setup_frame() */ static void setup_frame(int sig, struct target_sigaction *ka, - target_sigset_t *set, CPUX86State *env) + a_target_sigset *set, CPUX86State *env) { abi_ulong frame_addr; struct sigframe *frame; @@ -884,8 +884,8 @@ give_sigsegv: /* compare linux/arch/i386/kernel/signal.c:setup_rt_frame() */ static void setup_rt_frame(int sig, struct target_sigaction *ka, - target_siginfo_t *info, - target_sigset_t *set, CPUX86State *env) + a_target_siginfo *info, + a_target_sigset *set, CPUX86State *env) { abi_ulong frame_addr, addr; struct rt_sigframe *frame; @@ -1008,7 +1008,7 @@ long do_sigreturn(CPUX86State *env) { struct sigframe *frame; abi_ulong frame_addr = env->regs[R_ESP] - 8; - target_sigset_t target_set; + a_target_sigset target_set; sigset_t set; int eax, i; @@ -1098,17 +1098,17 @@ struct target_sigcontext { struct target_ucontext_v1 { abi_ulong tuc_flags; abi_ulong tuc_link; - target_stack_t tuc_stack; + a_target_stack tuc_stack; struct target_sigcontext tuc_mcontext; - target_sigset_t tuc_sigmask; /* mask last for extensibility */ + a_target_sigset tuc_sigmask; /* mask last for extensibility */ }; struct target_ucontext_v2 { abi_ulong tuc_flags; abi_ulong tuc_link; - target_stack_t tuc_stack; + a_target_stack tuc_stack; struct target_sigcontext tuc_mcontext; - target_sigset_t tuc_sigmask; /* mask last for extensibility */ + a_target_sigset tuc_sigmask; /* mask last for extensibility */ char __unused[128 - sizeof(sigset_t)]; abi_ulong tuc_regspace[128] __attribute__((__aligned__(8))); }; @@ -1257,7 +1257,7 @@ setup_return(CPUState *env, struct target_sigaction *ka, } static void setup_sigframe_v2(struct target_ucontext_v2 *uc, - target_sigset_t *set, CPUState *env) + a_target_sigset *set, CPUState *env) { struct target_sigaltstack stack; int i; @@ -1280,7 +1280,7 @@ static void setup_sigframe_v2(struct target_ucontext_v2 *uc, /* compare linux/arch/arm/kernel/signal.c:setup_frame() */ static void setup_frame_v1(int usig, struct target_sigaction *ka, - target_sigset_t *set, CPUState *regs) + a_target_sigset *set, CPUState *regs) { struct sigframe_v1 *frame; abi_ulong frame_addr = get_sigframe(ka, regs, sizeof(*frame)); @@ -1304,7 +1304,7 @@ end: } static void setup_frame_v2(int usig, struct target_sigaction *ka, - target_sigset_t *set, CPUState *regs) + a_target_sigset *set, CPUState *regs) { struct sigframe_v2 *frame; abi_ulong frame_addr = get_sigframe(ka, regs, sizeof(*frame)); @@ -1321,7 +1321,7 @@ static void setup_frame_v2(int usig, struct target_sigaction *ka, } static void setup_frame(int usig, struct target_sigaction *ka, - target_sigset_t *set, CPUState *regs) + a_target_sigset *set, CPUState *regs) { if (get_osversion() >= 0x020612) { setup_frame_v2(usig, ka, set, regs); @@ -1332,8 +1332,8 @@ static void setup_frame(int usig, struct target_sigaction *ka, /* compare linux/arch/arm/kernel/signal.c:setup_rt_frame() */ static void setup_rt_frame_v1(int usig, struct target_sigaction *ka, - target_siginfo_t *info, - target_sigset_t *set, CPUState *env) + a_target_siginfo *info, + a_target_sigset *set, CPUState *env) { struct rt_sigframe_v1 *frame; abi_ulong frame_addr = get_sigframe(ka, env, sizeof(*frame)); @@ -1376,8 +1376,8 @@ end: } static void setup_rt_frame_v2(int usig, struct target_sigaction *ka, - target_siginfo_t *info, - target_sigset_t *set, CPUState *env) + a_target_siginfo *info, + a_target_sigset *set, CPUState *env) { struct rt_sigframe_v2 *frame; abi_ulong frame_addr = get_sigframe(ka, env, sizeof(*frame)); @@ -1402,8 +1402,8 @@ static void setup_rt_frame_v2(int usig, struct target_sigaction *ka, } static void setup_rt_frame(int usig, struct target_sigaction *ka, - target_siginfo_t *info, - target_sigset_t *set, CPUState *env) + a_target_siginfo *info, + a_target_sigset *set, CPUState *env) { if (get_osversion() >= 0x020612) { setup_rt_frame_v2(usig, ka, info, set, env); @@ -1448,7 +1448,7 @@ static long do_sigreturn_v1(CPUState *env) { abi_ulong frame_addr; struct sigframe_v1 *frame; - target_sigset_t set; + a_target_sigset set; sigset_t host_set; int i; @@ -1691,7 +1691,7 @@ typedef struct { unsigned long *insn_addr; unsigned long insn; } si_fpqueue [16]; -} qemu_siginfo_fpu_t; +} a_qemu_siginfo_fpu; struct target_signal_frame { @@ -1701,7 +1701,7 @@ struct target_signal_frame { abi_ulong insns[2] __attribute__ ((aligned (8))); abi_ulong extramask[TARGET_NSIG_WORDS - 1]; abi_ulong extra_size; /* Should be 0 */ - qemu_siginfo_fpu_t fpu_state; + a_qemu_siginfo_fpu fpu_state; }; struct target_rt_signal_frame { struct sparc_stackf ss; @@ -1712,7 +1712,7 @@ struct target_rt_signal_frame { unsigned int insns[2]; stack_t stack; unsigned int extra_size; /* Should be 0 */ - qemu_siginfo_fpu_t fpu_state; + a_qemu_siginfo_fpu fpu_state; }; #define UREG_O0 16 @@ -1785,7 +1785,7 @@ setup_sigcontext(struct target_sigcontext *sc, /*struct _fpstate *fpstate,*/ #define NF_ALIGNEDSZ (((sizeof(struct target_signal_frame) + 7) & (~7))) static void setup_frame(int sig, struct target_sigaction *ka, - target_sigset_t *set, CPUState *env) + a_target_sigset *set, CPUState *env) { abi_ulong sf_addr; struct target_signal_frame *sf; @@ -1874,7 +1874,7 @@ sigsegv: force_sig(TARGET_SIGSEGV); } static inline int -restore_fpu_state(CPUState *env, qemu_siginfo_fpu_t *fpu) +restore_fpu_state(CPUState *env, a_qemu_siginfo_fpu *fpu) { int err; #if 0 @@ -1914,8 +1914,8 @@ restore_fpu_state(CPUState *env, qemu_siginfo_fpu_t *fpu) static void setup_rt_frame(int sig, struct target_sigaction *ka, - target_siginfo_t *info, - target_sigset_t *set, CPUState *env) + a_target_siginfo *info, + a_target_sigset *set, CPUState *env) { fprintf(stderr, "setup_rt_frame: not implemented\n"); } @@ -1925,7 +1925,7 @@ long do_sigreturn(CPUState *env) abi_ulong sf_addr; struct target_signal_frame *sf; uint32_t up_psr, pc, npc; - target_sigset_t set; + a_target_sigset set; sigset_t host_set; abi_ulong fpu_save_addr; int err, i; @@ -2021,8 +2021,8 @@ long do_rt_sigreturn(CPUState *env) #define MC_O7 18 #define MC_NGREG 19 -typedef abi_ulong target_mc_greg_t; -typedef target_mc_greg_t target_mc_gregset_t[MC_NGREG]; +typedef abi_ulong a_target_mc_greg; +typedef a_target_mc_greg a_target_mc_gregset[MC_NGREG]; struct target_mc_fq { abi_ulong *mcfq_addr; @@ -2043,20 +2043,20 @@ struct target_mc_fpu { unsigned char mcfpu_qentsz; unsigned char mcfpu_enab; }; -typedef struct target_mc_fpu target_mc_fpu_t; +typedef struct target_mc_fpu a_target_mc_fpu; typedef struct { - target_mc_gregset_t mc_gregs; - target_mc_greg_t mc_fp; - target_mc_greg_t mc_i7; - target_mc_fpu_t mc_fpregs; -} target_mcontext_t; + a_target_mc_gregset mc_gregs; + a_target_mc_greg mc_fp; + a_target_mc_greg mc_i7; + a_target_mc_fpu mc_fpregs; +} a_target_mcontext; struct target_ucontext { struct target_ucontext *uc_link; abi_ulong uc_flags; - target_sigset_t uc_sigmask; - target_mcontext_t uc_mcontext; + a_target_sigset uc_sigmask; + a_target_mcontext uc_mcontext; }; /* A V9 register window */ @@ -2072,7 +2072,7 @@ void sparc64_set_context(CPUSPARCState *env) { abi_ulong ucp_addr; struct target_ucontext *ucp; - target_mc_gregset_t *grp; + a_target_mc_gregset *grp; abi_ulong pc, npc, tstate; abi_ulong fp, i7, w_addr; unsigned char fenab; @@ -2088,7 +2088,7 @@ void sparc64_set_context(CPUSPARCState *env) if (err || ((pc | npc) & 3)) goto do_sigsegv; if (env->regwptr[UREG_I1]) { - target_sigset_t target_set; + a_target_sigset target_set; sigset_t set; if (TARGET_NSIG_WORDS == 1) { @@ -2098,7 +2098,7 @@ void sparc64_set_context(CPUSPARCState *env) abi_ulong *src, *dst; src = ucp->uc_sigmask.sig; dst = target_set.sig; - for (i = 0; i < sizeof(target_sigset_t) / sizeof(abi_ulong); + for (i = 0; i < sizeof(a_target_sigset) / sizeof(abi_ulong); i++, dst++, src++) err |= __get_user(*dst, src); if (err) @@ -2167,12 +2167,12 @@ void sparc64_get_context(CPUSPARCState *env) { abi_ulong ucp_addr; struct target_ucontext *ucp; - target_mc_gregset_t *grp; - target_mcontext_t *mcp; + a_target_mc_gregset *grp; + a_target_mcontext *mcp; abi_ulong fp, i7, w_addr; int err; unsigned int i; - target_sigset_t target_set; + a_target_sigset target_set; sigset_t set; ucp_addr = env->regwptr[UREG_I0]; @@ -2197,7 +2197,7 @@ void sparc64_get_context(CPUSPARCState *env) abi_ulong *src, *dst; src = target_set.sig; dst = ucp->uc_sigmask.sig; - for (i = 0; i < sizeof(target_sigset_t) / sizeof(abi_ulong); + for (i = 0; i < sizeof(a_target_sigset) / sizeof(abi_ulong); i++, dst++, src++) err |= __put_user(*src, dst); if (err) @@ -2262,14 +2262,14 @@ void sparc64_get_context(CPUSPARCState *env) # warning signal handling not implemented static void setup_frame(int sig, struct target_sigaction *ka, - target_sigset_t *set, CPUState *env) + a_target_sigset *set, CPUState *env) { fprintf(stderr, "setup_frame: not implemented\n"); } static void setup_rt_frame(int sig, struct target_sigaction *ka, - target_siginfo_t *info, - target_sigset_t *set, CPUState *env) + a_target_siginfo *info, + a_target_sigset *set, CPUState *env) { fprintf(stderr, "setup_rt_frame: not implemented\n"); } @@ -2291,14 +2291,14 @@ long do_rt_sigreturn(CPUState *env) # warning signal handling not implemented static void setup_frame(int sig, struct target_sigaction *ka, - target_sigset_t *set, CPUState *env) + a_target_sigset *set, CPUState *env) { fprintf(stderr, "setup_frame: not implemented\n"); } static void setup_rt_frame(int sig, struct target_sigaction *ka, - target_siginfo_t *info, - target_sigset_t *set, CPUState *env) + a_target_siginfo *info, + a_target_sigset *set, CPUState *env) { fprintf(stderr, "setup_rt_frame: not implemented\n"); } @@ -2343,16 +2343,16 @@ struct sigframe { uint32_t sf_ass[4]; /* argument save space for o32 */ uint32_t sf_code[2]; /* signal trampoline */ struct target_sigcontext sf_sc; - target_sigset_t sf_mask; + a_target_sigset sf_mask; }; struct target_ucontext { target_ulong uc_flags; target_ulong uc_link; - target_stack_t uc_stack; + a_target_stack uc_stack; target_ulong pad0; struct target_sigcontext uc_mcontext; - target_sigset_t uc_sigmask; + a_target_sigset uc_sigmask; }; struct target_rt_sigframe { @@ -2551,7 +2551,7 @@ get_sigframe(struct target_sigaction *ka, CPUState *regs, size_t frame_size) /* compare linux/arch/mips/kernel/signal.c:setup_frame() */ static void setup_frame(int sig, struct target_sigaction * ka, - target_sigset_t *set, CPUState *regs) + a_target_sigset *set, CPUState *regs) { struct sigframe *frame; abi_ulong frame_addr; @@ -2604,7 +2604,7 @@ long do_sigreturn(CPUState *regs) struct sigframe *frame; abi_ulong frame_addr; sigset_t blocked; - target_sigset_t target_set; + a_target_sigset target_set; int i; #if defined(DEBUG_SIGNAL) @@ -2649,8 +2649,8 @@ badframe: } static void setup_rt_frame(int sig, struct target_sigaction *ka, - target_siginfo_t *info, - target_sigset_t *set, CPUState *env) + a_target_siginfo *info, + a_target_sigset *set, CPUState *env) { struct target_rt_sigframe *frame; abi_ulong frame_addr; @@ -2782,9 +2782,9 @@ struct target_sigframe struct target_ucontext { target_ulong uc_flags; struct target_ucontext *uc_link; - target_stack_t uc_stack; + a_target_stack uc_stack; struct target_sigcontext uc_mcontext; - target_sigset_t uc_sigmask; /* mask last for extensibility */ + a_target_sigset uc_sigmask; /* mask last for extensibility */ }; struct target_rt_sigframe @@ -2861,7 +2861,7 @@ static int restore_sigcontext(CPUState *regs, } static void setup_frame(int sig, struct target_sigaction *ka, - target_sigset_t *set, CPUState *regs) + a_target_sigset *set, CPUState *regs) { struct target_sigframe *frame; abi_ulong frame_addr; @@ -2912,8 +2912,8 @@ give_sigsegv: } static void setup_rt_frame(int sig, struct target_sigaction *ka, - target_siginfo_t *info, - target_sigset_t *set, CPUState *regs) + a_target_siginfo *info, + a_target_sigset *set, CPUState *regs) { struct target_rt_sigframe *frame; abi_ulong frame_addr; @@ -2979,7 +2979,7 @@ long do_sigreturn(CPUState *regs) struct target_sigframe *frame; abi_ulong frame_addr; sigset_t blocked; - target_sigset_t target_set; + a_target_sigset target_set; int i; int err = 0; @@ -3151,7 +3151,7 @@ static abi_ulong get_sigframe(struct target_sigaction *ka, } static void setup_frame(int sig, struct target_sigaction *ka, - target_sigset_t *set, CPUState *env) + a_target_sigset *set, CPUState *env) { struct target_signal_frame *frame; abi_ulong frame_addr; @@ -3214,8 +3214,8 @@ static void setup_frame(int sig, struct target_sigaction *ka, } static void setup_rt_frame(int sig, struct target_sigaction *ka, - target_siginfo_t *info, - target_sigset_t *set, CPUState *env) + a_target_siginfo *info, + a_target_sigset *set, CPUState *env) { fprintf(stderr, "Microblaze setup_rt_frame: not implemented\n"); } @@ -3224,7 +3224,7 @@ long do_sigreturn(CPUState *env) { struct target_signal_frame *frame; abi_ulong frame_addr; - target_sigset_t target_set; + a_target_sigset target_set; sigset_t set; int i; @@ -3339,7 +3339,7 @@ static abi_ulong get_sigframe(CPUState *env, int framesize) } static void setup_frame(int sig, struct target_sigaction *ka, - target_sigset_t *set, CPUState *env) + a_target_sigset *set, CPUState *env) { struct target_signal_frame *frame; abi_ulong frame_addr; @@ -3389,8 +3389,8 @@ static void setup_frame(int sig, struct target_sigaction *ka, } static void setup_rt_frame(int sig, struct target_sigaction *ka, - target_siginfo_t *info, - target_sigset_t *set, CPUState *env) + a_target_siginfo *info, + a_target_sigset *set, CPUState *env) { fprintf(stderr, "CRIS setup_rt_frame: not implemented\n"); } @@ -3399,7 +3399,7 @@ long do_sigreturn(CPUState *env) { struct target_signal_frame *frame; abi_ulong frame_addr; - target_sigset_t target_set; + a_target_sigset target_set; sigset_t set; int i; @@ -3537,7 +3537,7 @@ struct target_mcontext { #else #define QEMU_NVRREG 33 #endif - ppc_avr_t altivec[QEMU_NVRREG]; + union ppc_avr altivec[QEMU_NVRREG]; #undef QEMU_NVRREG } mc_vregs __attribute__((__aligned__(16))); }; @@ -3551,9 +3551,9 @@ struct target_ucontext { target_ulong uc_regs; /* struct mcontext __user * points to uc_mcontext field */ #endif - target_sigset_t uc_sigmask; + a_target_sigset uc_sigmask; #if defined(TARGET_PPC64) - target_sigset_t unused[15]; /* Allow for uc_sigmask growth */ + a_target_sigset unused[15]; /* Allow for uc_sigmask growth */ struct target_sigcontext uc_mcontext; #else int32_t uc_maskext[30]; @@ -3630,8 +3630,8 @@ static int save_user_regs(CPUState *env, struct target_mcontext *frame, /* Save Altivec registers if necessary. */ if (env->insns_flags & PPC_ALTIVEC) { for (i = 0; i < ARRAY_SIZE(env->avr); i++) { - ppc_avr_t *avr = &env->avr[i]; - ppc_avr_t *vreg = &frame->mc_vregs.altivec[i]; + union ppc_avr *avr = &env->avr[i]; + union ppc_avr *vreg = &frame->mc_vregs.altivec[i]; if (__put_user(avr->u64[0], &vreg->u64[0]) || __put_user(avr->u64[1], &vreg->u64[1])) { @@ -3739,8 +3739,8 @@ static int restore_user_regs(CPUState *env, /* Restore Altivec registers if necessary. */ if (env->insns_flags & PPC_ALTIVEC) { for (i = 0; i < ARRAY_SIZE(env->avr); i++) { - ppc_avr_t *avr = &env->avr[i]; - ppc_avr_t *vreg = &frame->mc_vregs.altivec[i]; + union ppc_avr *avr = &env->avr[i]; + union ppc_avr *vreg = &frame->mc_vregs.altivec[i]; if (__get_user(avr->u64[0], &vreg->u64[0]) || __get_user(avr->u64[1], &vreg->u64[1])) { @@ -3793,7 +3793,7 @@ static int restore_user_regs(CPUState *env, } static void setup_frame(int sig, struct target_sigaction *ka, - target_sigset_t *set, CPUState *env) + a_target_sigset *set, CPUState *env) { struct target_sigframe *frame; struct target_sigcontext *sc; @@ -3854,8 +3854,8 @@ sigsegv: } static void setup_rt_frame(int sig, struct target_sigaction *ka, - target_siginfo_t *info, - target_sigset_t *set, CPUState *env) + a_target_siginfo *info, + a_target_sigset *set, CPUState *env) { struct target_rt_sigframe *rt_sf; struct target_mcontext *frame; @@ -3929,7 +3929,7 @@ long do_sigreturn(CPUState *env) struct target_mcontext *sr = NULL; target_ulong sr_addr, sc_addr; sigset_t blocked; - target_sigset_t set; + a_target_sigset set; sc_addr = env->gpr[1] + SIGNAL_FRAMESIZE; if (!lock_user_struct(VERIFY_READ, sc, sc_addr, 1)) @@ -3971,7 +3971,7 @@ static int do_setcontext(struct target_ucontext *ucp, CPUState *env, int sig) struct target_mcontext *mcp; target_ulong mcp_addr; sigset_t blocked; - target_sigset_t set; + a_target_sigset set; if (copy_from_user(&set, h2g(ucp) + offsetof(struct target_ucontext, uc_sigmask), sizeof (set))) @@ -4052,19 +4052,19 @@ struct target_sigframe struct target_sigcontext sc; }; -typedef int target_greg_t; +typedef int a_target_greg; #define TARGET_NGREG 18 -typedef target_greg_t target_gregset_t[TARGET_NGREG]; +typedef a_target_greg a_target_gregset[TARGET_NGREG]; typedef struct target_fpregset { int f_fpcntl[3]; int f_fpregs[8*3]; -} target_fpregset_t; +} a_target_fpregset; struct target_mcontext { int version; - target_gregset_t gregs; - target_fpregset_t fpregs; + a_target_gregset gregs; + a_target_fpregset fpregs; }; #define TARGET_MCONTEXT_VERSION 2 @@ -4072,10 +4072,10 @@ struct target_mcontext { struct target_ucontext { abi_ulong uc_flags; abi_ulong uc_link; - target_stack_t uc_stack; + a_target_stack uc_stack; struct target_mcontext uc_mcontext; abi_long uc_filler[80]; - target_sigset_t uc_sigmask; + a_target_sigset uc_sigmask; }; struct target_rt_sigframe @@ -4144,7 +4144,7 @@ get_sigframe(struct target_sigaction *ka, CPUState *regs, size_t frame_size) } static void setup_frame(int sig, struct target_sigaction *ka, - target_sigset_t *set, CPUState *env) + a_target_sigset *set, CPUState *env) { struct target_sigframe *frame; abi_ulong frame_addr; @@ -4200,7 +4200,7 @@ give_sigsegv: static inline int target_rt_setup_ucontext(struct target_ucontext *uc, CPUState *env) { - target_greg_t *gregs = uc->uc_mcontext.gregs; + a_target_greg *gregs = uc->uc_mcontext.gregs; int err; err = __put_user(TARGET_MCONTEXT_VERSION, &uc->uc_mcontext.version); @@ -4232,7 +4232,7 @@ static inline int target_rt_restore_ucontext(CPUState *env, { int temp; int err; - target_greg_t *gregs = uc->uc_mcontext.gregs; + a_target_greg *gregs = uc->uc_mcontext.gregs; err = __get_user(temp, &uc->uc_mcontext.version); if (temp != TARGET_MCONTEXT_VERSION) @@ -4267,8 +4267,8 @@ badframe: } static void setup_rt_frame(int sig, struct target_sigaction *ka, - target_siginfo_t *info, - target_sigset_t *set, CPUState *env) + a_target_siginfo *info, + a_target_sigset *set, CPUState *env) { struct target_rt_sigframe *frame; abi_ulong frame_addr; @@ -4343,7 +4343,7 @@ long do_sigreturn(CPUState *env) { struct target_sigframe *frame; abi_ulong frame_addr = env->aregs[7] - 4; - target_sigset_t target_set; + a_target_sigset target_set; sigset_t set; int d0, i; @@ -4381,7 +4381,7 @@ long do_rt_sigreturn(CPUState *env) { struct target_rt_sigframe *frame; abi_ulong frame_addr = env->aregs[7] - 4; - target_sigset_t target_set; + a_target_sigset target_set; sigset_t set; int d0; @@ -4413,14 +4413,14 @@ badframe: #else static void setup_frame(int sig, struct target_sigaction *ka, - target_sigset_t *set, CPUState *env) + a_target_sigset *set, CPUState *env) { fprintf(stderr, "setup_frame: not implemented\n"); } static void setup_rt_frame(int sig, struct target_sigaction *ka, - target_siginfo_t *info, - target_sigset_t *set, CPUState *env) + a_target_siginfo *info, + a_target_sigset *set, CPUState *env) { fprintf(stderr, "setup_rt_frame: not implemented\n"); } @@ -4444,7 +4444,7 @@ void process_pending_signals(CPUState *cpu_env) int sig; abi_ulong handler; sigset_t set, old_set; - target_sigset_t target_old_set; + a_target_sigset target_old_set; struct emulated_sigtable *k; struct target_sigaction *sa; struct sigqueue *q; diff --git a/linux-user/sparc/target_signal.h b/linux-user/sparc/target_signal.h index c7de300cd7..a63ee7f6dc 100644 --- a/linux-user/sparc/target_signal.h +++ b/linux-user/sparc/target_signal.h @@ -9,7 +9,7 @@ typedef struct target_sigaltstack { abi_ulong ss_sp; abi_long ss_flags; abi_ulong ss_size; -} target_stack_t; +} a_target_stack; /* diff --git a/linux-user/sparc64/target_signal.h b/linux-user/sparc64/target_signal.h index c7de300cd7..a63ee7f6dc 100644 --- a/linux-user/sparc64/target_signal.h +++ b/linux-user/sparc64/target_signal.h @@ -9,7 +9,7 @@ typedef struct target_sigaltstack { abi_ulong ss_sp; abi_long ss_flags; abi_ulong ss_size; -} target_stack_t; +} a_target_stack; /* diff --git a/linux-user/syscall.c b/linux-user/syscall.c index bf06d14fc7..0fd6f7813d 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -4255,10 +4255,10 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, info.si_pid = 0; ret = get_errno(waitid(arg1, arg2, &info, arg4)); if (!is_error(ret) && arg3 && info.si_pid != 0) { - if (!(p = lock_user(VERIFY_WRITE, arg3, sizeof(target_siginfo_t), 0))) + if (!(p = lock_user(VERIFY_WRITE, arg3, sizeof(a_target_siginfo), 0))) goto efault; host_to_target_siginfo(p, &info); - unlock_user(p, arg3, sizeof(target_siginfo_t)); + unlock_user(p, arg3, sizeof(a_target_siginfo)); } } break; @@ -4888,7 +4888,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, ret = -TARGET_EINVAL; goto fail; } - if (!(p = lock_user(VERIFY_READ, arg2, sizeof(target_sigset_t), 1))) + if (!(p = lock_user(VERIFY_READ, arg2, sizeof(a_target_sigset), 1))) goto efault; target_to_host_old_sigset(&set, p); unlock_user(p, arg2, 0); @@ -4899,10 +4899,10 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, } ret = get_errno(sigprocmask(arg1, set_ptr, &oldset)); if (!is_error(ret) && arg3) { - if (!(p = lock_user(VERIFY_WRITE, arg3, sizeof(target_sigset_t), 0))) + if (!(p = lock_user(VERIFY_WRITE, arg3, sizeof(a_target_sigset), 0))) goto efault; host_to_target_old_sigset(p, &oldset); - unlock_user(p, arg3, sizeof(target_sigset_t)); + unlock_user(p, arg3, sizeof(a_target_sigset)); } } break; @@ -4927,7 +4927,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, ret = -TARGET_EINVAL; goto fail; } - if (!(p = lock_user(VERIFY_READ, arg2, sizeof(target_sigset_t), 1))) + if (!(p = lock_user(VERIFY_READ, arg2, sizeof(a_target_sigset), 1))) goto efault; target_to_host_sigset(&set, p); unlock_user(p, arg2, 0); @@ -4938,10 +4938,10 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, } ret = get_errno(sigprocmask(how, set_ptr, &oldset)); if (!is_error(ret) && arg3) { - if (!(p = lock_user(VERIFY_WRITE, arg3, sizeof(target_sigset_t), 0))) + if (!(p = lock_user(VERIFY_WRITE, arg3, sizeof(a_target_sigset), 0))) goto efault; host_to_target_sigset(p, &oldset); - unlock_user(p, arg3, sizeof(target_sigset_t)); + unlock_user(p, arg3, sizeof(a_target_sigset)); } } break; @@ -4951,10 +4951,10 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, sigset_t set; ret = get_errno(sigpending(&set)); if (!is_error(ret)) { - if (!(p = lock_user(VERIFY_WRITE, arg1, sizeof(target_sigset_t), 0))) + if (!(p = lock_user(VERIFY_WRITE, arg1, sizeof(a_target_sigset), 0))) goto efault; host_to_target_old_sigset(p, &set); - unlock_user(p, arg1, sizeof(target_sigset_t)); + unlock_user(p, arg1, sizeof(a_target_sigset)); } } break; @@ -4964,10 +4964,10 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, sigset_t set; ret = get_errno(sigpending(&set)); if (!is_error(ret)) { - if (!(p = lock_user(VERIFY_WRITE, arg1, sizeof(target_sigset_t), 0))) + if (!(p = lock_user(VERIFY_WRITE, arg1, sizeof(a_target_sigset), 0))) goto efault; host_to_target_sigset(p, &set); - unlock_user(p, arg1, sizeof(target_sigset_t)); + unlock_user(p, arg1, sizeof(a_target_sigset)); } } break; @@ -4975,7 +4975,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, case TARGET_NR_sigsuspend: { sigset_t set; - if (!(p = lock_user(VERIFY_READ, arg1, sizeof(target_sigset_t), 1))) + if (!(p = lock_user(VERIFY_READ, arg1, sizeof(a_target_sigset), 1))) goto efault; target_to_host_old_sigset(&set, p); unlock_user(p, arg1, 0); @@ -4986,7 +4986,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, case TARGET_NR_rt_sigsuspend: { sigset_t set; - if (!(p = lock_user(VERIFY_READ, arg1, sizeof(target_sigset_t), 1))) + if (!(p = lock_user(VERIFY_READ, arg1, sizeof(a_target_sigset), 1))) goto efault; target_to_host_sigset(&set, p); unlock_user(p, arg1, 0); @@ -4999,7 +4999,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, struct timespec uts, *puts; siginfo_t uinfo; - if (!(p = lock_user(VERIFY_READ, arg1, sizeof(target_sigset_t), 1))) + if (!(p = lock_user(VERIFY_READ, arg1, sizeof(a_target_sigset), 1))) goto efault; target_to_host_sigset(&set, p); unlock_user(p, arg1, 0); @@ -5011,17 +5011,17 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, } ret = get_errno(sigtimedwait(&set, &uinfo, puts)); if (!is_error(ret) && arg2) { - if (!(p = lock_user(VERIFY_WRITE, arg2, sizeof(target_siginfo_t), 0))) + if (!(p = lock_user(VERIFY_WRITE, arg2, sizeof(a_target_siginfo), 0))) goto efault; host_to_target_siginfo(p, &uinfo); - unlock_user(p, arg2, sizeof(target_siginfo_t)); + unlock_user(p, arg2, sizeof(a_target_siginfo)); } } break; case TARGET_NR_rt_sigqueueinfo: { siginfo_t uinfo; - if (!(p = lock_user(VERIFY_READ, arg3, sizeof(target_sigset_t), 1))) + if (!(p = lock_user(VERIFY_READ, arg3, sizeof(a_target_sigset), 1))) goto efault; target_to_host_siginfo(&uinfo, p); unlock_user(p, arg1, 0); diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h index c018165bf3..fa3950ad33 100644 --- a/linux-user/syscall_defs.h +++ b/linux-user/syscall_defs.h @@ -148,15 +148,15 @@ struct target_itimerval { struct target_timeval it_value; }; -typedef abi_long target_clock_t; +typedef abi_long a_target_clock; #define TARGET_HZ 100 struct target_tms { - target_clock_t tms_utime; - target_clock_t tms_stime; - target_clock_t tms_cutime; - target_clock_t tms_cstime; + a_target_clock tms_utime; + a_target_clock tms_stime; + a_target_clock tms_cutime; + a_target_clock tms_cstime; }; struct target_utimbuf { @@ -235,7 +235,7 @@ struct target_rusage { typedef struct { int val[2]; -} kernel_fsid_t; +} a_kernel_fsid; struct kernel_statfs { int f_type; @@ -245,7 +245,7 @@ struct kernel_statfs { int f_bavail; int f_files; int f_ffree; - kernel_fsid_t f_fsid; + a_kernel_fsid f_fsid; int f_namelen; int f_spare[6]; }; @@ -281,23 +281,23 @@ struct target_dirent64 { typedef struct { abi_ulong sig[TARGET_NSIG_WORDS]; -} target_sigset_t; +} a_target_sigset; #ifdef BSWAP_NEEDED -static inline void tswap_sigset(target_sigset_t *d, const target_sigset_t *s) +static inline void tswap_sigset(a_target_sigset *d, const a_target_sigset *s) { int i; for(i = 0;i < TARGET_NSIG_WORDS; i++) d->sig[i] = tswapl(s->sig[i]); } #else -static inline void tswap_sigset(target_sigset_t *d, const target_sigset_t *s) +static inline void tswap_sigset(a_target_sigset *d, const a_target_sigset *s) { *d = *s; } #endif -static inline void target_siginitset(target_sigset_t *d, abi_ulong set) +static inline void target_siginitset(a_target_sigset *d, abi_ulong set) { int i; d->sig[0] = set; @@ -305,8 +305,8 @@ static inline void target_siginitset(target_sigset_t *d, abi_ulong set) d->sig[i] = 0; } -void host_to_target_sigset(target_sigset_t *d, const sigset_t *s); -void target_to_host_sigset(sigset_t *d, const target_sigset_t *s); +void host_to_target_sigset(a_target_sigset *d, const sigset_t *s); +void target_to_host_sigset(sigset_t *d, const a_target_sigset *s); void host_to_target_old_sigset(abi_ulong *old_sigset, const sigset_t *sigset); void target_to_host_old_sigset(sigset_t *sigset, @@ -481,7 +481,7 @@ struct target_sigaction { #else abi_ulong _sa_handler; #endif - target_sigset_t sa_mask; + a_target_sigset sa_mask; }; #else @@ -496,14 +496,14 @@ struct target_sigaction { abi_ulong _sa_handler; abi_ulong sa_flags; abi_ulong sa_restorer; - target_sigset_t sa_mask; + a_target_sigset sa_mask; }; #endif typedef union target_sigval { int sival_int; abi_ulong sival_ptr; -} target_sigval_t; +} a_target_sigval; #if 0 #if defined (TARGET_SPARC) typedef struct { @@ -562,7 +562,7 @@ typedef struct target_siginfo { struct { pid_t _pid; /* sender's pid */ uid_t _uid; /* sender's uid */ - target_sigval_t _sigval; + a_target_sigval _sigval; } _rt; /* SIGCHLD */ @@ -570,8 +570,8 @@ typedef struct target_siginfo { pid_t _pid; /* which child */ uid_t _uid; /* sender's uid */ int _status; /* exit code */ - target_clock_t _utime; - target_clock_t _stime; + a_target_clock _utime; + a_target_clock _stime; } _sigchld; /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */ @@ -585,7 +585,7 @@ typedef struct target_siginfo { int _fd; } _sigpoll; } _sifields; -} target_siginfo_t; +} a_target_siginfo; /* * si_code values @@ -1623,7 +1623,7 @@ struct target_stat { typedef struct { int val[2]; -} target_fsid_t; +} a_target_fsid; #ifdef TARGET_MIPS #ifdef TARGET_ABI_MIPSN32 @@ -1638,7 +1638,7 @@ struct target_statfs { int32_t f_bavail; /* Linux specials */ - target_fsid_t f_fsid; + a_target_fsid f_fsid; int32_t f_namelen; int32_t f_spare[6]; }; @@ -1654,7 +1654,7 @@ struct target_statfs { abi_long f_bavail; /* Linux specials */ - target_fsid_t f_fsid; + a_target_fsid f_fsid; abi_long f_namelen; abi_long f_spare[6]; }; @@ -1670,7 +1670,7 @@ struct target_statfs64 { uint64_t f_files; uint64_t f_ffree; uint64_t f_bavail; - target_fsid_t f_fsid; + a_target_fsid f_fsid; uint32_t f_namelen; uint32_t f_spare[6]; }; @@ -1684,7 +1684,7 @@ struct target_statfs { abi_long f_bavail; abi_long f_files; abi_long f_ffree; - target_fsid_t f_fsid; + a_target_fsid f_fsid; abi_long f_namelen; abi_long f_frsize; abi_long f_spare[5]; @@ -1698,7 +1698,7 @@ struct target_statfs64 { abi_long f_bavail; abi_long f_files; abi_long f_ffree; - target_fsid_t f_fsid; + a_target_fsid f_fsid; abi_long f_namelen; abi_long f_frsize; abi_long f_spare[5]; @@ -1712,7 +1712,7 @@ struct target_statfs { uint32_t f_bavail; uint32_t f_files; uint32_t f_ffree; - target_fsid_t f_fsid; + a_target_fsid f_fsid; uint32_t f_namelen; uint32_t f_frsize; uint32_t f_spare[5]; @@ -1726,7 +1726,7 @@ struct target_statfs64 { uint64_t f_bavail; uint64_t f_files; uint64_t f_ffree; - target_fsid_t f_fsid; + a_target_fsid f_fsid; uint32_t f_namelen; uint32_t f_frsize; uint32_t f_spare[5]; diff --git a/linux-user/x86_64/target_signal.h b/linux-user/x86_64/target_signal.h index 9baf7fbeb5..da86689f1f 100644 --- a/linux-user/x86_64/target_signal.h +++ b/linux-user/x86_64/target_signal.h @@ -9,7 +9,7 @@ typedef struct target_sigaltstack { abi_ulong ss_sp; abi_long ss_flags; abi_ulong ss_size; -} target_stack_t; +} a_target_stack; /* diff --git a/linux-user/x86_64/termbits.h b/linux-user/x86_64/termbits.h index 1c3445c6a2..b958549af1 100644 --- a/linux-user/x86_64/termbits.h +++ b/linux-user/x86_64/termbits.h @@ -1,15 +1,15 @@ #define TARGET_NCCS 19 -typedef unsigned char target_cc_t; -typedef unsigned int target_speed_t; -typedef unsigned int target_tcflag_t; +typedef unsigned char a_target_cc; +typedef unsigned int a_target_speed; +typedef unsigned int a_target_tcflag; struct target_termios { - target_tcflag_t c_iflag; /* input mode flags */ - target_tcflag_t c_oflag; /* output mode flags */ - target_tcflag_t c_cflag; /* control mode flags */ - target_tcflag_t c_lflag; /* local mode flags */ - target_cc_t c_line; /* line discipline */ - target_cc_t c_cc[TARGET_NCCS]; /* control characters */ + a_target_tcflag c_iflag; /* input mode flags */ + a_target_tcflag c_oflag; /* output mode flags */ + a_target_tcflag c_cflag; /* control mode flags */ + a_target_tcflag c_lflag; /* local mode flags */ + a_target_cc c_line; /* line discipline */ + a_target_cc c_cc[TARGET_NCCS]; /* control characters */ }; /* c_cc characters */ diff --git a/m68k-semi.c b/m68k-semi.c index 48e3bd38be..ef2729f4a8 100644 --- a/m68k-semi.c +++ b/m68k-semi.c @@ -53,13 +53,13 @@ #define HOSTED_ISATTY 12 #define HOSTED_SYSTEM 13 -typedef uint32_t gdb_mode_t; -typedef uint32_t gdb_time_t; +typedef uint32_t a_gdb_mode; +typedef uint32_t a_gdb_time; struct m68k_gdb_stat { uint32_t gdb_st_dev; /* device */ uint32_t gdb_st_ino; /* inode */ - gdb_mode_t gdb_st_mode; /* protection */ + a_gdb_mode gdb_st_mode; /* protection */ uint32_t gdb_st_nlink; /* number of hard links */ uint32_t gdb_st_uid; /* user ID of owner */ uint32_t gdb_st_gid; /* group ID of owner */ @@ -67,13 +67,13 @@ struct m68k_gdb_stat { uint64_t gdb_st_size; /* total size, in bytes */ uint64_t gdb_st_blksize; /* blocksize for filesystem I/O */ uint64_t gdb_st_blocks; /* number of blocks allocated */ - gdb_time_t gdb_st_atime; /* time of last access */ - gdb_time_t gdb_st_mtime; /* time of last modification */ - gdb_time_t gdb_st_ctime; /* time of last change */ + a_gdb_time gdb_st_atime; /* time of last access */ + a_gdb_time gdb_st_mtime; /* time of last modification */ + a_gdb_time gdb_st_ctime; /* time of last change */ } __attribute__((packed)); struct gdb_timeval { - gdb_time_t tv_sec; /* second */ + a_gdb_time tv_sec; /* second */ uint64_t tv_usec; /* microsecond */ } __attribute__((packed)); @@ -67,20 +67,20 @@ * */ -typedef struct mon_cmd_t { +typedef struct mon_cmd { const char *name; const char *args_type; void *handler; const char *params; const char *help; -} mon_cmd_t; +} a_mon_cmd; /* file descriptors passed via SCM_RIGHTS */ -typedef struct mon_fd_t mon_fd_t; -struct mon_fd_t { +typedef struct mon_fd a_mon_fd; +struct mon_fd { char *name; int fd; - QLIST_ENTRY(mon_fd_t) next; + QLIST_ENTRY(mon_fd) next; }; struct Monitor { @@ -95,14 +95,14 @@ struct Monitor { CPUState *mon_cpu; BlockDriverCompletionFunc *password_completion_cb; void *password_opaque; - QLIST_HEAD(,mon_fd_t) fds; + QLIST_HEAD(,mon_fd) fds; QLIST_ENTRY(Monitor) entry; }; static QLIST_HEAD(mon_list, Monitor) mon_list; -static const mon_cmd_t mon_cmds[]; -static const mon_cmd_t info_cmds[]; +static const a_mon_cmd mon_cmds[]; +static const a_mon_cmd info_cmds[]; Monitor *cur_mon = NULL; @@ -229,10 +229,10 @@ static int compare_cmd(const char *name, const char *list) return 0; } -static void help_cmd_dump(Monitor *mon, const mon_cmd_t *cmds, +static void help_cmd_dump(Monitor *mon, const a_mon_cmd *cmds, const char *prefix, const char *name) { - const mon_cmd_t *cmd; + const a_mon_cmd *cmd; for(cmd = cmds; cmd->name != NULL; cmd++) { if (!name || !strcmp(name, cmd->name)) @@ -280,7 +280,7 @@ static void do_commit(Monitor *mon, const QDict *qdict) static void do_info(Monitor *mon, const QDict *qdict) { - const mon_cmd_t *cmd; + const a_mon_cmd *cmd; const char *item = qdict_get_try_str(qdict, "item"); void (*handler)(Monitor *); @@ -666,7 +666,7 @@ static void monitor_printc(Monitor *mon, int c) } static void memory_dump(Monitor *mon, int count, int format, int wsize, - target_phys_addr_t addr, int is_physical) + a_target_phys_addr addr, int is_physical) { CPUState *env; int nb_per_line, l, line_size, i, max_digits, len; @@ -805,7 +805,7 @@ static void do_physical_memory_dump(Monitor *mon, const QDict *qdict) int count = qdict_get_int(qdict, "count"); int format = qdict_get_int(qdict, "format"); int size = qdict_get_int(qdict, "size"); - target_phys_addr_t addr = qdict_get_int(qdict, "addr"); + a_target_phys_addr addr = qdict_get_int(qdict, "addr"); memory_dump(mon, count, format, size, addr, 1); } @@ -813,7 +813,7 @@ static void do_physical_memory_dump(Monitor *mon, const QDict *qdict) static void do_print(Monitor *mon, const QDict *qdict) { int format = qdict_get_int(qdict, "format"); - target_phys_addr_t val = qdict_get_int(qdict, "val"); + a_target_phys_addr val = qdict_get_int(qdict, "val"); #if TARGET_PHYS_ADDR_BITS == 32 switch(format) { @@ -895,7 +895,7 @@ static void do_physical_memory_save(Monitor *mon, const QDict *qdict) uint8_t buf[1024]; uint32_t size = qdict_get_int(qdict, "size"); const char *filename = qdict_get_str(qdict, "filename"); - target_phys_addr_t addr = qdict_get_int(qdict, "val"); + a_target_phys_addr addr = qdict_get_int(qdict, "val"); f = fopen(filename, "wb"); if (!f) { @@ -1565,13 +1565,13 @@ static void do_info_status(Monitor *mon) static void do_balloon(Monitor *mon, const QDict *qdict) { int value = qdict_get_int(qdict, "value"); - ram_addr_t target = value; + a_ram_addr target = value; qemu_balloon(target << 20); } static void do_info_balloon(Monitor *mon) { - ram_addr_t actual; + a_ram_addr actual; actual = qemu_balloon_status(); if (kvm_enabled() && !kvm_has_sync_mmu()) @@ -1711,7 +1711,7 @@ static void do_inject_mce(Monitor *mon, const QDict *qdict) static void do_getfd(Monitor *mon, const QDict *qdict) { const char *fdname = qdict_get_str(qdict, "fdname"); - mon_fd_t *monfd; + a_mon_fd *monfd; int fd; fd = qemu_chr_get_msgfd(mon->chr); @@ -1742,7 +1742,7 @@ static void do_getfd(Monitor *mon, const QDict *qdict) return; } - monfd = qemu_mallocz(sizeof(mon_fd_t)); + monfd = qemu_mallocz(sizeof(a_mon_fd)); monfd->name = qemu_strdup(fdname); monfd->fd = fd; @@ -1752,7 +1752,7 @@ static void do_getfd(Monitor *mon, const QDict *qdict) static void do_closefd(Monitor *mon, const QDict *qdict) { const char *fdname = qdict_get_str(qdict, "fdname"); - mon_fd_t *monfd; + a_mon_fd *monfd; QLIST_FOREACH(monfd, &mon->fds, next) { if (strcmp(monfd->name, fdname) != 0) { @@ -1783,7 +1783,7 @@ static void do_loadvm(Monitor *mon, const QDict *qdict) int monitor_get_fd(Monitor *mon, const char *fdname) { - mon_fd_t *monfd; + a_mon_fd *monfd; QLIST_FOREACH(monfd, &mon->fds, next) { int fd; @@ -1805,13 +1805,13 @@ int monitor_get_fd(Monitor *mon, const char *fdname) return -1; } -static const mon_cmd_t mon_cmds[] = { +static const a_mon_cmd mon_cmds[] = { #include "qemu-monitor.h" { NULL, NULL, }, }; /* Please update qemu-monitor.hx when adding or changing commands */ -static const mon_cmd_t info_cmds[] = { +static const a_mon_cmd info_cmds[] = { { "version", "", do_info_version, "", "show the version of QEMU" }, { "network", "", do_info_network, @@ -2585,13 +2585,13 @@ static int default_fmt_size = 4; #define MAX_ARGS 16 -static const mon_cmd_t *monitor_parse_command(Monitor *mon, +static const a_mon_cmd *monitor_parse_command(Monitor *mon, const char *cmdline, QDict *qdict) { const char *p, *typestr; int c; - const mon_cmd_t *cmd; + const a_mon_cmd *cmd; char cmdname[256]; char buf[1024]; char *key; @@ -2826,7 +2826,7 @@ fail: static void monitor_handle_command(Monitor *mon, const char *cmdline) { QDict *qdict; - const mon_cmd_t *cmd; + const a_mon_cmd *cmd; qdict = qdict_new(); @@ -2971,7 +2971,7 @@ static void monitor_find_completion(const char *cmdline) char *args[MAX_ARGS]; int nb_args, i, len; const char *ptype, *str; - const mon_cmd_t *cmd; + const a_mon_cmd *cmd; const KeyDef *key; parse_cmdline(cmdline, &nb_args, args); diff --git a/qemu-img.c b/qemu-img.c index 070fe2e229..b317305ff3 100644 --- a/qemu-img.c +++ b/qemu-img.c @@ -31,10 +31,10 @@ #include <windows.h> #endif -typedef struct img_cmd_t { +typedef struct img_cmd { const char *name; int (*handler)(int argc, char **argv); -} img_cmd_t; +} a_img_cmd; /* Default to cache=writeback as data integrity is not important for qemu-tcg. */ #define BRDV_O_FLAGS BDRV_O_CACHE_WB @@ -1035,7 +1035,7 @@ static int img_snapshot(int argc, char **argv) return 0; } -static const img_cmd_t img_cmds[] = { +static const a_img_cmd img_cmds[] = { #define DEF(option, callback, arg_string) \ { option, callback }, #include "qemu-img-cmds.h" @@ -1046,7 +1046,7 @@ static const img_cmd_t img_cmds[] = { int main(int argc, char **argv) { - const img_cmd_t *cmd; + const a_img_cmd *cmd; const char *cmdname; bdrv_init(); diff --git a/qemu-lock.h b/qemu-lock.h index 9a3e6acce8..45bd2cdd7f 100644 --- a/qemu-lock.h +++ b/qemu-lock.h @@ -28,29 +28,29 @@ #include <pthread.h> #define spin_lock pthread_mutex_lock #define spin_unlock pthread_mutex_unlock -#define spinlock_t pthread_mutex_t +#define a_spinlock pthread_mutex_t #define SPIN_LOCK_UNLOCKED PTHREAD_MUTEX_INITIALIZER #else #if defined(__hppa__) -typedef int spinlock_t[4]; +typedef int a_spinlock[4]; #define SPIN_LOCK_UNLOCKED { 1, 1, 1, 1 } -static inline void resetlock (spinlock_t *p) +static inline void resetlock (a_spinlock *p) { (*p)[0] = (*p)[1] = (*p)[2] = (*p)[3] = 1; } #else -typedef int spinlock_t; +typedef int a_spinlock; #define SPIN_LOCK_UNLOCKED 0 -static inline void resetlock (spinlock_t *p) +static inline void resetlock (a_spinlock *p) { *p = SPIN_LOCK_UNLOCKED; } @@ -171,7 +171,7 @@ static inline void *ldcw_align (void *p) { return (void *)a; } -static inline int testandset (spinlock_t *p) +static inline int testandset (a_spinlock *p) { unsigned int ret; p = ldcw_align(p); @@ -215,30 +215,30 @@ static inline int testandset (int *p) #endif #if defined(CONFIG_USER_ONLY) -static inline void spin_lock(spinlock_t *lock) +static inline void spin_lock(a_spinlock *lock) { while (testandset(lock)); } -static inline void spin_unlock(spinlock_t *lock) +static inline void spin_unlock(a_spinlock *lock) { resetlock(lock); } -static inline int spin_trylock(spinlock_t *lock) +static inline int spin_trylock(a_spinlock *lock) { return !testandset(lock); } #else -static inline void spin_lock(spinlock_t *lock) +static inline void spin_lock(a_spinlock *lock) { } -static inline void spin_unlock(spinlock_t *lock) +static inline void spin_unlock(a_spinlock *lock) { } -static inline int spin_trylock(spinlock_t *lock) +static inline int spin_trylock(a_spinlock *lock) { return 1; } @@ -235,7 +235,7 @@ static DisplaySurface* sdl_resize_displaysurface(DisplaySurface *surface, int wi #include "sdl_keysym.h" -static kbd_layout_t *kbd_layout = NULL; +static a_kbd_layout *kbd_layout = NULL; static uint8_t sdl_keyevent_to_keycode_generic(const SDL_KeyboardEvent *ev) { diff --git a/sdl_keysym.h b/sdl_keysym.h index ee904805da..c2a8ff9d52 100644 --- a/sdl_keysym.h +++ b/sdl_keysym.h @@ -1,7 +1,7 @@ #include "keymaps.h" -static const name2keysym_t name2keysym[]={ +static const a_name2keysym name2keysym[]={ /* ascii */ { "space", 0x020}, { "exclam", 0x021}, diff --git a/softmmu_template.h b/softmmu_template.h index 0e13153748..2e2afc7e0f 100644 --- a/softmmu_template.h +++ b/softmmu_template.h @@ -49,7 +49,7 @@ static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr, int mmu_idx, void *retaddr); -static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr, +static inline DATA_TYPE glue(io_read, SUFFIX)(a_target_phys_addr physaddr, target_ulong addr, void *retaddr) { @@ -85,7 +85,7 @@ DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr, DATA_TYPE res; int index; target_ulong tlb_addr; - target_phys_addr_t addend; + a_target_phys_addr addend; void *retaddr; /* test if there is match for unaligned or IO access */ @@ -141,7 +141,7 @@ static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr, { DATA_TYPE res, res1, res2; int index, shift; - target_phys_addr_t addend; + a_target_phys_addr addend; target_ulong tlb_addr, addr1, addr2; index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); @@ -191,7 +191,7 @@ static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr, int mmu_idx, void *retaddr); -static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr, +static inline void glue(io_write, SUFFIX)(a_target_phys_addr physaddr, DATA_TYPE val, target_ulong addr, void *retaddr) @@ -223,7 +223,7 @@ void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, DATA_TYPE val, int mmu_idx) { - target_phys_addr_t addend; + a_target_phys_addr addend; target_ulong tlb_addr; void *retaddr; int index; @@ -276,7 +276,7 @@ static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr, int mmu_idx, void *retaddr) { - target_phys_addr_t addend; + a_target_phys_addr addend; target_ulong tlb_addr; int index, i; diff --git a/tap-win32.c b/tap-win32.c index 2c02ce3013..475f80a7f6 100644 --- a/tap-win32.c +++ b/tap-win32.c @@ -84,7 +84,7 @@ typedef struct tun_buffer_s { unsigned char buffer [TUN_BUFFER_SIZE]; unsigned long read_size; struct tun_buffer_s* next; -} tun_buffer_t; +} a_tun_buffer; typedef struct tap_win32_overlapped { HANDLE handle; @@ -97,17 +97,17 @@ typedef struct tap_win32_overlapped { CRITICAL_SECTION free_list_cs; OVERLAPPED read_overlapped; OVERLAPPED write_overlapped; - tun_buffer_t buffers[TUN_MAX_BUFFER_COUNT]; - tun_buffer_t* free_list; - tun_buffer_t* output_queue_front; - tun_buffer_t* output_queue_back; -} tap_win32_overlapped_t; + a_tun_buffer buffers[TUN_MAX_BUFFER_COUNT]; + a_tun_buffer* free_list; + a_tun_buffer* output_queue_front; + a_tun_buffer* output_queue_back; +} a_tap_win32_overlapped; -static tap_win32_overlapped_t tap_overlapped; +static a_tap_win32_overlapped tap_overlapped; -static tun_buffer_t* get_buffer_from_free_list(tap_win32_overlapped_t* const overlapped) +static a_tun_buffer* get_buffer_from_free_list(a_tap_win32_overlapped* const overlapped) { - tun_buffer_t* buffer = NULL; + a_tun_buffer* buffer = NULL; WaitForSingleObject(overlapped->free_list_semaphore, INFINITE); EnterCriticalSection(&overlapped->free_list_cs); buffer = overlapped->free_list; @@ -118,7 +118,7 @@ static tun_buffer_t* get_buffer_from_free_list(tap_win32_overlapped_t* const ove return buffer; } -static void put_buffer_on_free_list(tap_win32_overlapped_t* const overlapped, tun_buffer_t* const buffer) +static void put_buffer_on_free_list(a_tap_win32_overlapped* const overlapped, a_tun_buffer* const buffer) { EnterCriticalSection(&overlapped->free_list_cs); buffer->next = overlapped->free_list; @@ -127,9 +127,9 @@ static void put_buffer_on_free_list(tap_win32_overlapped_t* const overlapped, tu ReleaseSemaphore(overlapped->free_list_semaphore, 1, NULL); } -static tun_buffer_t* get_buffer_from_output_queue(tap_win32_overlapped_t* const overlapped, const int block) +static a_tun_buffer* get_buffer_from_output_queue(a_tap_win32_overlapped* const overlapped, const int block) { - tun_buffer_t* buffer = NULL; + a_tun_buffer* buffer = NULL; DWORD result, timeout = block ? INFINITE : 0L; // Non-blocking call @@ -160,12 +160,12 @@ static tun_buffer_t* get_buffer_from_output_queue(tap_win32_overlapped_t* const return buffer; } -static tun_buffer_t* get_buffer_from_output_queue_immediate (tap_win32_overlapped_t* const overlapped) +static a_tun_buffer* get_buffer_from_output_queue_immediate (a_tap_win32_overlapped* const overlapped) { return get_buffer_from_output_queue(overlapped, 0); } -static void put_buffer_on_output_queue(tap_win32_overlapped_t* const overlapped, tun_buffer_t* const buffer) +static void put_buffer_on_output_queue(a_tap_win32_overlapped* const overlapped, a_tun_buffer* const buffer) { EnterCriticalSection(&overlapped->output_queue_cs); @@ -393,7 +393,7 @@ static int tap_win32_set_status(HANDLE handle, int status) &status, sizeof (status), &len, NULL); } -static void tap_win32_overlapped_init(tap_win32_overlapped_t* const overlapped, const HANDLE handle) +static void tap_win32_overlapped_init(a_tap_win32_overlapped* const overlapped, const HANDLE handle) { overlapped->handle = handle; @@ -436,7 +436,7 @@ static void tap_win32_overlapped_init(tap_win32_overlapped_t* const overlapped, { unsigned index; for(index = 0; index < TUN_MAX_BUFFER_COUNT; index++) { - tun_buffer_t* element = &overlapped->buffers[index]; + a_tun_buffer* element = &overlapped->buffers[index]; element->next = overlapped->free_list; overlapped->free_list = element; } @@ -447,7 +447,7 @@ static void tap_win32_overlapped_init(tap_win32_overlapped_t* const overlapped, fprintf(stderr, "error creating tap_semaphore.\n"); } -static int tap_win32_write(tap_win32_overlapped_t *overlapped, +static int tap_win32_write(a_tap_win32_overlapped *overlapped, const void *buffer, unsigned long size) { unsigned long write_size; @@ -481,11 +481,11 @@ static int tap_win32_write(tap_win32_overlapped_t *overlapped, static DWORD WINAPI tap_win32_thread_entry(LPVOID param) { - tap_win32_overlapped_t *overlapped = (tap_win32_overlapped_t*)param; + a_tap_win32_overlapped *overlapped = (a_tap_win32_overlapped*)param; unsigned long read_size; BOOL result; DWORD dwError; - tun_buffer_t* buffer = get_buffer_from_free_list(overlapped); + a_tun_buffer* buffer = get_buffer_from_free_list(overlapped); for (;;) { @@ -534,12 +534,12 @@ static DWORD WINAPI tap_win32_thread_entry(LPVOID param) return 0; } -static int tap_win32_read(tap_win32_overlapped_t *overlapped, +static int tap_win32_read(a_tap_win32_overlapped *overlapped, uint8_t **pbuf, int max_size) { int size = 0; - tun_buffer_t* buffer = get_buffer_from_output_queue_immediate(overlapped); + a_tun_buffer* buffer = get_buffer_from_output_queue_immediate(overlapped); if(buffer != NULL) { *pbuf = buffer->buffer; @@ -552,14 +552,14 @@ static int tap_win32_read(tap_win32_overlapped_t *overlapped, return size; } -static void tap_win32_free_buffer(tap_win32_overlapped_t *overlapped, +static void tap_win32_free_buffer(a_tap_win32_overlapped *overlapped, uint8_t *pbuf) { - tun_buffer_t* buffer = (tun_buffer_t*)pbuf; + a_tun_buffer* buffer = (a_tun_buffer*)pbuf; put_buffer_on_free_list(overlapped, buffer); } -static int tap_win32_open(tap_win32_overlapped_t **phandle, +static int tap_win32_open(a_tap_win32_overlapped **phandle, const char *prefered_name) { char device_path[256]; @@ -628,7 +628,7 @@ static int tap_win32_open(tap_win32_overlapped_t **phandle, typedef struct TAPState { VLANClientState *vc; - tap_win32_overlapped_t *handle; + a_tap_win32_overlapped *handle; } TAPState; static void tap_cleanup(VLANClientState *vc) diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index ca9dfe2458..4cc1f5eba8 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -260,8 +260,8 @@ enum { typedef struct CPUAlphaState CPUAlphaState; -typedef struct pal_handler_t pal_handler_t; -struct pal_handler_t { +typedef struct pal_handler a_pal_handler; +struct pal_handler { /* Reset */ void (*reset)(CPUAlphaState *env); /* Uncorrectable hardware error */ @@ -323,7 +323,7 @@ struct CPUAlphaState { uint32_t features; uint32_t amask; int implver; - pal_handler_t *pal_handler; + a_pal_handler *pal_handler; }; #define cpu_init cpu_alpha_init diff --git a/target-alpha/helper.c b/target-alpha/helper.c index fcd5841e01..d982c18a9a 100644 --- a/target-alpha/helper.c +++ b/target-alpha/helper.c @@ -38,7 +38,7 @@ int cpu_alpha_handle_mmu_fault (CPUState *env, target_ulong address, int rw, return 1; } -target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr) +a_target_phys_addr cpu_get_phys_page_debug (CPUState *env, target_ulong addr) { return addr; } @@ -50,7 +50,7 @@ void do_interrupt (CPUState *env) #else -target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr) +a_target_phys_addr cpu_get_phys_page_debug (CPUState *env, target_ulong addr) { return -1; } diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c index fe222dccd9..7a6e8fb920 100644 --- a/target-alpha/op_helper.c +++ b/target-alpha/op_helper.c @@ -89,7 +89,7 @@ void helper_store_fpcr (uint64_t val) } } -static spinlock_t intr_cpu_lock = SPIN_LOCK_UNLOCKED; +static a_spinlock intr_cpu_lock = SPIN_LOCK_UNLOCKED; uint64_t helper_rs(void) { diff --git a/target-arm/helper.c b/target-arm/helper.c index 701629af3a..7a61c1c0e5 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -520,7 +520,7 @@ void HELPER(clrex)(CPUState *env) flush_mmon(env->mmon_entry->addr); } -target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) +a_target_phys_addr cpu_get_phys_page_debug(CPUState *env, target_ulong addr) { return addr; } @@ -1230,7 +1230,7 @@ int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, return 1; } -target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) +a_target_phys_addr cpu_get_phys_page_debug(CPUState *env, target_ulong addr) { uint32_t phys_addr; int prot; diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index d4ae4ae7e3..24382a0608 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -30,7 +30,7 @@ void raise_exception(int tt) /* thread support */ -static spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED; +static a_spinlock global_cpu_lock = SPIN_LOCK_UNLOCKED; void cpu_lock(void) { diff --git a/target-cris/helper.c b/target-cris/helper.c index c0e11d1aa7..45825ffd67 100644 --- a/target-cris/helper.c +++ b/target-cris/helper.c @@ -56,7 +56,7 @@ int cpu_cris_handle_mmu_fault(CPUState * env, target_ulong address, int rw, return 1; } -target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) +a_target_phys_addr cpu_get_phys_page_debug(CPUState * env, target_ulong addr) { return addr; } @@ -187,7 +187,7 @@ void do_interrupt(CPUState *env) env->pregs[PR_ERP]); } -target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) +a_target_phys_addr cpu_get_phys_page_debug(CPUState * env, target_ulong addr) { uint32_t phy = addr; struct cris_mmu_result res; diff --git a/target-i386/helper.c b/target-i386/helper.c index 8111f25662..e70e63ecc6 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -91,7 +91,7 @@ static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features, } } -typedef struct x86_def_t { +typedef struct x86_def { const char *name; uint32_t level; uint32_t vendor1, vendor2, vendor3; @@ -102,7 +102,7 @@ typedef struct x86_def_t { uint32_t xlevel; char model_id[48]; int vendor_override; -} x86_def_t; +} a_x86_def; #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ @@ -115,7 +115,7 @@ typedef struct x86_def_t { CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ CPUID_PAE | CPUID_SEP | CPUID_APIC) -static x86_def_t x86_defs[] = { +static a_x86_def x86_defs[] = { #ifdef TARGET_X86_64 { .name = "qemu64", @@ -336,7 +336,7 @@ static int cpu_x86_fill_model_id(char *str) return 0; } -static int cpu_x86_fill_host(x86_def_t *x86_cpu_def) +static int cpu_x86_fill_host(a_x86_def *x86_cpu_def) { uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0; @@ -366,10 +366,10 @@ static int cpu_x86_fill_host(x86_def_t *x86_cpu_def) return 0; } -static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *cpu_model) +static int cpu_x86_find_by_name(a_x86_def *x86_cpu_def, const char *cpu_model) { unsigned int i; - x86_def_t *def; + a_x86_def *def; char *s = strdup(cpu_model); char *featurestr, *name = strtok(s, ","); @@ -501,7 +501,7 @@ void x86_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) static int cpu_x86_register (CPUX86State *env, const char *cpu_model) { - x86_def_t def1, *def = &def1; + a_x86_def def1, *def = &def1; if (cpu_x86_find_by_name(def, cpu_model) < 0) return -1; @@ -1030,7 +1030,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr, return 1; } -target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) +a_target_phys_addr cpu_get_phys_page_debug(CPUState *env, target_ulong addr) { return addr; } @@ -1057,7 +1057,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr, uint64_t ptep, pte; target_ulong pde_addr, pte_addr; int error_code, is_dirty, prot, page_size, ret, is_write, is_user; - target_phys_addr_t paddr; + a_target_phys_addr paddr; uint32_t page_offset; target_ulong vaddr, virt_addr; @@ -1341,11 +1341,11 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr, return 1; } -target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) +a_target_phys_addr cpu_get_phys_page_debug(CPUState *env, target_ulong addr) { target_ulong pde_addr, pte_addr; uint64_t pte; - target_phys_addr_t paddr; + a_target_phys_addr paddr; uint32_t page_offset; int page_size; diff --git a/target-i386/op_helper.c b/target-i386/op_helper.c index 33d44b0037..c796df0e9d 100644 --- a/target-i386/op_helper.c +++ b/target-i386/op_helper.c @@ -106,7 +106,7 @@ static const CPU86_LDouble f15rk[7] = /* broken thread support */ -static spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED; +static a_spinlock global_cpu_lock = SPIN_LOCK_UNLOCKED; void helper_lock(void) { @@ -4855,7 +4855,7 @@ void helper_svm_check_io(uint32_t port, uint32_t param, } #else -static inline void svm_save_seg(target_phys_addr_t addr, +static inline void svm_save_seg(a_target_phys_addr addr, const SegmentCache *sc) { stw_phys(addr + offsetof(struct vmcb_seg, selector), @@ -4868,7 +4868,7 @@ static inline void svm_save_seg(target_phys_addr_t addr, ((sc->flags >> 8) & 0xff) | ((sc->flags >> 12) & 0x0f00)); } -static inline void svm_load_seg(target_phys_addr_t addr, SegmentCache *sc) +static inline void svm_load_seg(a_target_phys_addr addr, SegmentCache *sc) { unsigned int flags; @@ -4879,7 +4879,7 @@ static inline void svm_load_seg(target_phys_addr_t addr, SegmentCache *sc) sc->flags = ((flags & 0xff) << 8) | ((flags & 0x0f00) << 12); } -static inline void svm_load_seg_cache(target_phys_addr_t addr, +static inline void svm_load_seg_cache(a_target_phys_addr addr, CPUState *env, int seg_reg) { SegmentCache sc1, *sc = &sc1; diff --git a/target-m68k/helper.c b/target-m68k/helper.c index 9f30a7479d..2a9f7e6906 100644 --- a/target-m68k/helper.c +++ b/target-m68k/helper.c @@ -38,14 +38,14 @@ enum m68k_cpuid { M68K_CPUID_ANY, }; -typedef struct m68k_def_t m68k_def_t; +typedef struct m68k_def a_m68k_def; -struct m68k_def_t { +struct m68k_def { const char * name; enum m68k_cpuid id; }; -static m68k_def_t m68k_cpu_defs[] = { +static a_m68k_def m68k_cpu_defs[] = { {"m5206", M68K_CPUID_M5206}, {"m5208", M68K_CPUID_M5208}, {"cfv4e", M68K_CPUID_CFV4E}, @@ -96,7 +96,7 @@ static void m68k_set_feature(CPUM68KState *env, int feature) static int cpu_m68k_set_model(CPUM68KState *env, const char *name) { - m68k_def_t *def; + a_m68k_def *def; for (def = m68k_cpu_defs; def->name; def++) { if (strcmp(def->name, name) == 0) @@ -345,7 +345,7 @@ void m68k_switch_sp(CPUM68KState *env) /* MMU */ /* TODO: This will need fixing once the MMU is implemented. */ -target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) +a_target_phys_addr cpu_get_phys_page_debug(CPUState *env, target_ulong addr) { return addr; } diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h index 1bf4875ecf..facae2fa18 100644 --- a/target-microblaze/cpu.h +++ b/target-microblaze/cpu.h @@ -324,6 +324,6 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, *flags = env->iflags & IFLAGS_TB_MASK; } -void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, +void do_unassigned_access(a_target_phys_addr addr, int is_write, int is_exec, int is_asi, int size); #endif diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c index 40d27b956e..0de1b066dd 100644 --- a/target-microblaze/helper.c +++ b/target-microblaze/helper.c @@ -45,7 +45,7 @@ int cpu_mb_handle_mmu_fault(CPUState * env, target_ulong address, int rw, return 1; } -target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) +a_target_phys_addr cpu_get_phys_page_debug(CPUState * env, target_ulong addr) { return addr; } @@ -265,7 +265,7 @@ void do_interrupt(CPUState *env) } } -target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) +a_target_phys_addr cpu_get_phys_page_debug(CPUState * env, target_ulong addr) { target_ulong vaddr, paddr = 0; struct microblaze_mmu_lookup lu; diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c index ee4f623131..63c5225c96 100644 --- a/target-microblaze/op_helper.c +++ b/target-microblaze/op_helper.c @@ -238,7 +238,7 @@ void helper_mmu_write(uint32_t rn, uint32_t v) } #endif -void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, +void do_unassigned_access(a_target_phys_addr addr, int is_write, int is_exec, int is_asi, int size) { CPUState *saved_env; diff --git a/target-mips/cpu.h b/target-mips/cpu.h index c27738ac47..e7d30d156e 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -21,8 +21,8 @@ typedef unsigned int uint_fast16_t; struct CPUMIPSState; -typedef struct r4k_tlb_t r4k_tlb_t; -struct r4k_tlb_t { +typedef struct r4k_tlb a_r4k_tlb; +struct r4k_tlb { target_ulong VPN; uint32_t PageMask; uint_fast8_t ASID; @@ -47,13 +47,12 @@ struct CPUMIPSTLBContext { void (*helper_tlbr) (void); union { struct { - r4k_tlb_t tlb[MIPS_TLB_MAX]; + a_r4k_tlb tlb[MIPS_TLB_MAX]; } r4k; } mmu; }; -typedef union fpr_t fpr_t; -union fpr_t { +union fpr { float64 fd; /* ieee double precision */ float32 fs[2];/* ieee single precision */ uint64_t d; /* binary double fixed-point */ @@ -71,7 +70,7 @@ union fpr_t { typedef struct CPUMIPSFPUContext CPUMIPSFPUContext; struct CPUMIPSFPUContext { /* Floating point registers */ - fpr_t fpr[32]; + union fpr fpr[32]; float_status fp_status; /* fpu implementation/revision register (fir) */ uint32_t fcr0; @@ -130,7 +129,7 @@ struct CPUMIPSMVPContext { #define CP0MVPC1_PCP1 0 }; -typedef struct mips_def_t mips_def_t; +typedef struct mips_def a_mips_def; #define MIPS_SHADOW_SET_MAX 16 #define MIPS_TC_MAX 5 @@ -458,7 +457,7 @@ struct CPUMIPSState { CPU_COMMON - const mips_def_t *cpu_model; + const a_mips_def *cpu_model; void *irq[8]; struct QEMUTimer *timer; /* Internal timer */ }; @@ -475,7 +474,7 @@ void r4k_helper_tlbp (void); void r4k_helper_tlbr (void); void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); -void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, +void do_unassigned_access(a_target_phys_addr addr, int is_write, int is_exec, int unused, int size); #define cpu_init cpu_mips_init diff --git a/target-mips/helper.c b/target-mips/helper.c index 7f659ae6bc..abca444837 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -69,7 +69,7 @@ int r4k_map_address (CPUState *env, target_ulong *physical, int *prot, int i; for (i = 0; i < env->tlb->tlb_in_use; i++) { - r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i]; + a_r4k_tlb *tlb = &env->tlb->mmu.r4k.tlb[i]; /* 1k pages are not supported. */ target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); target_ulong tag = address & ~mask; @@ -201,7 +201,7 @@ static int get_physical_address (CPUState *env, target_ulong *physical, } #endif -target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) +a_target_phys_addr cpu_get_phys_page_debug(CPUState *env, target_ulong addr) { #if defined(CONFIG_USER_ONLY) return addr; @@ -564,7 +564,7 @@ void do_interrupt (CPUState *env) void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra) { - r4k_tlb_t *tlb; + a_r4k_tlb *tlb; target_ulong addr; target_ulong end; uint8_t ASID = env->CP0_EntryHi & 0xFF; diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index d3dab33a36..17e6ed5a8d 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -1508,7 +1508,7 @@ static void r4k_mips_tlb_flush_extra (CPUState *env, int first) static void r4k_fill_tlb (int idx) { - r4k_tlb_t *tlb; + a_r4k_tlb *tlb; /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */ tlb = &env->tlb->mmu.r4k.tlb[idx]; @@ -1554,7 +1554,7 @@ void r4k_helper_tlbwr (void) void r4k_helper_tlbp (void) { - r4k_tlb_t *tlb; + a_r4k_tlb *tlb; target_ulong mask; target_ulong tag; target_ulong VPN; @@ -1596,7 +1596,7 @@ void r4k_helper_tlbp (void) void r4k_helper_tlbr (void) { - r4k_tlb_t *tlb; + a_r4k_tlb *tlb; uint8_t ASID; int idx; @@ -1846,7 +1846,7 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr) env = saved_env; } -void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, +void do_unassigned_access(a_target_phys_addr addr, int is_write, int is_exec, int unused, int size) { if (is_exec) diff --git a/target-mips/translate.c b/target-mips/translate.c index 58f483fa0a..d05fee9f1f 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -8451,7 +8451,7 @@ static void fpu_dump_state(CPUState *env, FILE *f, (fp)->w[FP_ENDIAN_IDX], (fp)->d, (fp)->fd, \ (fp)->fs[FP_ENDIAN_IDX], (fp)->fs[!FP_ENDIAN_IDX]); \ else { \ - fpr_t tmp; \ + union fpr tmp; \ tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \ tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \ fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu:%13g\n", \ @@ -8591,7 +8591,7 @@ static void mips_tcg_init(void) CPUMIPSState *cpu_mips_init (const char *cpu_model) { CPUMIPSState *env; - const mips_def_t *def; + const a_mips_def *def; def = cpu_mips_find_by_name(cpu_model); if (!def) diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index eb35dbad38..7c8519a9c2 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -61,7 +61,7 @@ enum mips_mmu_types { MMU_TYPE_R8000 }; -struct mips_def_t { +struct mips_def { const char *name; int32_t CP0_PRid; int32_t CP0_Config0; @@ -94,7 +94,7 @@ struct mips_def_t { /*****************************************************************************/ /* MIPS CPU definitions */ -static const mips_def_t mips_defs[] = +static const a_mips_def mips_defs[] = { { .name = "4Kc", @@ -416,7 +416,7 @@ static const mips_def_t mips_defs[] = #endif }; -static const mips_def_t *cpu_mips_find_by_name (const char *name) +static const a_mips_def *cpu_mips_find_by_name (const char *name) { int i; @@ -439,19 +439,19 @@ void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) } #ifndef CONFIG_USER_ONLY -static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def) +static void no_mmu_init (CPUMIPSState *env, const a_mips_def *def) { env->tlb->nb_tlb = 1; env->tlb->map_address = &no_mmu_map_address; } -static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def) +static void fixed_mmu_init (CPUMIPSState *env, const a_mips_def *def) { env->tlb->nb_tlb = 1; env->tlb->map_address = &fixed_mmu_map_address; } -static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def) +static void r4k_mmu_init (CPUMIPSState *env, const a_mips_def *def) { env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); env->tlb->map_address = &r4k_map_address; @@ -461,7 +461,7 @@ static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def) env->tlb->helper_tlbr = r4k_helper_tlbr; } -static void mmu_init (CPUMIPSState *env, const mips_def_t *def) +static void mmu_init (CPUMIPSState *env, const a_mips_def *def) { env->tlb = qemu_mallocz(sizeof(CPUMIPSTLBContext)); @@ -486,7 +486,7 @@ static void mmu_init (CPUMIPSState *env, const mips_def_t *def) } #endif /* CONFIG_USER_ONLY */ -static void fpu_init (CPUMIPSState *env, const mips_def_t *def) +static void fpu_init (CPUMIPSState *env, const a_mips_def *def) { int i; @@ -504,7 +504,7 @@ static void fpu_init (CPUMIPSState *env, const mips_def_t *def) #endif } -static void mvp_init (CPUMIPSState *env, const mips_def_t *def) +static void mvp_init (CPUMIPSState *env, const a_mips_def *def) { env->mvp = qemu_mallocz(sizeof(CPUMIPSMVPContext)); @@ -531,7 +531,7 @@ static void mvp_init (CPUMIPSState *env, const mips_def_t *def) (0x1 << CP0MVPC1_PCP1); } -static int cpu_mips_register (CPUMIPSState *env, const mips_def_t *def) +static int cpu_mips_register (CPUMIPSState *env, const a_mips_def *def) { env->CP0_PRid = def->CP0_PRid; env->CP0_Config0 = def->CP0_Config0; diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 27f523f6f3..cd120d03c6 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -70,8 +70,8 @@ /*****************************************************************************/ /* MMU model */ -typedef enum powerpc_mmu_t powerpc_mmu_t; -enum powerpc_mmu_t { +typedef enum powerpc_mmu e_powerpc_mmu; +enum powerpc_mmu { POWERPC_MMU_UNKNOWN = 0x00000000, /* Standard 32 bits PowerPC MMU */ POWERPC_MMU_32B = 0x00000001, @@ -104,8 +104,8 @@ enum powerpc_mmu_t { /*****************************************************************************/ /* Exception model */ -typedef enum powerpc_excp_t powerpc_excp_t; -enum powerpc_excp_t { +typedef enum powerpc_excp e_powerpc_excp; +enum powerpc_excp { POWERPC_EXCP_UNKNOWN = 0, /* Standard PowerPC exception model */ POWERPC_EXCP_STD, @@ -258,8 +258,8 @@ enum { /*****************************************************************************/ /* Input pins model */ -typedef enum powerpc_input_t powerpc_input_t; -enum powerpc_input_t { +typedef enum powerpc_input e_powerpc_input; +enum powerpc_input { PPC_FLAGS_INPUT_UNKNOWN = 0, /* PowerPC 6xx bus */ PPC_FLAGS_INPUT_6xx, @@ -278,20 +278,18 @@ enum powerpc_input_t { #define PPC_INPUT(env) (env->bus_model) /*****************************************************************************/ -typedef struct ppc_def_t ppc_def_t; -typedef struct opc_handler_t opc_handler_t; +typedef struct ppc_def a_ppc_def; +typedef struct opc_handler an_opc_handler; /*****************************************************************************/ /* Types used to describe some PowerPC registers */ typedef struct CPUPPCState CPUPPCState; -typedef struct ppc_tb_t ppc_tb_t; -typedef struct ppc_spr_t ppc_spr_t; -typedef struct ppc_dcr_t ppc_dcr_t; -typedef union ppc_avr_t ppc_avr_t; -typedef union ppc_tlb_t ppc_tlb_t; +typedef struct ppc_tb a_ppc_tb; +typedef struct ppc_spr a_ppc_spr; +typedef struct ppc_dcr a_ppc_dcr; /* SPR access micro-ops generations callbacks */ -struct ppc_spr_t { +struct ppc_spr { void (*uea_read)(void *opaque, int gpr_num, int spr_num); void (*uea_write)(void *opaque, int spr_num, int gpr_num); #if !defined(CONFIG_USER_ONLY) @@ -304,7 +302,7 @@ struct ppc_spr_t { }; /* Altivec registers (128 bits) */ -union ppc_avr_t { +union ppc_avr { float32 f[4]; uint8_t u8[16]; uint16_t u16[8]; @@ -316,16 +314,16 @@ union ppc_avr_t { }; /* Software TLB cache */ -typedef struct ppc6xx_tlb_t ppc6xx_tlb_t; -struct ppc6xx_tlb_t { +typedef struct ppc6xx_tlb a_ppc6xx_tlb; +struct ppc6xx_tlb { target_ulong pte0; target_ulong pte1; target_ulong EPN; }; -typedef struct ppcemb_tlb_t ppcemb_tlb_t; -struct ppcemb_tlb_t { - target_phys_addr_t RPN; +typedef struct ppcemb_tlb a_ppcemb_tlb; +struct ppcemb_tlb { + a_target_phys_addr RPN; target_ulong EPN; target_ulong PID; target_ulong size; @@ -333,13 +331,13 @@ struct ppcemb_tlb_t { uint32_t attr; /* Storage attributes */ }; -union ppc_tlb_t { - ppc6xx_tlb_t tlb6; - ppcemb_tlb_t tlbe; +union ppc_tlb { + a_ppc6xx_tlb tlb6; + a_ppcemb_tlb tlbe; }; -typedef struct ppc_slb_t ppc_slb_t; -struct ppc_slb_t { +typedef struct ppc_slb a_ppc_slb; +struct ppc_slb { uint64_t tmp64; uint32_t tmp; }; @@ -590,7 +588,7 @@ struct CPUPPCState { /* Address space register */ target_ulong asr; /* PowerPC 64 SLB area */ - ppc_slb_t slb[64]; + a_ppc_slb slb[64]; int slb_nr; #endif /* segment registers */ @@ -607,7 +605,7 @@ struct CPUPPCState { int last_way; /* Last used way used to allocate TLB in a LRU way */ int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */ int nb_pids; /* Number of available PID registers */ - ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */ + union ppc_tlb *tlb; /* TLB is optional. Allocate them only if needed */ /* 403 dedicated access protection registers */ target_ulong pb[4]; #endif @@ -615,9 +613,9 @@ struct CPUPPCState { /* Other registers */ /* Special purpose registers */ target_ulong spr[1024]; - ppc_spr_t spr_cb[1024]; + a_ppc_spr spr_cb[1024]; /* Altivec registers */ - ppc_avr_t avr[32]; + union ppc_avr avr[32]; uint32_t vscr; /* SPE registers */ uint64_t spe_acc; @@ -628,9 +626,9 @@ struct CPUPPCState { /* Internal devices resources */ /* Time base and decrementer */ - ppc_tb_t *tb_env; + a_ppc_tb *tb_env; /* Device control registers */ - ppc_dcr_t *dcr_env; + a_ppc_dcr *dcr_env; int dcache_line_size; int icache_line_size; @@ -638,9 +636,9 @@ struct CPUPPCState { /* Those resources are used during exception processing */ /* CPU model definition */ target_ulong msr_mask; - powerpc_mmu_t mmu_model; - powerpc_excp_t excp_model; - powerpc_input_t bus_model; + e_powerpc_mmu mmu_model; + e_powerpc_excp excp_model; + e_powerpc_input bus_model; int bfd_mach; uint32_t flags; uint64_t insns_flags; @@ -667,7 +665,7 @@ struct CPUPPCState { target_ulong nip; /* opcode handlers */ - opc_handler_t *opcodes[0x40]; + an_opc_handler *opcodes[0x40]; /* Those resources are used only in Qemu core */ target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */ @@ -683,12 +681,12 @@ struct CPUPPCState { }; /* Context used internally during MMU translations */ -typedef struct mmu_ctx_t mmu_ctx_t; -struct mmu_ctx_t { - target_phys_addr_t raddr; /* Real address */ - target_phys_addr_t eaddr; /* Effective address */ +typedef struct mmu_ctx a_mmu_ctx; +struct mmu_ctx { + a_target_phys_addr raddr; /* Real address */ + a_target_phys_addr eaddr; /* Effective address */ int prot; /* Protection bits */ - target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */ + a_target_phys_addr pg_addr[2]; /* PTE tables base addresses */ target_ulong ptem; /* Virtual segment ID | API */ int key; /* Access key */ int nx; /* Non-execute area */ @@ -707,7 +705,7 @@ int cpu_ppc_signal_handler (int host_signum, void *pinfo, int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw, int mmu_idx, int is_softmmu); #define cpu_handle_mmu_fault cpu_ppc_handle_mmu_fault -int get_physical_address (CPUPPCState *env, mmu_ctx_t *ctx, target_ulong vaddr, +int get_physical_address (CPUPPCState *env, a_mmu_ctx *ctx, target_ulong vaddr, int rw, int access_type); void do_interrupt (CPUPPCState *env); void ppc_hw_interrupt (CPUPPCState *env); @@ -738,8 +736,8 @@ void cpu_ppc_reset (void *opaque); void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); -const ppc_def_t *cpu_ppc_find_by_name (const char *name); -int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def); +const a_ppc_def *cpu_ppc_find_by_name (const char *name); +int cpu_ppc_register_internal (CPUPPCState *env, const a_ppc_def *def); /* Time-base and decrementer management */ #ifndef NO_CPU_IO_DEFS @@ -797,8 +795,8 @@ static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn) } /* Device control registers */ -int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp); -int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val); +int ppc_dcr_read (a_ppc_dcr *dcr_env, int dcrn, target_ulong *valp); +int ppc_dcr_write (a_ppc_dcr *dcr_env, int dcrn, target_ulong val); #define cpu_init cpu_ppc_init #define cpu_exec cpu_ppc_exec diff --git a/target-ppc/helper.c b/target-ppc/helper.c index 5c85c6120a..afe538fea2 100644 --- a/target-ppc/helper.c +++ b/target-ppc/helper.c @@ -97,7 +97,7 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, return 1; } -target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr) +a_target_phys_addr cpu_get_phys_page_debug (CPUState *env, target_ulong addr) { return addr; } @@ -197,7 +197,7 @@ static inline int check_prot(int prot, int rw, int access_type) return ret; } -static inline int _pte_check(mmu_ctx_t *ctx, int is_64b, target_ulong pte0, +static inline int _pte_check(a_mmu_ctx *ctx, int is_64b, target_ulong pte0, target_ulong pte1, int h, int rw, int type) { target_ulong ptem, mmask; @@ -233,7 +233,7 @@ static inline int _pte_check(mmu_ctx_t *ctx, int is_64b, target_ulong pte0, pp = pte1 & 0x00000003; } if (ptem == ctx->ptem) { - if (ctx->raddr != (target_phys_addr_t)-1ULL) { + if (ctx->raddr != (a_target_phys_addr)-1ULL) { /* all matches should have equal RPN, WIMG & PP */ if ((ctx->raddr & mmask) != (pte1 & mmask)) { qemu_log("Bad RPN/WIMG/PP\n"); @@ -259,21 +259,21 @@ static inline int _pte_check(mmu_ctx_t *ctx, int is_64b, target_ulong pte0, return ret; } -static inline int pte32_check(mmu_ctx_t *ctx, target_ulong pte0, +static inline int pte32_check(a_mmu_ctx *ctx, target_ulong pte0, target_ulong pte1, int h, int rw, int type) { return _pte_check(ctx, 0, pte0, pte1, h, rw, type); } #if defined(TARGET_PPC64) -static inline int pte64_check(mmu_ctx_t *ctx, target_ulong pte0, +static inline int pte64_check(a_mmu_ctx *ctx, target_ulong pte0, target_ulong pte1, int h, int rw, int type) { return _pte_check(ctx, 1, pte0, pte1, h, rw, type); } #endif -static inline int pte_update_flags(mmu_ctx_t *ctx, target_ulong *pte1p, +static inline int pte_update_flags(a_mmu_ctx *ctx, target_ulong *pte1p, int ret, int rw) { int store = 0; @@ -317,7 +317,7 @@ static inline int ppc6xx_tlb_getnum(CPUState *env, target_ulong eaddr, int way, static inline void ppc6xx_tlb_invalidate_all(CPUState *env) { - ppc6xx_tlb_t *tlb; + a_ppc6xx_tlb *tlb; int nr, max; //LOG_SWTLB("Invalidate all TLBs\n"); @@ -337,7 +337,7 @@ static inline void __ppc6xx_tlb_invalidate_virt(CPUState *env, int is_code, int match_epn) { #if !defined(FLUSH_ALL_TLBS) - ppc6xx_tlb_t *tlb; + a_ppc6xx_tlb *tlb; int way, nr; /* Invalidate ITLB + DTLB, all ways */ @@ -366,7 +366,7 @@ static inline void ppc6xx_tlb_invalidate_virt(CPUState *env, void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code, target_ulong pte0, target_ulong pte1) { - ppc6xx_tlb_t *tlb; + a_ppc6xx_tlb *tlb; int nr; nr = ppc6xx_tlb_getnum(env, EPN, way, is_code); @@ -382,10 +382,10 @@ void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code, env->last_way = way; } -static inline int ppc6xx_tlb_check(CPUState *env, mmu_ctx_t *ctx, +static inline int ppc6xx_tlb_check(CPUState *env, a_mmu_ctx *ctx, target_ulong eaddr, int rw, int access_type) { - ppc6xx_tlb_t *tlb; + a_ppc6xx_tlb *tlb; int nr, best, way; int ret; @@ -494,7 +494,7 @@ static inline void bat_601_size_prot(CPUState *env, target_ulong *blp, *protp = prot; } -static inline int get_bat(CPUState *env, mmu_ctx_t *ctx, target_ulong virtual, +static inline int get_bat(CPUState *env, a_mmu_ctx *ctx, target_ulong virtual, int rw, int type) { target_ulong *BATlt, *BATut, *BATu, *BATl; @@ -571,7 +571,7 @@ static inline int get_bat(CPUState *env, mmu_ctx_t *ctx, target_ulong virtual, } /* PTE table lookup */ -static inline int _find_pte(mmu_ctx_t *ctx, int is_64b, int h, int rw, +static inline int _find_pte(a_mmu_ctx *ctx, int is_64b, int h, int rw, int type, int target_page_bits) { target_ulong base, pte0, pte1; @@ -653,21 +653,21 @@ static inline int _find_pte(mmu_ctx_t *ctx, int is_64b, int h, int rw, return ret; } -static inline int find_pte32(mmu_ctx_t *ctx, int h, int rw, int type, +static inline int find_pte32(a_mmu_ctx *ctx, int h, int rw, int type, int target_page_bits) { return _find_pte(ctx, 0, h, rw, type, target_page_bits); } #if defined(TARGET_PPC64) -static inline int find_pte64(mmu_ctx_t *ctx, int h, int rw, int type, +static inline int find_pte64(a_mmu_ctx *ctx, int h, int rw, int type, int target_page_bits) { return _find_pte(ctx, 1, h, rw, type, target_page_bits); } #endif -static inline int find_pte(CPUState *env, mmu_ctx_t *ctx, int h, int rw, +static inline int find_pte(CPUState *env, a_mmu_ctx *ctx, int h, int rw, int type, int target_page_bits) { #if defined(TARGET_PPC64) @@ -679,13 +679,13 @@ static inline int find_pte(CPUState *env, mmu_ctx_t *ctx, int h, int rw, } #if defined(TARGET_PPC64) -static ppc_slb_t *slb_get_entry(CPUPPCState *env, int nr) +static a_ppc_slb *slb_get_entry(CPUPPCState *env, int nr) { - ppc_slb_t *retval = &env->slb[nr]; + a_ppc_slb *retval = &env->slb[nr]; #if 0 // XXX implement bridge mode? if (env->spr[SPR_ASR] & 1) { - target_phys_addr_t sr_base; + a_target_phys_addr sr_base; sr_base = env->spr[SPR_ASR] & 0xfffffffffffff000; sr_base += (12 * nr); @@ -698,9 +698,9 @@ static ppc_slb_t *slb_get_entry(CPUPPCState *env, int nr) return retval; } -static void slb_set_entry(CPUPPCState *env, int nr, ppc_slb_t *slb) +static void slb_set_entry(CPUPPCState *env, int nr, a_ppc_slb *slb) { - ppc_slb_t *entry = &env->slb[nr]; + a_ppc_slb *entry = &env->slb[nr]; if (slb == entry) return; @@ -709,12 +709,12 @@ static void slb_set_entry(CPUPPCState *env, int nr, ppc_slb_t *slb) entry->tmp = slb->tmp; } -static inline int slb_is_valid(ppc_slb_t *slb) +static inline int slb_is_valid(a_ppc_slb *slb) { return (int)(slb->tmp64 & 0x0000000008000000ULL); } -static inline void slb_invalidate(ppc_slb_t *slb) +static inline void slb_invalidate(a_ppc_slb *slb) { slb->tmp64 &= ~0x0000000008000000ULL; } @@ -730,7 +730,7 @@ static inline int slb_lookup(CPUPPCState *env, target_ulong eaddr, LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr); mask = 0x0000000000000000ULL; /* Avoid gcc warning */ for (n = 0; n < env->slb_nr; n++) { - ppc_slb_t *slb = slb_get_entry(env, n); + a_ppc_slb *slb = slb_get_entry(env, n); LOG_SLB("%s: seg %d %016" PRIx64 " %08" PRIx32 "\n", __func__, n, slb->tmp64, slb->tmp); @@ -768,7 +768,7 @@ void ppc_slb_invalidate_all (CPUPPCState *env) do_invalidate = 0; /* XXX: Warning: slbia never invalidates the first segment */ for (n = 1; n < env->slb_nr; n++) { - ppc_slb_t *slb = slb_get_entry(env, n); + a_ppc_slb *slb = slb_get_entry(env, n); if (slb_is_valid(slb)) { slb_invalidate(slb); @@ -792,7 +792,7 @@ void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0) n = slb_lookup(env, T0, &vsid, &page_mask, &attr, NULL); if (n >= 0) { - ppc_slb_t *slb = slb_get_entry(env, n); + a_ppc_slb *slb = slb_get_entry(env, n); if (slb_is_valid(slb)) { slb_invalidate(slb); @@ -809,7 +809,7 @@ void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0) target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr) { target_ulong rt; - ppc_slb_t *slb = slb_get_entry(env, slb_nr); + a_ppc_slb *slb = slb_get_entry(env, slb_nr); if (slb_is_valid(slb)) { /* SLB entry is valid */ @@ -829,7 +829,7 @@ target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr) void ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs) { - ppc_slb_t *slb; + a_ppc_slb *slb; uint64_t vsid; uint64_t esid; @@ -855,18 +855,18 @@ void ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs) #endif /* defined(TARGET_PPC64) */ /* Perform segment based translation */ -static inline target_phys_addr_t get_pgaddr(target_phys_addr_t sdr1, +static inline a_target_phys_addr get_pgaddr(a_target_phys_addr sdr1, int sdr_sh, - target_phys_addr_t hash, - target_phys_addr_t mask) + a_target_phys_addr hash, + a_target_phys_addr mask) { - return (sdr1 & ((target_phys_addr_t)(-1ULL) << sdr_sh)) | (hash & mask); + return (sdr1 & ((a_target_phys_addr)(-1ULL) << sdr_sh)) | (hash & mask); } -static inline int get_segment(CPUState *env, mmu_ctx_t *ctx, +static inline int get_segment(CPUState *env, a_mmu_ctx *ctx, target_ulong eaddr, int rw, int type) { - target_phys_addr_t sdr, hash, mask, sdr_mask, htab_mask; + a_target_phys_addr sdr, hash, mask, sdr_mask, htab_mask; target_ulong sr, vsid, vsid_mask, pgidx, page_mask; #if defined(TARGET_PPC64) int attr; @@ -958,7 +958,7 @@ static inline int get_segment(CPUState *env, mmu_ctx_t *ctx, ctx->ptem = (vsid << 7) | (pgidx >> 10); } /* Initialize real address with an invalid value */ - ctx->raddr = (target_phys_addr_t)-1ULL; + ctx->raddr = (a_target_phys_addr)-1ULL; if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx || env->mmu_model == POWERPC_MMU_SOFT_74xx)) { /* Software TLB search */ @@ -985,7 +985,7 @@ static inline int get_segment(CPUState *env, mmu_ctx_t *ctx, } #if defined (DUMP_PAGE_TABLES) if (qemu_log_enabled()) { - target_phys_addr_t curaddr; + a_target_phys_addr curaddr; uint32_t a0, a1, a2, a3; qemu_log("Page table: " TARGET_FMT_plx " len " TARGET_FMT_plx "\n", sdr, mask + 0x80); @@ -1049,8 +1049,8 @@ static inline int get_segment(CPUState *env, mmu_ctx_t *ctx, } /* Generic TLB check function for embedded PowerPC implementations */ -static inline int ppcemb_tlb_check(CPUState *env, ppcemb_tlb_t *tlb, - target_phys_addr_t *raddrp, +static inline int ppcemb_tlb_check(CPUState *env, a_ppcemb_tlb *tlb, + a_target_phys_addr *raddrp, target_ulong address, uint32_t pid, int ext, int i) { @@ -1075,7 +1075,7 @@ static inline int ppcemb_tlb_check(CPUState *env, ppcemb_tlb_t *tlb, #if (TARGET_PHYS_ADDR_BITS >= 36) if (ext) { /* Extend the physical address to 36 bits */ - *raddrp |= (target_phys_addr_t)(tlb->RPN & 0xF) << 32; + *raddrp |= (a_target_phys_addr)(tlb->RPN & 0xF) << 32; } #endif @@ -1085,8 +1085,8 @@ static inline int ppcemb_tlb_check(CPUState *env, ppcemb_tlb_t *tlb, /* Generic TLB search function for PowerPC embedded implementations */ int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid) { - ppcemb_tlb_t *tlb; - target_phys_addr_t raddr; + a_ppcemb_tlb *tlb; + a_target_phys_addr raddr; int i, ret; /* Default return value is no match */ @@ -1105,7 +1105,7 @@ int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid) /* Helpers specific to PowerPC 40x implementations */ static inline void ppc4xx_tlb_invalidate_all(CPUState *env) { - ppcemb_tlb_t *tlb; + a_ppcemb_tlb *tlb; int i; for (i = 0; i < env->nb_tlb; i++) { @@ -1119,8 +1119,8 @@ static inline void ppc4xx_tlb_invalidate_virt(CPUState *env, target_ulong eaddr, uint32_t pid) { #if !defined(FLUSH_ALL_TLBS) - ppcemb_tlb_t *tlb; - target_phys_addr_t raddr; + a_ppcemb_tlb *tlb; + a_target_phys_addr raddr; target_ulong page, end; int i; @@ -1139,15 +1139,15 @@ static inline void ppc4xx_tlb_invalidate_virt(CPUState *env, #endif } -static int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx, +static int mmu40x_get_physical_address (CPUState *env, a_mmu_ctx *ctx, target_ulong address, int rw, int access_type) { - ppcemb_tlb_t *tlb; - target_phys_addr_t raddr; + a_ppcemb_tlb *tlb; + a_target_phys_addr raddr; int i, ret, zsel, zpr, pr; ret = -1; - raddr = (target_phys_addr_t)-1ULL; + raddr = (a_target_phys_addr)-1ULL; pr = msr_pr; for (i = 0; i < env->nb_tlb; i++) { tlb = &env->tlb[i].tlbe; @@ -1208,16 +1208,16 @@ void store_40x_sler (CPUPPCState *env, uint32_t val) env->spr[SPR_405_SLER] = val; } -static int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx, +static int mmubooke_get_physical_address (CPUState *env, a_mmu_ctx *ctx, target_ulong address, int rw, int access_type) { - ppcemb_tlb_t *tlb; - target_phys_addr_t raddr; + a_ppcemb_tlb *tlb; + a_target_phys_addr raddr; int i, prot, ret; ret = -1; - raddr = (target_phys_addr_t)-1ULL; + raddr = (a_target_phys_addr)-1ULL; for (i = 0; i < env->nb_tlb; i++) { tlb = &env->tlb[i].tlbe; if (ppcemb_tlb_check(env, tlb, &raddr, address, @@ -1254,7 +1254,7 @@ static int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx, return ret; } -static inline int check_physical(CPUState *env, mmu_ctx_t *ctx, +static inline int check_physical(CPUState *env, a_mmu_ctx *ctx, target_ulong eaddr, int rw) { int in_plb, ret; @@ -1320,7 +1320,7 @@ static inline int check_physical(CPUState *env, mmu_ctx_t *ctx, return ret; } -int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr, +int get_physical_address (CPUState *env, a_mmu_ctx *ctx, target_ulong eaddr, int rw, int access_type) { int ret; @@ -1384,9 +1384,9 @@ int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr, return ret; } -target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr) +a_target_phys_addr cpu_get_phys_page_debug (CPUState *env, target_ulong addr) { - mmu_ctx_t ctx; + a_mmu_ctx ctx; if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT) != 0)) return -1; @@ -1398,7 +1398,7 @@ target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr) int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, int mmu_idx, int is_softmmu) { - mmu_ctx_t ctx; + a_mmu_ctx ctx; int access_type; int ret = 0; @@ -2800,7 +2800,7 @@ void cpu_ppc_reset (void *opaque) CPUPPCState *cpu_ppc_init (const char *cpu_model) { CPUPPCState *env; - const ppc_def_t *def; + const a_ppc_def *def; def = cpu_ppc_find_by_name(cpu_model); if (!def) diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 5cf6cd4501..ad5d075e02 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -94,7 +94,7 @@ DEF_HELPER_1(frsqrte, i64, i64) DEF_HELPER_3(fsel, i64, i64, i64, i64) #define dh_alias_avr ptr -#define dh_ctype_avr ppc_avr_t * +#define dh_ctype_avr union ppc_avr * DEF_HELPER_3(vaddubm, void, avr, avr, avr) DEF_HELPER_3(vadduhm, void, avr, avr, avr) diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c index e3bd29cc10..e6cec76491 100644 --- a/target-ppc/op_helper.c +++ b/target-ppc/op_helper.c @@ -1782,7 +1782,7 @@ target_ulong helper_divso (target_ulong arg1, target_ulong arg2) #if !defined (CONFIG_USER_ONLY) target_ulong helper_rac (target_ulong addr) { - mmu_ctx_t ctx; + a_mmu_ctx ctx; int nb_BATs; target_ulong ret = 0; @@ -1996,7 +1996,7 @@ SATCVT(sd, uw, int64_t, uint32_t, 0, UINT32_MAX, 1, 1) #undef SATCVT #define LVE(name, access, swap, element) \ - void helper_##name (ppc_avr_t *r, target_ulong addr) \ + void helper_##name (union ppc_avr *r, target_ulong addr) \ { \ size_t n_elems = ARRAY_SIZE(r->element); \ int adjust = HI_IDX*(n_elems-1); \ @@ -2015,7 +2015,7 @@ LVE(lvewx, ldl, bswap32, u32) #undef I #undef LVE -void helper_lvsl (ppc_avr_t *r, target_ulong sh) +void helper_lvsl (union ppc_avr *r, target_ulong sh) { int i, j = (sh & 0xf); @@ -2024,7 +2024,7 @@ void helper_lvsl (ppc_avr_t *r, target_ulong sh) } } -void helper_lvsr (ppc_avr_t *r, target_ulong sh) +void helper_lvsr (union ppc_avr *r, target_ulong sh) { int i, j = 0x10 - (sh & 0xf); @@ -2034,7 +2034,7 @@ void helper_lvsr (ppc_avr_t *r, target_ulong sh) } #define STVE(name, access, swap, element) \ - void helper_##name (ppc_avr_t *r, target_ulong addr) \ + void helper_##name (union ppc_avr *r, target_ulong addr) \ { \ size_t n_elems = ARRAY_SIZE(r->element); \ int adjust = HI_IDX*(n_elems-1); \ @@ -2053,7 +2053,7 @@ STVE(stvewx, stl, bswap32, u32) #undef I #undef LVE -void helper_mtvscr (ppc_avr_t *r) +void helper_mtvscr (union ppc_avr *r) { #if defined(HOST_WORDS_BIGENDIAN) env->vscr = r->u32[3]; @@ -2063,7 +2063,7 @@ void helper_mtvscr (ppc_avr_t *r) set_flush_to_zero(vscr_nj, &env->vec_status); } -void helper_vaddcuw (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) +void helper_vaddcuw (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b) { int i; for (i = 0; i < ARRAY_SIZE(r->u32); i++) { @@ -2071,13 +2071,13 @@ void helper_vaddcuw (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) } } -#define VARITH_DO(name, op, element) \ -void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \ -{ \ - int i; \ - for (i = 0; i < ARRAY_SIZE(r->element); i++) { \ - r->element[i] = a->element[i] op b->element[i]; \ - } \ +#define VARITH_DO(name, op, element) \ +void helper_v##name (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b) \ +{ \ + int i; \ + for (i = 0; i < ARRAY_SIZE(r->element); i++) { \ + r->element[i] = a->element[i] op b->element[i]; \ + } \ } #define VARITH(suffix, element) \ VARITH_DO(add##suffix, +, element) \ @@ -2089,7 +2089,7 @@ VARITH(uwm, u32) #undef VARITH #define VARITHFP(suffix, func) \ - void helper_v##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \ + void helper_v##suffix (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b)\ { \ int i; \ for (i = 0; i < ARRAY_SIZE(r->f); i++) { \ @@ -2109,7 +2109,7 @@ VARITHFP(subfp, float32_sub) } #define VARITHSAT_DO(name, op, optype, cvt, element) \ - void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \ + void helper_v##name (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b) \ { \ int sat = 0; \ int i; \ @@ -2142,7 +2142,7 @@ VARITHSAT_UNSIGNED(w, u32, uint64_t, cvtsduw) #undef VARITHSAT_UNSIGNED #define VAVG_DO(name, element, etype) \ - void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \ + void helper_v##name (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b)\ { \ int i; \ for (i = 0; i < ARRAY_SIZE(r->element); i++) { \ @@ -2161,7 +2161,7 @@ VAVG(w, s32, int64_t, u32, uint64_t) #undef VAVG #define VCF(suffix, cvt, element) \ - void helper_vcf##suffix (ppc_avr_t *r, ppc_avr_t *b, uint32_t uim) \ + void helper_vcf##suffix (union ppc_avr *r, union ppc_avr *b, uint32_t uim) \ { \ int i; \ for (i = 0; i < ARRAY_SIZE(r->f); i++) { \ @@ -2174,7 +2174,7 @@ VCF(sx, int32_to_float32, s32) #undef VCF #define VCMP_DO(suffix, compare, element, record) \ - void helper_vcmp##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \ + void helper_vcmp##suffix (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b) \ { \ uint32_t ones = (uint32_t)-1; \ uint32_t all = ones; \ @@ -2210,7 +2210,7 @@ VCMP(gtsw, >, s32) #undef VCMP #define VCMPFP_DO(suffix, compare, order, record) \ - void helper_vcmp##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \ + void helper_vcmp##suffix (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b) \ { \ uint32_t ones = (uint32_t)-1; \ uint32_t all = ones; \ @@ -2243,7 +2243,7 @@ VCMPFP(gtfp, ==, float_relation_greater) #undef VCMPFP_DO #undef VCMPFP -static inline void vcmpbfp_internal(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, +static inline void vcmpbfp_internal(union ppc_avr *r, union ppc_avr *a, union ppc_avr *b, int record) { int i; @@ -2267,18 +2267,18 @@ static inline void vcmpbfp_internal(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, } } -void helper_vcmpbfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) +void helper_vcmpbfp (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b) { vcmpbfp_internal(r, a, b, 0); } -void helper_vcmpbfp_dot (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) +void helper_vcmpbfp_dot (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b) { vcmpbfp_internal(r, a, b, 1); } #define VCT(suffix, satcvt, element) \ - void helper_vct##suffix (ppc_avr_t *r, ppc_avr_t *b, uint32_t uim) \ + void helper_vct##suffix (union ppc_avr *r, union ppc_avr *b, uint32_t uim) \ { \ int i; \ int sat = 0; \ @@ -2304,7 +2304,7 @@ VCT(uxs, cvtsduw, u32) VCT(sxs, cvtsdsw, s32) #undef VCT -void helper_vmaddfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) +void helper_vmaddfp (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b, union ppc_avr *c) { int i; for (i = 0; i < ARRAY_SIZE(r->f); i++) { @@ -2322,7 +2322,7 @@ void helper_vmaddfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) } } -void helper_vmhaddshs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) +void helper_vmhaddshs (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b, union ppc_avr *c) { int sat = 0; int i; @@ -2338,7 +2338,7 @@ void helper_vmhaddshs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) } } -void helper_vmhraddshs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) +void helper_vmhraddshs (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b, union ppc_avr *c) { int sat = 0; int i; @@ -2355,7 +2355,7 @@ void helper_vmhraddshs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) } #define VMINMAX_DO(name, compare, element) \ - void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \ + void helper_v##name (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b) \ { \ int i; \ for (i = 0; i < ARRAY_SIZE(r->element); i++) { \ @@ -2379,7 +2379,7 @@ VMINMAX(uw, u32) #undef VMINMAX #define VMINMAXFP(suffix, rT, rF) \ - void helper_v##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \ + void helper_v##suffix (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b) \ { \ int i; \ for (i = 0; i < ARRAY_SIZE(r->f); i++) { \ @@ -2396,7 +2396,7 @@ VMINMAXFP(minfp, a, b) VMINMAXFP(maxfp, b, a) #undef VMINMAXFP -void helper_vmladduhm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) +void helper_vmladduhm (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b, union ppc_avr *c) { int i; for (i = 0; i < ARRAY_SIZE(r->s16); i++) { @@ -2406,9 +2406,9 @@ void helper_vmladduhm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) } #define VMRG_DO(name, element, highp) \ - void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \ + void helper_v##name (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b) \ { \ - ppc_avr_t result; \ + union ppc_avr result; \ int i; \ size_t n_elems = ARRAY_SIZE(r->element); \ for (i = 0; i < n_elems/2; i++) { \ @@ -2440,7 +2440,7 @@ VMRG(w, u32) #undef MRGHI #undef MRGLO -void helper_vmsummbm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) +void helper_vmsummbm (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b, union ppc_avr *c) { int32_t prod[16]; int i; @@ -2454,7 +2454,7 @@ void helper_vmsummbm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) } } -void helper_vmsumshm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) +void helper_vmsumshm (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b, union ppc_avr *c) { int32_t prod[8]; int i; @@ -2468,7 +2468,7 @@ void helper_vmsumshm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) } } -void helper_vmsumshs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) +void helper_vmsumshs (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b, union ppc_avr *c) { int32_t prod[8]; int i; @@ -2488,7 +2488,7 @@ void helper_vmsumshs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) } } -void helper_vmsumubm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) +void helper_vmsumubm (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b, union ppc_avr *c) { uint16_t prod[16]; int i; @@ -2502,7 +2502,7 @@ void helper_vmsumubm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) } } -void helper_vmsumuhm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) +void helper_vmsumuhm (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b, union ppc_avr *c) { uint32_t prod[8]; int i; @@ -2516,7 +2516,7 @@ void helper_vmsumuhm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) } } -void helper_vmsumuhs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) +void helper_vmsumuhs (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b, union ppc_avr *c) { uint32_t prod[8]; int i; @@ -2537,7 +2537,7 @@ void helper_vmsumuhs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) } #define VMUL_DO(name, mul_element, prod_element, evenp) \ - void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \ + void helper_v##name (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b) \ { \ int i; \ VECTOR_FOR_INORDER_I(i, prod_element) { \ @@ -2558,7 +2558,7 @@ VMUL(uh, u16, u32) #undef VMUL_DO #undef VMUL -void helper_vnmsubfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) +void helper_vnmsubfp (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b, union ppc_avr *c) { int i; for (i = 0; i < ARRAY_SIZE(r->f); i++) { @@ -2577,9 +2577,9 @@ void helper_vnmsubfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) } } -void helper_vperm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) +void helper_vperm (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b, union ppc_avr *c) { - ppc_avr_t result; + union ppc_avr result; int i; VECTOR_FOR_INORDER_I (i, u8) { int s = c->u8[i] & 0x1f; @@ -2602,14 +2602,14 @@ void helper_vperm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) #else #define PKBIG 0 #endif -void helper_vpkpx (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) +void helper_vpkpx (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b) { int i, j; - ppc_avr_t result; + union ppc_avr result; #if defined(HOST_WORDS_BIGENDIAN) - const ppc_avr_t *x[2] = { a, b }; + const union ppc_avr *x[2] = { a, b }; #else - const ppc_avr_t *x[2] = { b, a }; + const union ppc_avr *x[2] = { b, a }; #endif VECTOR_FOR_INORDER_I (i, u64) { @@ -2624,13 +2624,13 @@ void helper_vpkpx (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) } #define VPK(suffix, from, to, cvt, dosat) \ - void helper_vpk##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \ + void helper_vpk##suffix (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b) \ { \ int i; \ int sat = 0; \ - ppc_avr_t result; \ - ppc_avr_t *a0 = PKBIG ? a : b; \ - ppc_avr_t *a1 = PKBIG ? b : a; \ + union ppc_avr result; \ + union ppc_avr *a0 = PKBIG ? a : b; \ + union ppc_avr *a1 = PKBIG ? b : a; \ VECTOR_FOR_INORDER_I (i, from) { \ result.to[i] = cvt(a0->from[i], &sat); \ result.to[i+ARRAY_SIZE(r->from)] = cvt(a1->from[i], &sat); \ @@ -2653,7 +2653,7 @@ VPK(uwum, u32, u16, I, 0) #undef VPK #undef PKBIG -void helper_vrefp (ppc_avr_t *r, ppc_avr_t *b) +void helper_vrefp (union ppc_avr *r, union ppc_avr *b) { int i; for (i = 0; i < ARRAY_SIZE(r->f); i++) { @@ -2664,7 +2664,7 @@ void helper_vrefp (ppc_avr_t *r, ppc_avr_t *b) } #define VRFI(suffix, rounding) \ - void helper_vrfi##suffix (ppc_avr_t *r, ppc_avr_t *b) \ + void helper_vrfi##suffix (union ppc_avr *r, union ppc_avr *b) \ { \ int i; \ float_status s = env->vec_status; \ @@ -2682,7 +2682,7 @@ VRFI(z, float_round_to_zero) #undef VRFI #define VROTATE(suffix, element) \ - void helper_vrl##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \ + void helper_vrl##suffix (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b) \ { \ int i; \ for (i = 0; i < ARRAY_SIZE(r->element); i++) { \ @@ -2696,7 +2696,7 @@ VROTATE(h, u16) VROTATE(w, u32) #undef VROTATE -void helper_vrsqrtefp (ppc_avr_t *r, ppc_avr_t *b) +void helper_vrsqrtefp (union ppc_avr *r, union ppc_avr *b) { int i; for (i = 0; i < ARRAY_SIZE(r->f); i++) { @@ -2707,13 +2707,13 @@ void helper_vrsqrtefp (ppc_avr_t *r, ppc_avr_t *b) } } -void helper_vsel (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) +void helper_vsel (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b, union ppc_avr *c) { r->u64[0] = (a->u64[0] & ~c->u64[0]) | (b->u64[0] & c->u64[0]); r->u64[1] = (a->u64[1] & ~c->u64[1]) | (b->u64[1] & c->u64[1]); } -void helper_vlogefp (ppc_avr_t *r, ppc_avr_t *b) +void helper_vlogefp (union ppc_avr *r, union ppc_avr *b) { int i; for (i = 0; i < ARRAY_SIZE(r->f); i++) { @@ -2734,7 +2734,7 @@ void helper_vlogefp (ppc_avr_t *r, ppc_avr_t *b) * shift counts are not identical. We check to make sure that they are * to conform to what real hardware appears to do. */ #define VSHIFT(suffix, leftp) \ - void helper_vs##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \ + void helper_vs##suffix (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b) \ { \ int shift = b->u8[LO_IDX*15] & 0x7; \ int doit = 1; \ @@ -2763,7 +2763,7 @@ VSHIFT(r, RIGHT) #undef RIGHT #define VSL(suffix, element) \ - void helper_vsl##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \ + void helper_vsl##suffix (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b) \ { \ int i; \ for (i = 0; i < ARRAY_SIZE(r->element); i++) { \ @@ -2777,11 +2777,11 @@ VSL(h, u16) VSL(w, u32) #undef VSL -void helper_vsldoi (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t shift) +void helper_vsldoi (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b, uint32_t shift) { int sh = shift & 0xf; int i; - ppc_avr_t result; + union ppc_avr result; #if defined(HOST_WORDS_BIGENDIAN) for (i = 0; i < ARRAY_SIZE(r->u8); i++) { @@ -2805,7 +2805,7 @@ void helper_vsldoi (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t shift) *r = result; } -void helper_vslo (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) +void helper_vslo (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b) { int sh = (b->u8[LO_IDX*0xf] >> 3) & 0xf; @@ -2826,7 +2826,7 @@ void helper_vslo (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) #define SPLAT_ELEMENT(element) (ARRAY_SIZE(r->element)-1 - _SPLAT_MASKED(element)) #endif #define VSPLT(suffix, element) \ - void helper_vsplt##suffix (ppc_avr_t *r, ppc_avr_t *b, uint32_t splat) \ + void helper_vsplt##suffix (union ppc_avr *r, union ppc_avr *b, uint32_t splat) \ { \ uint32_t s = b->element[SPLAT_ELEMENT(element)]; \ int i; \ @@ -2842,7 +2842,7 @@ VSPLT(w, u32) #undef _SPLAT_MASKED #define VSPLTI(suffix, element, splat_type) \ - void helper_vspltis##suffix (ppc_avr_t *r, uint32_t splat) \ + void helper_vspltis##suffix (union ppc_avr *r, uint32_t splat) \ { \ splat_type x = (int8_t)(splat << 3) >> 3; \ int i; \ @@ -2856,7 +2856,7 @@ VSPLTI(w, s32, int32_t) #undef VSPLTI #define VSR(suffix, element) \ - void helper_vsr##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \ + void helper_vsr##suffix (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b) \ { \ int i; \ for (i = 0; i < ARRAY_SIZE(r->element); i++) { \ @@ -2873,7 +2873,7 @@ VSR(h, u16) VSR(w, u32) #undef VSR -void helper_vsro (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) +void helper_vsro (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b) { int sh = (b->u8[LO_IDX*0xf] >> 3) & 0xf; @@ -2886,7 +2886,7 @@ void helper_vsro (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) #endif } -void helper_vsubcuw (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) +void helper_vsubcuw (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b) { int i; for (i = 0; i < ARRAY_SIZE(r->u32); i++) { @@ -2894,11 +2894,11 @@ void helper_vsubcuw (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) } } -void helper_vsumsws (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) +void helper_vsumsws (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b) { int64_t t; int i, upper; - ppc_avr_t result; + union ppc_avr result; int sat = 0; #if defined(HOST_WORDS_BIGENDIAN) @@ -2919,10 +2919,10 @@ void helper_vsumsws (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) } } -void helper_vsum2sws (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) +void helper_vsum2sws (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b) { int i, j, upper; - ppc_avr_t result; + union ppc_avr result; int sat = 0; #if defined(HOST_WORDS_BIGENDIAN) @@ -2945,7 +2945,7 @@ void helper_vsum2sws (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) } } -void helper_vsum4sbs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) +void helper_vsum4sbs (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b) { int i, j; int sat = 0; @@ -2963,7 +2963,7 @@ void helper_vsum4sbs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) } } -void helper_vsum4shs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) +void helper_vsum4shs (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b) { int sat = 0; int i; @@ -2979,7 +2979,7 @@ void helper_vsum4shs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) } } -void helper_vsum4ubs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) +void helper_vsum4ubs (union ppc_avr *r, union ppc_avr *a, union ppc_avr *b) { int i, j; int sat = 0; @@ -3005,10 +3005,10 @@ void helper_vsum4ubs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) #define UPKLO 1 #endif #define VUPKPX(suffix, hi) \ - void helper_vupk##suffix (ppc_avr_t *r, ppc_avr_t *b) \ + void helper_vupk##suffix (union ppc_avr *r, union ppc_avr *b) \ { \ int i; \ - ppc_avr_t result; \ + union ppc_avr result; \ for (i = 0; i < ARRAY_SIZE(r->u32); i++) { \ uint16_t e = b->u16[hi ? i : i+4]; \ uint8_t a = (e >> 15) ? 0xff : 0; \ @@ -3024,10 +3024,10 @@ VUPKPX(hpx, UPKHI) #undef VUPKPX #define VUPK(suffix, unpacked, packee, hi) \ - void helper_vupk##suffix (ppc_avr_t *r, ppc_avr_t *b) \ + void helper_vupk##suffix (union ppc_avr *r, union ppc_avr *b) \ { \ int i; \ - ppc_avr_t result; \ + union ppc_avr result; \ if (hi) { \ for (i = 0; i < ARRAY_SIZE(r->unpacked); i++) { \ result.unpacked[i] = b->packee[i]; \ @@ -3921,7 +3921,7 @@ static inline int booke_page_size_to_tlb(target_ulong page_size) /* Helpers for 4xx TLB management */ target_ulong helper_4xx_tlbre_lo (target_ulong entry) { - ppcemb_tlb_t *tlb; + a_ppcemb_tlb *tlb; target_ulong ret; int size; @@ -3940,7 +3940,7 @@ target_ulong helper_4xx_tlbre_lo (target_ulong entry) target_ulong helper_4xx_tlbre_hi (target_ulong entry) { - ppcemb_tlb_t *tlb; + a_ppcemb_tlb *tlb; target_ulong ret; entry &= 0x3F; @@ -3955,7 +3955,7 @@ target_ulong helper_4xx_tlbre_hi (target_ulong entry) void helper_4xx_tlbwe_hi (target_ulong entry, target_ulong val) { - ppcemb_tlb_t *tlb; + a_ppcemb_tlb *tlb; target_ulong page, end; LOG_SWTLB("%s entry %d val " TARGET_FMT_lx "\n", __func__, (int)entry, @@ -4010,7 +4010,7 @@ void helper_4xx_tlbwe_hi (target_ulong entry, target_ulong val) void helper_4xx_tlbwe_lo (target_ulong entry, target_ulong val) { - ppcemb_tlb_t *tlb; + a_ppcemb_tlb *tlb; LOG_SWTLB("%s entry %i val " TARGET_FMT_lx "\n", __func__, (int)entry, val); @@ -4039,7 +4039,7 @@ target_ulong helper_4xx_tlbsx (target_ulong address) /* PowerPC 440 TLB management */ void helper_440_tlbwe (uint32_t word, target_ulong entry, target_ulong value) { - ppcemb_tlb_t *tlb; + a_ppcemb_tlb *tlb; target_ulong EPN, RPN, size; int do_flush_tlbs; @@ -4101,7 +4101,7 @@ void helper_440_tlbwe (uint32_t word, target_ulong entry, target_ulong value) target_ulong helper_440_tlbre (uint32_t word, target_ulong entry) { - ppcemb_tlb_t *tlb; + a_ppcemb_tlb *tlb; target_ulong ret; int size; diff --git a/target-ppc/translate.c b/target-ppc/translate.c index d4e81ce89b..640016b39c 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -191,11 +191,11 @@ typedef struct DisasContext { int fpu_enabled; int altivec_enabled; int spe_enabled; - ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ + a_ppc_spr *spr_cb; /* Needed to check rights for mfspr/mtspr */ int singlestep_enabled; } DisasContext; -struct opc_handler_t { +struct opc_handler { /* invalid bits */ uint32_t inval; /* instruction type */ @@ -318,16 +318,16 @@ GEN_OPCODE(name, opc1, opc2, opc3, inval, type) #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type) -typedef struct opcode_t { +typedef struct opcode { unsigned char opc1, opc2, opc3; #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ unsigned char pad[5]; #else unsigned char pad[1]; #endif - opc_handler_t handler; + an_opc_handler handler; const char *oname; -} opcode_t; +} an_opcode; /*****************************************************************************/ /*** Instruction decoding ***/ @@ -530,7 +530,7 @@ static void gen_invalid(DisasContext *ctx) gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); } -static opc_handler_t invalid_handler = { +static an_opc_handler invalid_handler = { .inval = 0xFFFFFFFF, .type = PPC_NONE, .handler = gen_invalid, @@ -7975,7 +7975,7 @@ GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPE_DOUBLE); GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPE_DOUBLE); // GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPE_DOUBLE); // -static opcode_t opcodes[] = { +static an_opcode opcodes[] = { GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), @@ -8903,7 +8903,7 @@ void cpu_dump_statistics (CPUState *env, FILE*f, int flags) { #if defined(DO_PPC_STATISTICS) - opc_handler_t **t1, **t2, **t3, *handler; + an_opc_handler **t1, **t2, **t3, *handler; int op1, op2, op3; t1 = env->opcodes; @@ -8951,7 +8951,7 @@ static inline void gen_intermediate_code_internal(CPUState *env, int search_pc) { DisasContext ctx, *ctxp = &ctx; - opc_handler_t **table, *handler; + an_opc_handler **table, *handler; target_ulong pc_start; uint16_t *gen_opc_end; CPUBreakpoint *bp; diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 79d3b4ca9a..c7b857fa66 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -32,15 +32,15 @@ #define TODO_USER_ONLY 1 #endif -struct ppc_def_t { +struct ppc_def { const char *name; uint32_t pvr; uint32_t svr; uint64_t insns_flags; uint64_t msr_mask; - powerpc_mmu_t mmu_model; - powerpc_excp_t excp_model; - powerpc_input_t bus_model; + e_powerpc_mmu mmu_model; + e_powerpc_excp excp_model; + e_powerpc_input bus_model; uint32_t flags; int bfd_mach; void (*init_proc)(CPUPPCState *env); @@ -531,7 +531,7 @@ static inline void spr_register (CPUPPCState *env, int num, target_ulong initial_value) #endif { - ppc_spr_t *spr; + a_ppc_spr *spr; spr = &env->spr_cb[num]; if (spr->name != NULL ||env-> spr[num] != 0x00000000 || @@ -7228,7 +7228,7 @@ enum { #define POWERPC_DEF(_name, _pvr, _type) \ POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type) -static const ppc_def_t ppc_defs[] = { +static const a_ppc_def ppc_defs[] = { /* Embedded PowerPC */ /* PowerPC 401 family */ /* Generic PowerPC 401 */ @@ -8882,7 +8882,7 @@ static const ppc_def_t ppc_defs[] = { /*****************************************************************************/ /* Generic CPU instanciation routine */ -static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def) +static void init_ppc_proc (CPUPPCState *env, const a_ppc_def *def) { #if !defined(CONFIG_USER_ONLY) int i; @@ -9022,7 +9022,7 @@ static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def) int nb_tlb = env->nb_tlb; if (env->id_tlbs != 0) nb_tlb *= 2; - env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t)); + env->tlb = qemu_mallocz(nb_tlb * sizeof(union ppc_tlb)); /* Pre-compute some useful values */ env->tlb_per_way = env->nb_tlb / env->nb_ways; } @@ -9093,14 +9093,14 @@ static inline int is_indirect_opcode (void *handler) return ((unsigned long)handler & 0x03) == PPC_INDIRECT; } -static inline opc_handler_t **ind_table(void *handler) +static inline an_opc_handler **ind_table(void *handler) { - return (opc_handler_t **)((unsigned long)handler & ~3); + return (an_opc_handler **)((unsigned long)handler & ~3); } /* Instruction table creation */ /* Opcodes tables creation */ -static void fill_new_table (opc_handler_t **table, int len) +static void fill_new_table (an_opc_handler **table, int len) { int i; @@ -9108,19 +9108,19 @@ static void fill_new_table (opc_handler_t **table, int len) table[i] = &invalid_handler; } -static int create_new_table (opc_handler_t **table, unsigned char idx) +static int create_new_table (an_opc_handler **table, unsigned char idx) { - opc_handler_t **tmp; + an_opc_handler **tmp; - tmp = malloc(0x20 * sizeof(opc_handler_t)); + tmp = malloc(0x20 * sizeof(an_opc_handler)); fill_new_table(tmp, 0x20); - table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT); + table[idx] = (an_opc_handler *)((unsigned long)tmp | PPC_INDIRECT); return 0; } -static int insert_in_table (opc_handler_t **table, unsigned char idx, - opc_handler_t *handler) +static int insert_in_table (an_opc_handler **table, unsigned char idx, + an_opc_handler *handler) { if (table[idx] != &invalid_handler) return -1; @@ -9129,8 +9129,8 @@ static int insert_in_table (opc_handler_t **table, unsigned char idx, return 0; } -static int register_direct_insn (opc_handler_t **ppc_opcodes, - unsigned char idx, opc_handler_t *handler) +static int register_direct_insn (an_opc_handler **ppc_opcodes, + unsigned char idx, an_opc_handler *handler) { if (insert_in_table(ppc_opcodes, idx, handler) < 0) { printf("*** ERROR: opcode %02x already assigned in main " @@ -9145,9 +9145,9 @@ static int register_direct_insn (opc_handler_t **ppc_opcodes, return 0; } -static int register_ind_in_table (opc_handler_t **table, +static int register_ind_in_table (an_opc_handler **table, unsigned char idx1, unsigned char idx2, - opc_handler_t *handler) + an_opc_handler *handler) { if (table[idx1] == &invalid_handler) { if (create_new_table(table, idx1) < 0) { @@ -9180,9 +9180,9 @@ static int register_ind_in_table (opc_handler_t **table, return 0; } -static int register_ind_insn (opc_handler_t **ppc_opcodes, +static int register_ind_insn (an_opc_handler **ppc_opcodes, unsigned char idx1, unsigned char idx2, - opc_handler_t *handler) + an_opc_handler *handler) { int ret; @@ -9191,9 +9191,9 @@ static int register_ind_insn (opc_handler_t **ppc_opcodes, return ret; } -static int register_dblind_insn (opc_handler_t **ppc_opcodes, +static int register_dblind_insn (an_opc_handler **ppc_opcodes, unsigned char idx1, unsigned char idx2, - unsigned char idx3, opc_handler_t *handler) + unsigned char idx3, an_opc_handler *handler) { if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { printf("*** ERROR: unable to join indirect table idx " @@ -9210,7 +9210,7 @@ static int register_dblind_insn (opc_handler_t **ppc_opcodes, return 0; } -static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn) +static int register_insn (an_opc_handler **ppc_opcodes, an_opcode *insn) { if (insn->opc2 != 0xFF) { if (insn->opc3 != 0xFF) { @@ -9230,7 +9230,7 @@ static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn) return 0; } -static int test_opcode_table (opc_handler_t **table, int len) +static int test_an_opcodeable (an_opc_handler **table, int len) { int i, count, tmp; @@ -9240,7 +9240,7 @@ static int test_opcode_table (opc_handler_t **table, int len) table[i] = &invalid_handler; if (table[i] != &invalid_handler) { if (is_indirect_opcode(table[i])) { - tmp = test_opcode_table(ind_table(table[i]), 0x20); + tmp = test_an_opcodeable(ind_table(table[i]), 0x20); if (tmp == 0) { free(table[i]); table[i] = &invalid_handler; @@ -9256,16 +9256,16 @@ static int test_opcode_table (opc_handler_t **table, int len) return count; } -static void fix_opcode_tables (opc_handler_t **ppc_opcodes) +static void fix_an_opcodeables (an_opc_handler **ppc_opcodes) { - if (test_opcode_table(ppc_opcodes, 0x40) == 0) + if (test_an_opcodeable(ppc_opcodes, 0x40) == 0) printf("*** WARNING: no opcode defined !\n"); } /*****************************************************************************/ -static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def) +static int create_ppc_opcodes (CPUPPCState *env, const a_ppc_def *def) { - opcode_t *opc; + an_opcode *opc; fill_new_table(env->opcodes, 0x40); for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { @@ -9278,7 +9278,7 @@ static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def) } } } - fix_opcode_tables(env->opcodes); + fix_an_opcodeables(env->opcodes); fflush(stdout); fflush(stderr); @@ -9288,7 +9288,7 @@ static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def) #if defined(PPC_DUMP_CPU) static void dump_ppc_insns (CPUPPCState *env) { - opc_handler_t **table, *handler; + an_opc_handler **table, *handler; const char *p, *q; uint8_t opc1, opc2, opc3; @@ -9475,7 +9475,7 @@ static int gdb_set_spe_reg(CPUState *env, uint8_t *mem_buf, int n) return 0; } -int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def) +int cpu_ppc_register_internal (CPUPPCState *env, const a_ppc_def *def) { env->msr_mask = def->msr_mask; env->mmu_model = def->mmu_model; @@ -9667,9 +9667,9 @@ int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def) return 0; } -static const ppc_def_t *ppc_find_by_pvr (uint32_t pvr) +static const a_ppc_def *ppc_find_by_pvr (uint32_t pvr) { - const ppc_def_t *ret; + const a_ppc_def *ret; uint32_t pvr_rev; int i, best, match, best_match, max; @@ -9707,9 +9707,9 @@ static const ppc_def_t *ppc_find_by_pvr (uint32_t pvr) #include <ctype.h> -const ppc_def_t *cpu_ppc_find_by_name (const char *name) +const a_ppc_def *cpu_ppc_find_by_name (const char *name) { - const ppc_def_t *ret; + const a_ppc_def *ret; const char *p; int i, max, len; diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index 366e7986ed..a74dfa0208 100644 --- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -167,7 +167,7 @@ int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw, void do_interrupt(CPUSH4State * env); void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); -void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr, +void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, a_target_phys_addr addr, uint32_t mem_value); int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr); diff --git a/target-sh4/helper.c b/target-sh4/helper.c index 088d36a5f7..ac3197e4dc 100644 --- a/target-sh4/helper.c +++ b/target-sh4/helper.c @@ -53,7 +53,7 @@ int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw, return 1; } -target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) +a_target_phys_addr cpu_get_phys_page_debug(CPUState * env, target_ulong addr) { return addr; } @@ -520,7 +520,7 @@ int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw, return tlb_set_page(env, address, physical, prot, mmu_idx, is_softmmu); } -target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) +a_target_phys_addr cpu_get_phys_page_debug(CPUState * env, target_ulong addr) { target_ulong physical; int prot; @@ -574,7 +574,7 @@ void cpu_load_tlb(CPUSH4State * env) entry->tc = (uint8_t)cpu_ptea_tc(env->ptea); } -void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr, +void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, a_target_phys_addr addr, uint32_t mem_value) { int associate = addr & 0x0000080; diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index 63aead954b..e99c9b0689 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -520,7 +520,7 @@ static inline void PUT_CWP64(CPUSPARCState *env1, int cwp) #endif /* cpu-exec.c */ -void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, +void do_unassigned_access(a_target_phys_addr addr, int is_write, int is_exec, int is_asi, int size); int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); diff --git a/target-sparc/helper.c b/target-sparc/helper.c index 920432cb19..7d4811baef 100644 --- a/target-sparc/helper.c +++ b/target-sparc/helper.c @@ -36,7 +36,7 @@ static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model); /* thread support */ -static spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED; +static a_spinlock global_cpu_lock = SPIN_LOCK_UNLOCKED; void cpu_lock(void) { @@ -100,12 +100,12 @@ static const int perm_table[2][8] = { } }; -static int get_physical_address(CPUState *env, target_phys_addr_t *physical, +static int get_physical_address(CPUState *env, a_target_phys_addr *physical, int *prot, int *access_index, target_ulong address, int rw, int mmu_idx) { int access_perms = 0; - target_phys_addr_t pde_ptr; + a_target_phys_addr pde_ptr; uint32_t pde; target_ulong virt_addr; int error_code = 0, is_dirty, is_user; @@ -214,7 +214,7 @@ static int get_physical_address(CPUState *env, target_phys_addr_t *physical, /* Even if large ptes, we map only one 4KB page in the cache to avoid filling it too fast */ - *physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset; + *physical = ((a_target_phys_addr)(pde & PTE_ADDR_MASK) << 4) + page_offset; return error_code; } @@ -222,7 +222,7 @@ static int get_physical_address(CPUState *env, target_phys_addr_t *physical, int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, int mmu_idx, int is_softmmu) { - target_phys_addr_t paddr; + a_target_phys_addr paddr; target_ulong vaddr; int error_code = 0, prot, ret = 0, access_index; @@ -264,11 +264,11 @@ int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev) { - target_phys_addr_t pde_ptr; + a_target_phys_addr pde_ptr; uint32_t pde; /* Context base + context number */ - pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) + + pde_ptr = (a_target_phys_addr)(env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); pde = ldl_phys(pde_ptr); @@ -330,14 +330,14 @@ void dump_mmu(CPUState *env) { target_ulong va, va1, va2; unsigned int n, m, o; - target_phys_addr_t pde_ptr, pa; + a_target_phys_addr pde_ptr, pa; uint32_t pde; printf("MMU dump:\n"); pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); pde = ldl_phys(pde_ptr); printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n", - (target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]); + (a_target_phys_addr)env->mmuregs[1] << 4, env->mmuregs[2]); for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) { pde = mmu_probe(env, va, 2); if (pde) { @@ -370,7 +370,7 @@ void dump_mmu(CPUState *env) #else /* !TARGET_SPARC64 */ // 41 bit physical address space -static inline target_phys_addr_t ultrasparc_truncate_physical(uint64_t x) +static inline a_target_phys_addr ultrasparc_truncate_physical(uint64_t x) { return x & 0x1ffffffffffULL; } @@ -388,7 +388,7 @@ static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask) // requires virtual address mask value calculated from TTE entry size static inline int ultrasparc_tag_match(SparcTLBEntry *tlb, uint64_t address, uint64_t context, - target_phys_addr_t *physical) + a_target_phys_addr *physical) { uint64_t mask; @@ -422,7 +422,7 @@ static inline int ultrasparc_tag_match(SparcTLBEntry *tlb, } static int get_physical_address_data(CPUState *env, - target_phys_addr_t *physical, int *prot, + a_target_phys_addr *physical, int *prot, target_ulong address, int rw, int is_user) { unsigned int i; @@ -481,7 +481,7 @@ static int get_physical_address_data(CPUState *env, } static int get_physical_address_code(CPUState *env, - target_phys_addr_t *physical, int *prot, + a_target_phys_addr *physical, int *prot, target_ulong address, int is_user) { unsigned int i; @@ -527,7 +527,7 @@ static int get_physical_address_code(CPUState *env, return 1; } -static int get_physical_address(CPUState *env, target_phys_addr_t *physical, +static int get_physical_address(CPUState *env, a_target_phys_addr *physical, int *prot, int *access_index, target_ulong address, int rw, int mmu_idx) { @@ -546,7 +546,7 @@ int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, int mmu_idx, int is_softmmu) { target_ulong virt_addr, vaddr; - target_phys_addr_t paddr; + a_target_phys_addr paddr; int error_code = 0, prot, ret = 0, access_index; error_code = get_physical_address(env, &paddr, &prot, &access_index, @@ -649,15 +649,15 @@ void dump_mmu(CPUState *env) #if defined(CONFIG_USER_ONLY) -target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) +a_target_phys_addr cpu_get_phys_page_debug(CPUState *env, target_ulong addr) { return addr; } #else -target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) +a_target_phys_addr cpu_get_phys_page_debug(CPUState *env, target_ulong addr) { - target_phys_addr_t phys_addr; + a_target_phys_addr phys_addr; int prot, access_index; if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c index 8992d1c555..4a801ed444 100644 --- a/target-sparc/op_helper.c +++ b/target-sparc/op_helper.c @@ -1514,21 +1514,21 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ switch(size) { case 1: - ret = ldub_phys((target_phys_addr_t)addr - | ((target_phys_addr_t)(asi & 0xf) << 32)); + ret = ldub_phys((a_target_phys_addr)addr + | ((a_target_phys_addr)(asi & 0xf) << 32)); break; case 2: - ret = lduw_phys((target_phys_addr_t)addr - | ((target_phys_addr_t)(asi & 0xf) << 32)); + ret = lduw_phys((a_target_phys_addr)addr + | ((a_target_phys_addr)(asi & 0xf) << 32)); break; default: case 4: - ret = ldl_phys((target_phys_addr_t)addr - | ((target_phys_addr_t)(asi & 0xf) << 32)); + ret = ldl_phys((a_target_phys_addr)addr + | ((a_target_phys_addr)(asi & 0xf) << 32)); break; case 8: - ret = ldq_phys((target_phys_addr_t)addr - | ((target_phys_addr_t)(asi & 0xf) << 32)); + ret = ldq_phys((a_target_phys_addr)addr + | ((a_target_phys_addr)(asi & 0xf) << 32)); break; } break; @@ -1865,21 +1865,21 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size) { switch(size) { case 1: - stb_phys((target_phys_addr_t)addr - | ((target_phys_addr_t)(asi & 0xf) << 32), val); + stb_phys((a_target_phys_addr)addr + | ((a_target_phys_addr)(asi & 0xf) << 32), val); break; case 2: - stw_phys((target_phys_addr_t)addr - | ((target_phys_addr_t)(asi & 0xf) << 32), val); + stw_phys((a_target_phys_addr)addr + | ((a_target_phys_addr)(asi & 0xf) << 32), val); break; case 4: default: - stl_phys((target_phys_addr_t)addr - | ((target_phys_addr_t)(asi & 0xf) << 32), val); + stl_phys((a_target_phys_addr)addr + | ((a_target_phys_addr)(asi & 0xf) << 32), val); break; case 8: - stq_phys((target_phys_addr_t)addr - | ((target_phys_addr_t)(asi & 0xf) << 32), val); + stq_phys((a_target_phys_addr)addr + | ((a_target_phys_addr)(asi & 0xf) << 32), val); break; } } @@ -3672,7 +3672,7 @@ void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr) #endif #ifndef TARGET_SPARC64 -void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, +void do_unassigned_access(a_target_phys_addr addr, int is_write, int is_exec, int is_asi, int size) { CPUState *saved_env; @@ -3714,7 +3714,7 @@ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, env = saved_env; } #else -void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, +void do_unassigned_access(a_target_phys_addr addr, int is_write, int is_exec, int is_asi, int size) { #ifdef DEBUG_UNASSIGNED diff --git a/targphys.h b/targphys.h index 99ab23c7a7..2a5b1bd546 100644 --- a/targphys.h +++ b/targphys.h @@ -1,21 +1,21 @@ -/* Define target_phys_addr_t if it exists. */ +/* Define a_target_phys_addr if it exists. */ #ifndef TARGPHYS_H #define TARGPHYS_H #ifdef TARGET_PHYS_ADDR_BITS -/* target_phys_addr_t is the type of a physical address (its size can +/* a_target_phys_addr is the type of a physical address (its size can be different from 'target_ulong'). We have sizeof(target_phys_addr) = max(sizeof(unsigned long), sizeof(size_of_target_physical_address)) because we must pass a host pointer to memory operations in some cases */ #if TARGET_PHYS_ADDR_BITS == 32 -typedef uint32_t target_phys_addr_t; +typedef uint32_t a_target_phys_addr; #define TARGET_PHYS_ADDR_MAX UINT32_MAX #define TARGET_FMT_plx "%08x" #elif TARGET_PHYS_ADDR_BITS == 64 -typedef uint64_t target_phys_addr_t; +typedef uint64_t a_target_phys_addr; #define TARGET_PHYS_ADDR_MAX UINT64_MAX #define TARGET_FMT_plx "%016" PRIx64 #endif diff --git a/uboot_image.h b/uboot_image.h index 9fc2760b53..c4cc96ee87 100644 --- a/uboot_image.h +++ b/uboot_image.h @@ -152,7 +152,7 @@ typedef struct uboot_image_header { uint8_t ih_type; /* Image Type */ uint8_t ih_comp; /* Compression Type */ uint8_t ih_name[IH_NMLEN]; /* Image Name */ -} uboot_image_header_t; +} an_uboot_image_header; #endif /* __IMAGE_H__ */ @@ -186,7 +186,7 @@ enum vga_retrace_method vga_retrace_method = VGA_RETRACE_DUMB; static DisplayState *display_state; DisplayType display_type = DT_DEFAULT; const char* keyboard_layout = NULL; -ram_addr_t ram_size; +a_ram_addr ram_size; int nb_nics; NICInfo nd_table[MAX_NICS]; int vm_running; @@ -273,7 +273,7 @@ static void *boot_set_opaque; /***********************************************************/ /* x86 ISA bus support */ -target_phys_addr_t isa_mem_base = 0; +a_target_phys_addr isa_mem_base = 0; PicState2 *isa_pic; /***********************************************************/ @@ -324,13 +324,13 @@ void qemu_add_balloon_handler(QEMUBalloonEvent *func, void *opaque) qemu_balloon_event_opaque = opaque; } -void qemu_balloon(ram_addr_t target) +void qemu_balloon(a_ram_addr target) { if (qemu_balloon_event) qemu_balloon_event(qemu_balloon_event_opaque, target); } -ram_addr_t qemu_balloon_status(void) +a_ram_addr qemu_balloon_status(void) { if (qemu_balloon_event) return qemu_balloon_event(qemu_balloon_event_opaque, 0); @@ -1670,7 +1670,7 @@ static struct HCIInfo *hci_init(const char *str) static int bt_hci_parse(const char *str) { struct HCIInfo *hci; - bdaddr_t bdaddr; + a_bdaddr bdaddr; if (nb_hcis >= MAX_NICS) { fprintf(stderr, "qemu: Too many bluetooth HCIs (max %i).\n", MAX_NICS); @@ -2805,9 +2805,9 @@ static int is_dup_page(uint8_t *page, uint8_t ch) static int ram_save_block(QEMUFile *f) { - static ram_addr_t current_addr = 0; - ram_addr_t saved_addr = current_addr; - ram_addr_t addr = 0; + static a_ram_addr current_addr = 0; + a_ram_addr saved_addr = current_addr; + a_ram_addr addr = 0; int found = 0; while (addr < last_ram_offset) { @@ -2840,10 +2840,10 @@ static int ram_save_block(QEMUFile *f) static uint64_t bytes_transferred = 0; -static ram_addr_t ram_save_remaining(void) +static a_ram_addr ram_save_remaining(void) { - ram_addr_t addr; - ram_addr_t count = 0; + a_ram_addr addr; + a_ram_addr count = 0; for (addr = 0; addr < last_ram_offset; addr += TARGET_PAGE_SIZE) { if (cpu_physical_memory_get_dirty(addr, MIGRATION_DIRTY_FLAG)) @@ -2870,7 +2870,7 @@ uint64_t ram_bytes_total(void) static int ram_save_live(QEMUFile *f, int stage, void *opaque) { - ram_addr_t addr; + a_ram_addr addr; uint64_t bytes_transferred_last; double bwidth = 0; uint64_t expected_time = 0; @@ -2933,7 +2933,7 @@ static int ram_save_live(QEMUFile *f, int stage, void *opaque) static int ram_load(QEMUFile *f, void *opaque, int version_id) { - ram_addr_t addr; + a_ram_addr addr; int flags; if (version_id != 3) @@ -5038,7 +5038,7 @@ int main(int argc, char **argv, char **envp) fprintf(stderr, "qemu: at most 2047 MB RAM can be simulated\n"); exit(1); } - if (value != (uint64_t)(ram_addr_t)value) { + if (value != (uint64_t)(a_ram_addr)value) { fprintf(stderr, "qemu: ram size too large\n"); exit(1); } @@ -97,7 +97,7 @@ struct VncDisplay int lsock; DisplayState *ds; VncState *clients; - kbd_layout_t *kbd_layout; + a_kbd_layout *kbd_layout; struct VncSurface guest; /* guest visible surface (aka ds->surface) */ DisplaySurface *server; /* vnc server surface */ diff --git a/vnc_keysym.h b/vnc_keysym.h index 55cb87edec..b6893ba116 100644 --- a/vnc_keysym.h +++ b/vnc_keysym.h @@ -1,7 +1,7 @@ #include "keymaps.h" -static const name2keysym_t name2keysym[]={ +static const a_name2keysym name2keysym[]={ /* ascii */ { "space", 0x020}, { "exclam", 0x021}, |