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2017-04-14nir: Destination component count of shader_clock intrinsic is 2Boyan Ding2-2/+3
This fixes the following error when using ARB_shader_clock on i965: vec1 32 ssa_0 = intrinsic shader_clock () () () intrinsic store_var (ssa_0) (clock_retval) (3) /* wrmask=xy */ error: src->ssa->num_components == num_components (nir/nir_validate.c:204) Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Cc: mesa-stable@lists.freedesktop.org
2017-04-14radeonsi: add missing initialization for userptr buffersNicolai Hähnle1-0/+4
Fix the accounting for memory usage of userptr buffers, which has been wrong forever (or at least for a long time). Also initialize flags. Without this initialization, the sparse buffer flag might end up being set, which leads to staging buffers being used unnecessarily (and incorrectly) in transfers to or from userptr buffers. This works around VM faults that occur with the radeon kernel module when running piglit ./bin/amd_pinned_memory decrement-offset map-buffer -auto Fixes: e077c5fe6579 ("gallium/radeon: transfers and invalidation for sparse buffers") Reported-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-14radv: remove the temp descriptor set infrastructureFredrik Höglund2-76/+28
It is no longer used. Signed-off-by: Fredrik Höglund <fredrik@kde.org> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-04-14radv: use push descriptors in metaFredrik Höglund6-416/+301
Use push descriptors instead of temp descriptor sets. Signed-off-by: Fredrik Höglund <fredrik@kde.org> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-04-14radv: add private push descriptors for metaFredrik Höglund2-0/+41
This allows meta to use push descriptors without disturbing user push descriptors. radv_meta_push_descriptor_set differs from vkCmdPushDescriptorSetKHR in that partial updates are not supported; all descriptors used in subsequent draw commands must be pushed at the same time. Signed-off-by: Fredrik Höglund <fredrik@kde.org> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-04-14anv/blorp: Properly handle VK_ATTACHMENT_UNUSEDJason Ekstrand1-5/+22
The Vulkan driver was originally written under the assumption that VK_ATTACHMENT_UNUSED was basically just for depth-stencil attachments. However, the way things fell together, VK_ATTACHMENT_UNUSED can be used anywhere in the subpass description. The blorp-based clear and resolve code has a bunch of places where we walk lists of attachments and we weren't handling VK_ATTACHMENT_UNUSED everywhere. This commit should fix all of them. Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> Cc: <mesa-stable@lists.freedesktop.org>
2017-04-14anv/cmd_buffer: Use the null surface state for ATTACHMENT_UNUSEDJason Ekstrand1-2/+14
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> Cc: <mesa-stable@lists.freedesktop.org>
2017-04-14anv/cmd_buffer: Always set up a null surface stateJason Ekstrand1-31/+19
We're about to start requiring it in yet another case and calculating exactly when one is needed is starting to get prohibitively expensive. A single surface state doesn't take up that much space so we may as well create one all the time. Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> Cc: <mesa-stable@lists.freedesktop.org>
2017-04-14radeonsi: cope with missing disassemblyNicolai Hähnle1-1/+2
For robustness and testing purposes. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-14gallium/ddebug: dump missing members of pipe_draw_infoNicolai Hähnle2-0/+7
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-14radeonsi: enable ARB_shader_viewport_layer_arrayNicolai Hähnle1-1/+1
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
2017-04-14radeonsi: handle ignored LAYER and VIEWPORT_INDEX writesNicolai Hähnle1-0/+20
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
2017-04-14st/mesa: enable ARB_shader_viewport_layer_arrayNicolai Hähnle1-0/+5
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
2017-04-14tgsi: clarify TGSI_SEMANTIC_{LAYER,VIEWPORT_INDEX}Nicolai Hähnle1-0/+10
Depending on pipe caps they can be writable in all vertex processing stages, but only the output of the last stage counts. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
2017-04-14gallium: add PIPE_CAP_TGSI_TES_LAYER_VIEWPORTNicolai Hähnle17-0/+19
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
2017-04-14anv/cmd_buffer: Flush the VF cache at the top of all primariesJason Ekstrand1-0/+12
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
2017-04-14anv/blorp: Flush the texture cache in UpdateBufferJason Ekstrand1-0/+7
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
2017-04-14anv: Limit VkDeviceMemory objects to 2GBJason Ekstrand1-0/+20
Reviewed-by: Juan A. Suarez Romero <jasuarez@igalia.com>
2017-04-14intel/blorp: Add a blorp_emit_dynamic macroJason Ekstrand1-64/+50
This makes it much easier to throw together a bit of dynamic state. It also automatically handles flushing so you don't accidentally forget. Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2017-04-14swr: Enable MSAA in OpenSWR software rendererBruce Cherniak6-25/+313
This patch enables multisample antialiasing in the OpenSWR software renderer. MSAA is a proof-of-concept/work-in-progress with bug fixes and performance on the way. We wanted to get the changes out now to allow several customers to begin experimenting with MSAA in a software renderer. So as not to impact current customers, MSAA is turned off by default - previous functionality and performance remain intact. It is easily enabled via environment variables, as described below. It has only been tested with the glx-lib winsys. The intention is to enable other state-trackers, both Windows and Linux and more fully support FBOs. There are 2 environment variables that affect behavior: * SWR_MSAA_FORCE_ENABLE - force MSAA on, for apps that are not designed for MSAA... Beware, results will vary. This is mainly for testing. * SWR_MSAA_MAX_SAMPLE_COUNT - sets maximum supported number of samples (1,2,4,8,16), or 0 to disable MSAA altogether. (The default is currently 0.) Reviewed-by: George Kyriazis <george.kyriazis@intel.com>
2017-04-14swr: Removed unnecessary PIPE_BIND flags from swr_is_format_supportedBruce Cherniak1-2/+1
Removed unnecessary and probably wrong PIPE_BIND_SCANOUT and PIPE_BIND_SHARED flags in favor of check on single PIPE_BIND_DISPLAY_TARGET flag. Reference llvmpipe change <bee4c7718a3bd57e3d99f0913d9081cd13fe5fd> Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
2017-04-14swr: Align swr_context allocation to SIMD alignment.Bruce Cherniak1-2/+5
The context now contains SIMD vectors which must be aligned (specifically samplePositions in the rastState in the derived state). Failure to align can result in segv crash on unaligned memory access in vector instructions. Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
2017-04-14swr: update gallium driver docsTim Rowley2-6/+12
v2: add back scons section, mention additional built swr libraries Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-04-14radv: remove irrelevant commentGrazvydas Ignotas1-1/+1
A leftover from anv. Signed-off-by: Grazvydas Ignotas <notasas@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-04-14radv: report timestampPeriod correctlyGrazvydas Ignotas2-2/+2
The kernel returns frequency in kHz, so to convert to nanosecond interval that Vulkan uses the dividend should be 1000000.0 and not 100000.0. This fixes the GPU graph in DOOM and matches the amdgpu-pro blob. Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver" Signed-off-by: Grazvydas Ignotas <notasas@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-04-14nir/print: add compute shader infoRob Clark1-0/+13
Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2017-04-14gallium/docs: small correction about register files for atomicsRob Clark1-2/+4
These can operate on MEMORY[], in addition to BUFFER[] and IMAGE[] Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-04-14freedreno: enable draw/batch reordering by defaultRob Clark2-3/+3
Probably should have flipped the switch a long time ago, since it doesn't seem to cause any problems and is a nice perf boost in a number of cases. Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-04-14freedreno/ir3: small re-orderRob Clark1-24/+23
Small re-order of switch statement to handled op-code categories in order. Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-04-14freedreno/ir3: move 'keeps' to block levelRob Clark5-20/+22
For things like SSBOs and atomics we'll want to track this at a block level. Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-04-14freedreno/ir3: convert dynamic arrays to rallocRob Clark3-14/+8
Want to move one of these under ir3_block, so that gives a reason to migrate the remaining malloc/realloc to ralloc. Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-04-14swr: add linux to scons buildGeorge Kyriazis2-7/+2
Make swr compile for both linux and windows. Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
2017-04-14radv: make sizes & offsets 32 bit in radv_descriptor_update_template_entry.Bas Nieuwenhuizen2-7/+7
v2: Also convert the calculations. Signed-off-by: Bas Nieuwenhuizen <basni@google.com> Reviewed-by: Fredrik Höglund <fredrik@kde.org>
2017-04-13radv: Set descriptor set limits.Bas Nieuwenhuizen1-15/+29
Properly and with comments this time. Signed-off-by: Bas Nieuwenhuizen <bansi@google.com> Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-04-13radv: Increase integer sizes in descriptor sets.Bas Nieuwenhuizen1-8/+8
Needed if we want to allow them taking more than 64 KiB. The calculations of these already used 32 bits. Signed-off-by: Bas Nieuwenhuizen <basni@google.com> Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-04-14radv: support S8_UINT as a depth/stencil format.Dave Airlie1-1/+1
This enables a bunch of NotSupported CTS tests. Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-14radv: bump maxGeometryShaderInvocations.Dave Airlie1-1/+1
This bumps it to the same level as amdgpu-pro, it also moves a bunch of dEQP-VK.geometry.instanced.* from NotSupported to Pass. Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-13st/nine: Fix support for ps 1.4 dw and dz modifiersAxel Davy1-2/+2
RCP was used incorrectly to support NINED3DSPSM_DW and NINED3DSPSM_DZ. src.x was used as input instead of src.w or src.z. Fixes: https://github.com/iXit/Mesa-3D/issues/271 Signed-off-by: Axel Davy <axel.davy@ens.fr> Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2017-04-13clover: Add missing include to compat headerJan Vesely1-0/+1
Fixes build failure with LLVM 4 Fixes: a981e68c26dc4079a335101da0033185030207f6 (clover: Fix build against clang SVN >= r299965) Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2017-04-13gallium/radeon: never use staging buffers with AMD_pinned_memoryNicolai Hähnle1-2/+16
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
2017-04-13radeonsi: fix gl_BaseVertex in non-indexed drawsNicolai Hähnle3-4/+23
gl_BaseVertex is supposed to be 0 in non-indexed draws. Unfortunately, the way they're implemented, the VGT always generates indices starting at 0, and the VS prolog adds the start index. There's a VGT_INDX_OFFSET register which causes the VGT to start at a driver-defined index. However, this register cannot be written from indirect draws. So fix this unlikely case by setting a bit to tell the VS whether the draw is indexed or not, so that gl_BaseVertex can be adjusted accordingly when used. Fixes a bug in KHR-GL45.shader_draw_parameters_tests.ShaderMultiDrawArraysParameters.* Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-13radeonsi: provide VS_STATE input to all VS variantsNicolai Hähnle5-27/+18
v2: fix incorrect change in get_tcs_out_patch_stride Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-13radeonsi: change the bit-packing of LS out/TCS in dataNicolai Hähnle3-9/+14
Avoid conflicts when merging various VS state bits. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-13radeonsi: emit VS_STATE register explicitly from si_draw_vboNicolai Hähnle6-2/+27
We will merge other derived state information into this register. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-13radeonsi: extract derived tess state emit to higher levelNicolai Hähnle1-6/+7
Especially with subsequent changes, this makes it easier to see the sequence of state emits at the higher level. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-13radeonsi: drop support for TGSI_SEMANTIC_VERTEXID_NOBASENicolai Hähnle1-2/+3
It is unused. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-13radv: Add more trace points.Bas Nieuwenhuizen2-0/+3
Most trace points happen after an operation, so add a trace point at the start of the command buffer. Furthermore, add one after a CmdUpdateBuffer using CP_DMA as that didn't emit one yet. Signed-off-by: Bas Nieuwenhuizen <basni@google.com> Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-04-13radv: Ignore CmdUpdateBuffer with size 0.Bas Nieuwenhuizen1-0/+3
Signed-off-by: Bas Nieuwenhuizen <basni@google.com> Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-04-13radv: Enable query inheritance.Bas Nieuwenhuizen1-1/+1
timestamp and pipeline_statistics only do something on begin & end, so they don't need any action. Occlusion queries only do something to enable/disable and that register is set nowhere else so that doesn't need extra support either. (We technically should fix it to update the reg with the number of samples, but that hasn't happened yet, so we only change it to enable/disable counting) Signed-off-by: Bas Nieuwenhuizen <basni@google.com> Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-04-13radv: enable variableMultisampleRate.Bas Nieuwenhuizen1-1/+1
This is only relevant with 0 attachments. In that case we do nothing on subpass switch already, and the pipeline is the authoritative source of the number of samples, so this shouldn't change anything. Signed-off-by: Bas Nieuwenhuizen <basni@google.com> Reviewed-by: Dave Airlie <airlied@redhat.com>
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