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2017-03-30amdgpu/addrlib: style changes and minor cleanupsNicolai Hähnle11-84/+82
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30amdgpu/addrlib: AddrLib inheritance refactorNicolai Hähnle9-560/+675
Add one more abstraction layer into inheritance system. Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30amdgpu/addrlib: rearrange code in preparation of refactoringNicolai Hähnle4-3528/+3593
No code changes. Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30amdgpu/addrlib: add disableLinearOpt flagXavi Zhang3-3/+8
2017-03-30amdgpu/addrlib: Add GetMaxAlignmentsXavi Zhang8-1/+184
2017-03-30amdgpu/addrlib: Let Kaveri go general stereo right eye offset padding pathXavi Zhang4-54/+41
Kaveri (2-pipe) macro tiling mode table was initially set to all 4-aspect-ratio so the swizzling path did not work for it and then we chose to pad the offset. We now discover the root cause is that if ratio > 2, the swizzling path does not work. So we can safely use the same path for Kaveri.
2017-03-30amdgpu/addrlib: Rewrite tile mode optmization codeXavi Zhang5-24/+50
Note: remove reference to degrade4Space and use opt4Space instead.
2017-03-30amdgpu/addrlib: Add a flag "tcCompatible" to surface info output structure.Carlos Xiong3-15/+50
Even if surface info input flag "tcComaptible" is enabled, tc compatible may be not supported if tile split happens for depth surfaces. Add a new flag in output structure to notify client to disable tc compatible in this case.
2017-03-30amdgpu/addrlib: Make comments shorterXavi Zhang1-47/+29
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30amdgpu/addrlib: add new flag nonSplitXiaoYuan Zheng2-2/+3
Flag tcCompatible has different usage in CI and VI. Add a new flag "nonSplit" for CI.
2017-03-30amdgpu/addrlib: allow tileSplitBytes greater than row sizeXiao-Tao Zai1-1/+1
Carrizo row size is 1K, while tileSplitBytes is 2K for a 4xAA 32bpp depth surface. Remove the sanity check that tileSplitBytes must be greater than row size. There could be performance loss but may be covered by non-split depth which enables tc-compatible read.
2017-03-30amdgpu/addrlib: Change to compute TC compatible stencil infoCarlos Xiong2-65/+59
Change the logic to compute tc compatible stencil info via depth's tileIndex instead of using depth's tileInfo. So the clients can get the stencil's tileInfo computed from macroModeTable. If the stencil tileInfo is same as depth tileInfo, then stencil is tc compatible; otherwise, stencil is not tc compatible. The current suggestion is to create another stencil buffer with the tc compatible tileInfo, use depth-to-color copy to decompress and tile convert the rendered stencil to tc compoatible stencil (And use the new stencil buffer to program TC).
2017-03-30amdgpu/addrlib: rename SiAddrLib/CiAddrLib to match internal spellingNicolai Hähnle4-149/+149
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-12-21radeonsi: add Polaris12 support (v3)Junwei Zhang2-1/+3
v2: use gfxip names for llvm 4.0+ v3: use tonga for llvm <= 3.8, drop gfxip name, we can just change that we change the other asics. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2016-11-09amd/addrlib: limit fastcall/regparm to GCC i386Emil Velikov1-1/+5
The use of regparm causes an error on arm/arm64 builds with clang. fastcall is allowed, but still throws a warning. As both options only have effect on 32-bit x86 builds, limit them to that case. v2: keep the __i386__ within GCC (Nicolai) Cc: 13.0 <mesa-stable@lists.freedesktop.org> Cc: Rob Herring <robh@kernel.org> Cc: Nicolai Hähnle <nhaehnle@gmail.com> Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Rob Herring <robh@kernel.org>
2016-09-06amd/addrlib: move addrlib from amdgpu winsys to common codeDave Airlie19-0/+21745
Acked-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>