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2014-11-24MIPS: BCM47XX: Initialize bcma bus later (with mm available)Rafał Miłecki1-0/+8
Initializaion with memory allocator available will be much simpler, this will allow cleanup in the bcma code. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Acked-by: Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8234/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-22MIPS: BCM47XX: add vectored interrupt supportHauke Mehrtens1-0/+23
This adds support for vectored interrupt which is supported by the SoC using a MIPS 74K CPU like the BCM4716 and BCM4706. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6290/
2014-01-22MIPS: BCM47XX: add asmlinkage to plat_irq_dispatch()Hauke Mehrtens1-1/+1
plat_irq_dispatch() is called from asm code, add asmlinkage. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6043/
2011-08-08bcm47xx: fix irq assignment for new SoCs.Hauke Mehrtens1-0/+12
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Acked-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2007-10-11[MIPS] Add support for BCM47XX CPUs.Aurelien Jarno1-0/+55
Note that the BCM4710 does not support the wait instruction, this is not a mistake in the code. It originally comes from the OpenWrt patches. Cc: Michael Buesch <mb@bu3sch.de> Cc: Felix Fietkau <nbd@openwrt.org> Cc: Florian Schirmer <jolt@tuxbox.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>